JP5740125B2 - Semiconductor light emitting device - Google Patents

Semiconductor light emitting device Download PDF

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JP5740125B2
JP5740125B2 JP2010219985A JP2010219985A JP5740125B2 JP 5740125 B2 JP5740125 B2 JP 5740125B2 JP 2010219985 A JP2010219985 A JP 2010219985A JP 2010219985 A JP2010219985 A JP 2010219985A JP 5740125 B2 JP5740125 B2 JP 5740125B2
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light emitting
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emitting device
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江崎 瑞仙
瑞仙 江崎
雄一 山崎
雄一 山崎
酒井 忠司
忠司 酒井
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Description

本発明は、光配線等に用いる半導体発光素子関する。
The present invention relates to a semiconductor light emitting element used in the optical wiring and the like.

近年のLSIの高集積化に伴い、LSI内部の回路の微細化が進んでいる。この微細化により、配線断面積は減少し、隣接する配線間の距離が狭くなる。従って、LSI内部の配線抵抗が増大し、配線間の容量が増大する。その結果、配線抵抗と配線容量で決定される配線遅延時間が増大し、更なるLSIの高速化が困難となってくる。このようなLSIの高集積化に伴う配線遅延の問題を解決する技術として、光配線技術が注目されている。光配線技術は、光導波路を用いて光信号を伝送する方式であり、上記のような微細化に伴う配線抵抗や配線間容量の増大が発生せず、更なる動作速度の高速化が期待できる。このような光配線を用いて信号伝送を行うLSIとして、光電気混載LSIが提案されている。光電気混載LSIとは、各機能ブロックによる信号処理は電気で行われ、これらの機能ブロック間は光信号で伝送する方式を用いたLSIである。このような光電気混載LSIにおいては、信号処理が行われた電気信号を光信号に変換する素子、すなわち発光素子が必要である。発光素子の集積形態としては、光導波路の上部にウェハ接合によりレーザ構造が形成されたもの(非特許文献1)、光導波路とレーザ構造が有機膜を介して接着されたもの(非特許文献2)、基板であるSi上に直接搭載されたもの(特許文献1)がある。非特許文献1に記載の構造はレーザ構造下部に空気層を有するため、レーザ部で発生した熱を効率よく放熱することが難しく、良好な温度特性が得られていない。また、非特許文献2に記載の構造は有機膜上にレーザ素子が形成されているため、放熱性が悪く、良好な温度特性が得られない。また従来型のこれらの素子ではLSIチップに集積化するにはサイズが大きく、小型化が必要となる。現在、情報通信の急速な進展に伴い大規模集積化に向けて、光配線のLSI内への導入に向けて素子の小型化の検討が進められている。従来の屈折率差を利用して光閉じ込めを行う光導波路技術を改善する方法として、ポラリトン導波路の応用が提案されている(非特許文献1)。これは金属と誘電体との界面に局在しながら界面を伝搬する波動を利用するもので、従来の金属反射を利用する中空導波路とは原理的に異なる。表面を伝搬する波動は、電磁波の一種であり、表面プラズモンポラリトン( S u r f a c e P l a s m o n P o l a r i t o n :S P P ) 波と呼ばれる。負の誘電率側の材料として金属あるいは半導体を用いたポラリトン導波路では、可視光、通信波長帯への適用が可能であるが、伝搬損失が大きく効率があまり高くないという問題があった。近年、CdS半導体のナノロッド構造を誘電体膜/金属Ag膜上に形成することにより、SPP波を誘電体の界面に発生、CdS半導体のナノロッド構造の光導波モードとのハイブリッド化により伝搬損失を低くし、光励起のレーザ発振に成功した。しかしながら、従来型レーザと同様に素子構造の放熱性が悪く、極低温(4K)での発振に留まり、また電流駆動方式は難しく、実用化、量産化には適さない素子構造であり、大幅な改善が望まれる。 Along with the recent high integration of LSIs, the miniaturization of circuits inside the LSIs is progressing. With this miniaturization, the wiring cross-sectional area is reduced and the distance between adjacent wirings is reduced. Therefore, the wiring resistance inside the LSI increases and the capacitance between the wirings increases. As a result, the wiring delay time determined by the wiring resistance and the wiring capacitance increases, and it is difficult to further increase the speed of the LSI. Optical wiring technology has attracted attention as a technology for solving the wiring delay problem associated with high integration of LSIs. Optical wiring technology is a method of transmitting optical signals using optical waveguides, and does not increase the wiring resistance and inter-wiring capacitance due to the miniaturization as described above, and can be expected to further increase the operation speed. . An opto-electric hybrid LSI has been proposed as an LSI that performs signal transmission using such an optical wiring. An opto-electric hybrid LSI is an LSI using a method in which signal processing by each functional block is performed electrically, and an optical signal is transmitted between these functional blocks. Such an opto-electric hybrid LSI requires an element that converts an electric signal subjected to signal processing into an optical signal, that is, a light emitting element. As an integrated form of the light emitting element, a laser structure is formed by wafer bonding on the top of the optical waveguide (Non-patent Document 1), and the optical waveguide and the laser structure are bonded via an organic film (Non-patent Document 2). ), And those mounted directly on the Si substrate (Patent Document 1). Since the structure described in Non-Patent Document 1 has an air layer below the laser structure, it is difficult to efficiently dissipate the heat generated in the laser part, and good temperature characteristics are not obtained. Moreover, since the structure described in Non-Patent Document 2 has a laser element formed on the organic film, heat dissipation is poor and good temperature characteristics cannot be obtained. Further, these conventional elements are large in size and need to be miniaturized in order to be integrated on an LSI chip. Currently, along with the rapid progress of information communication, studies are being made to reduce the size of the element for the introduction of optical wiring into an LSI for large-scale integration. As a method for improving a conventional optical waveguide technique for confining light using a difference in refractive index, application of a polariton waveguide has been proposed (Non-Patent Document 1). This utilizes a wave propagating through the interface while being localized at the interface between the metal and the dielectric, and is different in principle from a conventional hollow waveguide using metal reflection. A wave propagating on the surface is a kind of electromagnetic wave, and is called a surface plasmon polariton (SurfaconePlaasmonPollanit: SPPP) wave. Polariton waveguides using metals or semiconductors as the negative dielectric constant side material can be applied to visible light and communication wavelength bands, but have a problem that propagation loss is large and efficiency is not so high. In recent years, by forming a nanorod structure of CdS semiconductor on a dielectric film / metal Ag film, an SPP wave is generated at the interface of the dielectric, and propagation loss is reduced by hybridization with the optical waveguide mode of the nanorod structure of CdS semiconductor. And we succeeded in laser oscillation with optical excitation. However, like the conventional laser, the heat dissipation of the element structure is poor, the oscillation is limited to extremely low temperature (4K), and the current driving method is difficult, and the element structure is not suitable for practical use and mass production. Improvement is desired.

特許第3391521号公報Japanese Patent No. 3391521

Optics Express, Vol. 14, Issue 20, pp. 9203-9210Optics Express, Vol. 14, Issue 20, pp. 9203-9210 Optics Express, Vol. 14, Issue 18, pp. 8154-8159Optics Express, Vol. 14, Issue 18, pp. 8154-8159

本発明は、上記問題点に鑑みてなされたもので、本発明の課題は、放熱性にすぐれ安定動作が可能な半導体発光素子を提供することにある。
The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor light-emitting element that has excellent heat dissipation and can be stably operated .

本実施形態の半導体発光素子は、Si基板と、このSi基板上に形成された、Gaを含む化合物半導体からなる発光素子を構成する半導体発光層と、前記半導体発光層上に形成された誘電体層と、前記誘電体層の上面上に形成され、複数のカーボンナノチューブを含むカーボンナノチューブ束と、前記誘電体層の底面と前記半導体発光層との間に形成された光導波路構造と、を具備し、前記複数のカーボンナノチューブの各々は、10μmの長軸方向の長さと1nm−100nmの直径とを有し、前記カーボンナノチューブ束は、前記複数のカーボンナノチューブを、50%以上の空間充填率で含み、前記カーボンナノチューブ束は、前記誘電体層に接し、前記半導体発光層からの650nmのピーク波長を有する光により前記誘電体層と前記カーボンナノチューブ束との界面に表面プラズモンポラリトンを発生させる。 The semiconductor light-emitting device of this embodiment includes a Si substrate, a semiconductor light-emitting layer that forms a light-emitting device made of a compound semiconductor containing Ga, and a dielectric formed on the semiconductor light-emitting layer. A carbon nanotube bundle formed on the top surface of the dielectric layer and including a plurality of carbon nanotubes, and an optical waveguide structure formed between the bottom surface of the dielectric layer and the semiconductor light emitting layer. Each of the plurality of carbon nanotubes has a long axis direction length of 10 μm and a diameter of 1 nm to 100 nm, and the carbon nanotube bundle has a space filling factor of 50% or more. wherein the carbon nanotube bundles, the dielectric layer in contact with said by light having a peak wavelength of 650nm from the semiconductor light-emitting layer dielectric layer and the front To generate a surface plasmon polaritons at the interface between the carbon nanotube bundles.

本発明の実施例1を説明する図。BRIEF DESCRIPTION OF THE DRAWINGS The figure explaining Example 1 of this invention. 本発明の実施例2を説明する図。The figure explaining Example 2 of this invention. 本発明の実施例1および2を説明する図。The figure explaining Example 1 and 2 of this invention.

以下に、本発明の詳細を図示の実施形態によって説明する。以下、本発明の実施形態について図面を参照して詳細に説明する。なお本発明は以下の実施の形態に限定されることなく、種々工夫して用いることが可能である。  Details of the present invention will be described below with reference to embodiments shown in the drawings. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited to the following embodiment, It can be used with various devices.

(第1の実施形態)
図1は本発明の実施形態を示す図であり、同図(a)は断面図、(b)は上面図である。Si基板上に下から順にp型コンタクト層、InAlAsクラッド層(図1ではコンタクト層とクラッド層をまとめてp型半導体層2と記す)、InAlAs/InGaAs多重量子井戸層、InAlAsクラッド層、n型InGaAsコンタクト層、InAlAsクラッド層、InGaAsガイド層(図1では各クラッド層,コンタクト層,及びガイド層をまとめてn型半導体層4と記す)からなる化合物半導体レーザ部、SiO2からなる誘電体層が形成されている。レーザ部にはp型およびn型オーミック電極6,7が形成されている。SiO2層の上にはカーボンナノチューブ(CNT)が形成されている。
(First embodiment)
1A and 1B are views showing an embodiment of the present invention, in which FIG. 1A is a sectional view and FIG. 1B is a top view. P-type contact layer in this order from below on the Si substrate 1, InAlAs cladding layer (referred to as a p-type semiconductor layer 2 are collectively in FIG. 1 the contact layer and the cladding layer), InAlAs / InGaAs multiple quantum well layer 3, InAlAs cladding layer, A compound semiconductor laser portion comprising an n-type InGaAs contact layer, InAlAs cladding layer, InGaAs guide layer (in FIG. 1, the cladding layer, contact layer, and guide layer are collectively referred to as an n-type semiconductor layer 4) , a dielectric comprising SiO 2 Layer 5 is formed. In the laser part, p-type and n-type ohmic electrodes 6 and 7 are formed. Carbon nanotubes (CNT) 8 are formed on the SiO2 layer.

半導体発光層は、ガリウム砒素(GaAs)基板を用いて,有機金属気相成長(MOCVD)法により必要な積層構造を形成した。n-GaAs基板上にn型AlGaInPクラッド層、GaInP/AlGaInP多重量子井戸活性層、p型AlGaInPクラッド層を積層した。活性層の多重量子井戸構造からのPL(Photo-Luminescence)ピーク波長が赤色の波長、約650nm になるように調整した。その後、Si基板上にMOCVD積層ウェハを貼り合わせ、エッチングによりn-GaAs基板部分を除去した。その後、リッジ導波路構造をドライエッチングにより形成した後、誘電体膜、SiO2膜を厚さ3〜5nmで成膜した。電極部分については誘電体膜を除去し、p型およびn型オーミック電極がそれぞれ形成した。その後、CNTの作製は、以下の手順により行われた。はじめに下地層100の側壁面に触媒となる金属(Co, Fe, Ni等)を堆積した後、斜めミリングで不要部分の触媒/下地層100を除去した。その後、プラズマCVD法によりCNTが触媒/下地層100に選択成長され、横方向に長さ約10μmのCNTが、直径1-100nm、アスペクト比10以上のナノロッドが空間充填率50%以上で形成された(図3参照)。
For the semiconductor light emitting layer, a gallium arsenide (GaAs) substrate was used, and a necessary laminated structure was formed by metal organic chemical vapor deposition (MOCVD). An n-type AlGaInP clad layer, a GaInP / AlGaInP multiple quantum well active layer, and a p-type AlGaInP clad layer were stacked on an n-GaAs substrate. The PL (Photo-Luminescence) peak wavelength from the multiple quantum well structure of the active layer was adjusted to be a red wavelength of about 650 nm. Thereafter, the MOCVD laminated wafer was bonded onto the Si substrate, and the n-GaAs substrate portion was removed by etching. Thereafter, a ridge waveguide structure was formed by dry etching, and then a dielectric film and a SiO2 film were formed to a thickness of 3 to 5 nm. For the electrode portion, the dielectric film was removed to form p-type and n-type ohmic electrodes, respectively. Thereafter, the production of CNTs was performed according to the following procedure. First, a metal (Co, Fe, Ni, etc.) serving as a catalyst was deposited on the side wall surface of the underlayer 100 , and then the unnecessary portion of the catalyst / underlayer 100 was removed by oblique milling. Thereafter, CNTs are selectively grown on the catalyst / underlayer 100 by plasma CVD, and CNTs having a length of about 10 μm in the lateral direction are formed with nanorods having a diameter of 1-100 nm and an aspect ratio of 10 or more with a space filling ratio of 50% or more. (See FIG. 3).

このようにして作製された発光素子は、誘電体層とCNTの界面に表面プラズモンポラリトンが発生、光波長以下に光が閉じ込められ且つ高強度の電界強度が得られることで、従来難しかった電流駆動方式で波長650nmでの室温発振が得られた。発光素子がSi基板上に形成されているため放熱性に優れ、室温動作が可能となった。これにより、発光素子と導波路を一体化した高効率低消費エネルギーの光配線デバイスの実現が期待できる。   In the light-emitting device fabricated in this way, surface plasmon polaritons are generated at the interface between the dielectric layer and the CNT, light is confined below the light wavelength, and high electric field strength is obtained, which is difficult to drive by current. Room temperature oscillation at a wavelength of 650 nm was obtained by the method. Since the light-emitting element is formed on the Si substrate, it has excellent heat dissipation and can be operated at room temperature. As a result, it is expected to realize a highly efficient and low energy consumption optical wiring device in which a light emitting element and a waveguide are integrated.

本実施例では、半導体発光層の活性層として、InGaAlP系を用いて説明したが、それに限らず、GaInAs(N)系、AlGaAs系やInGaAsP系、InGaN系など、様々な材料を用いることもできる。クラッド層も、同様に様々な材料を用いることもできる。また、所望の形状として、本実施例では、主に円筒形状のCNTを用いて説明を行ったが、正方形、長方形、楕円などの形状においても同様に本発明の効果があることは明らかである。下地層の形状としては、CNT束と下面の誘電体層との接触面積を小さくしかつCNT密度を多くできる点で縦長の長方形や逆メサ構造が好適である。CNTの成長には、ここではプラズマCVD法を用いたが、熱CVD法でも良い。熱またはプラズマCVD法が成長箇所選択性、成長温度範囲、量産性等の観点から望ましい。またCNT束と下面の誘電体層との接触面積を小さくしかつCNT密度を多くするためには、下地層の形状としては縦長の長方形や逆メサ等が望ましい。またCNTを作製する方法としては、選択的にCNT束を成長させた後に溶液浸漬によりCNT束を倒す方法がある。選択成長領域を円形にしておけば溶液浸漬後円柱状CNT束となり、最小の面積で誘電体面と接触させることができる。溶液としては、CNTへのダメージを考慮して水、アルコール等が好ましい。また誘電体として、ここではSiO2膜を用いたが、それ以外のSiN、SiON、MgF2などの材料を用いても同様の効果が得られることは明らかである。   In this embodiment, the active layer of the semiconductor light emitting layer has been described using an InGaAlP system. However, the present invention is not limited thereto, and various materials such as a GaInAs (N) system, an AlGaAs system, an InGaAsP system, and an InGaN system can be used. . Similarly, various materials can be used for the clad layer. Further, in the present embodiment, description has been made mainly using cylindrical CNTs as the desired shape, but it is clear that the present invention is also effective in shapes such as squares, rectangles, and ellipses. . The shape of the underlayer is preferably a vertically long rectangle or a reverse mesa structure in that the contact area between the CNT bundle and the lower dielectric layer can be reduced and the CNT density can be increased. For the growth of CNTs, the plasma CVD method is used here, but a thermal CVD method may be used. Thermal or plasma CVD is desirable from the viewpoints of growth site selectivity, growth temperature range, mass productivity, and the like. Further, in order to reduce the contact area between the CNT bundle and the dielectric layer on the lower surface and increase the CNT density, the shape of the underlayer is preferably a vertically long rectangle or a reverse mesa. As a method for producing CNTs, there is a method in which a CNT bundle is selectively grown and then the CNT bundle is tilted by immersion in a solution. If the selective growth region is made circular, it becomes a cylindrical CNT bundle after solution immersion, and can be brought into contact with the dielectric surface with a minimum area. As the solution, water, alcohol or the like is preferable in consideration of damage to the CNT. Although the SiO2 film is used here as the dielectric, it is obvious that the same effect can be obtained even if other materials such as SiN, SiON, MgF2 are used.

本発明によれば、Si基板上に半導体発光層(III-V)を配置、半導体発光層上に電流注入部を有し、前記半導体の発光により誘電体層とカーボンナノチューブ乃至はグラフェン層の界面に表面プラズモンポラリトンを発生させることを特徴とする素子であり、従来よりも超小型の電流注入型の発光素子を実現できる。また発光素子がSi基板上に形成されるので、放熱性に優れ安定動作が可能となる。これにより、発光素子と導波路を一体化した高効率低消費エネルギーの光配線デバイスが提供できる。  According to the present invention, the semiconductor light emitting layer (III-V) is disposed on the Si substrate, the semiconductor light emitting layer has a current injection portion, and the interface between the dielectric layer and the carbon nanotube or the graphene layer by light emission of the semiconductor. It is an element characterized by generating surface plasmon polaritons, and an ultra-small current injection type light-emitting element can be realized. Further, since the light emitting element is formed on the Si substrate, the heat dissipation is excellent and stable operation is possible. Thereby, a highly efficient and low energy consumption optical wiring device in which the light emitting element and the waveguide are integrated can be provided.

(第2の実施形態)
次に、本発明の第2の実施形態について説明する。図2は本発明の実施形態を示す図であり、同図(a)は断面図、(b)は上面図である。図1、図3に関して前述したものと同様の要素には同一の符号を付して詳細な説明は省略する。ここでの違いは、一方の電極をSi基板面に形成している点である。ウェハ接合する前に電極形成を行った後に、半導体発光層を接合することで作製できる。その他の工程は、第1の実施形態と同様である。このようにして作製された発光素子においても誘電体層とCNTの界面に表面プラズモンポラリトンが発生、光波長以下に光が閉じ込められ且つ高強度の電界強度が得られることで、従来難しかった電流駆動方式で波長650nmでの室温発振が得られた。
(Second Embodiment)
Next, a second embodiment of the present invention will be described. 2A and 2B are views showing an embodiment of the present invention, in which FIG. 2A is a sectional view and FIG. 2B is a top view. Elements similar to those described above with reference to FIGS. 1 and 3 are given the same reference numerals, and detailed descriptions thereof are omitted. The difference here is that one electrode 7 is formed on the Si substrate surface. It can be manufactured by bonding the semiconductor light emitting layer after performing electrode formation before wafer bonding. Other steps are the same as those in the first embodiment. Even in the light-emitting device fabricated in this manner, surface plasmon polaritons are generated at the interface between the dielectric layer 5 and the CNT 8 , light is confined below the light wavelength, and high electric field strength is obtained. Room-temperature oscillation at a wavelength of 650 nm was obtained by the current driving method.

1 Si基板
型半導体層
3 半導体発光層
型半導体層
5 誘電体
電極
電極
8 CNT
10 レーザー光
1 Si substrate 2 p- type semiconductor layer 3 semiconductor light emitting layer 4 n- type semiconductor layer 5 dielectric 6 n- electrode 7 p- electrode 8 CNT
10 Laser light

Claims (4)

Si基板と、このSi基板上に形成された、Gaを含む化合物半導体からなる発光素子を構成する半導体発光層と、
前記半導体発光層上に形成された誘電体層と、
前記誘電体層の上面上に形成され、複数のカーボンナノチューブを含むカーボンナノチューブ束と、
前記誘電体層の底面と前記半導体発光層との間に形成された光導波路構造と、
を具備し、
前記複数のカーボンナノチューブの各々は、10μmの長軸方向の長さと1nm−100nmの直径とを有し、
前記カーボンナノチューブ束は、前記複数のカーボンナノチューブを、50%以上の空間充填率で含み、
前記カーボンナノチューブ束は、前記誘電体層に接し、
前記半導体発光層からの650nmのピーク波長を有する光により前記誘電体層と前記カーボンナノチューブ束との界面に表面プラズモンポラリトンを発生させる、
ことを特徴とする半導体発光素子。
A semiconductor light emitting layer constituting a light emitting element made of a compound semiconductor containing Ga, formed on the Si substrate, and a Si substrate;
A dielectric layer formed on the semiconductor light emitting layer;
A carbon nanotube bundle formed on an upper surface of the dielectric layer and including a plurality of carbon nanotubes ;
An optical waveguide structure formed between the bottom surface of the dielectric layer and the semiconductor light emitting layer;
Comprising
Each of the plurality of carbon nanotubes has a long axis direction of 10 μm and a diameter of 1 nm-100 nm,
The carbon nanotube bundle includes the plurality of carbon nanotubes at a space filling rate of 50% or more,
The carbon nanotube bundle is in contact with the dielectric layer,
Generating surface plasmon polaritons at the interface between the dielectric layer and the carbon nanotube bundle by light having a peak wavelength of 650 nm from the semiconductor light emitting layer;
A semiconductor light emitting element characterized by the above.
前記発光素子は、前記半導体発光層上に電流注入部を有することを特徴とする請求項1記載の半導体発光素子。   The semiconductor light emitting device according to claim 1, wherein the light emitting device has a current injection portion on the semiconductor light emitting layer. 前記誘電体層の一部はエッチングされ、該エッチングにより露出する前記半導体発光層に接して電極が形成されていることを特徴とする請求項1に記載の半導体発光素子。   2. The semiconductor light emitting device according to claim 1, wherein a part of the dielectric layer is etched, and an electrode is formed in contact with the semiconductor light emitting layer exposed by the etching. 前記複数のカーボンナノチューブの各々は、10以上のアスペクト比を有する、Each of the plurality of carbon nanotubes has an aspect ratio of 10 or more.
ことを特徴とする請求項1乃至3のいずれか1項に記載の半導体発光素子。The semiconductor light-emitting device according to claim 1, wherein
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