GB2596060A

GB2596060A - Optoelectronic device and method of manufacture thereof

Info

Publication number: GB2596060A
Application number: GB2008698.9A
Authority: GB
Inventors: John Zilkie Aaron; Nykänen Henri; Peters Frank; Su-Chang Tsai Charles; Yu Guomin
Original assignee: Rockley Photonics Ltd
Current assignee: Rockley Photonics Ltd
Priority date: 2020-06-09
Filing date: 2020-06-09
Publication date: 2021-12-22
Also published as: GB202008698D0

Abstract

An optoelectronic device (hybrid waveguide) comprising a SOI platform 100 including a silicon waveguide 104 in a silicon layer 101, a silicon substrate 106 (Figure 2A), and a cavity 102. A III-V semiconductor device for use in a micro transfer printing process is located within the cavity 102 and contains a III-V semiconductor waveguide rib 111 optically coupled to SOI waveguide 104. The III-V waveguide 111 is tapered and has a width in a central region smaller than in one or both end regions. A region of the cavity 102 may comprise a wave-guiding patterned surface 103 for interacting with light within the III-V waveguide 111. The patterned surface 103 may comprise a guiding region 1104 (Figure 13A) separating two other regions 1103a-b (Figure 13A), wherein the refractive index of the other regions 1103a-b is lower than the that of the guiding region 1104. A method of forming the same.

Description

OPTOELECTRONIC DEVICE AND METHOD OF MANUFACTURE THEREOF Field of the Invention The present invention relates to an optoelectronic device and method of manufacture thereof.

Background

Hybrid integration of III-V semiconductor based electro-optical devices (e.g. lasers, or modulators), with silicon-on-insulator (S01) platforms confers the advantage of combining the best parts of both material systems.

However, conventional chip bonding processes typically use flip-chip bonding, in which the III-V semiconductor based device is inverted and bonded into a cavity on the SOI platform.

This manufacturing process can be costly and have a low yield, because of the metal bumping requirements for the die bonding and difficulties in accurately controlling the alignment of the respective components.

Micro-transfer printing (MTP) is therefore being investigated as an alternative way to integrate III-V semiconductor based devices within SOI wafer. In these methods, the III-V semiconductor based device can be printed into a cavity on the SOI in the same orientation in which it was manufactured and without the need for metal bumping. The alignment between the III-V semiconductor based waveguide and the SOI waveguide is thereby predetermined in the vertical direction (z direction). The requirements for alignment are therefore reduced from three dimension to two, which can be more easily facilitated.

There is a desire to expand the number of electro-optically active components which are suitable for MTP, and also to decrease the required footprint for these devices.

In particular, it is desired to provide distributed feedback (DFB) lasing devices, as they provide stable and mode-hop free operation. However these can be costly to produce and existing techniques provide a limited yield due to the complicated fabrication processes involved, in particular associated with the need to include a grating in the III-V semiconductor device.

Further, there is a desire to generally increase the optical efficiency of optoelectronic devices fabricated through MTP processes, and include efficient thermal management and control.

Summary

Accordingly, in a first aspect, embodiments of the invention provide an optoelectronic device, comprising: a silicon-on-insulator platform, including a silicon waveguide formed in a silicon device layer, a silicon substrate, and a cavity; a III-V semiconductor based device, located within the cavity of the silicon-oninsulator platform, and containing a III-V semiconductor based waveguide which is optically coupled to the silicon waveguide; wherein a region of a bed of the cavity, located between the III-V semiconductor based device and the substrate, includes a patterned surface, which is configured to interact with an optical signal within the III-V semiconductor based waveguide of the III-V semiconductor based device.

Such an optoelectronic device can be fabricated for a relatively low cost, and at relatively high volumes. Moreover, the optoelectronic device is thinner and more compact than those known previously and can be planar to the wafer surface. Further, coupling losses between the III-V semiconductor based waveguide and the silicon waveguide can be minimised.

Optional features of the invention will now be set out. These are applicable singly or in any combination with any aspect of the invention.

The patterned surface may be adjacent to, and extend along, the III-V semiconductor based waveguide. In some examples, the III-V semiconductor based waveguide may have a surface facing the bed of the cavity and the patterned surface may share the same geometry as the surface of the waveguide facing the bed. In other examples, the patterned surface may be wider than a width of the III-V semiconductor based waveguide, and may have a length at least equal to a length of the III-V semiconductor based waveguide.

By III-V semiconductor based device, it may be meant an optically active device which comprises one or more III-V semiconductors, or an optically active device which is entirely formed from III-V semiconductors. By optically coupled, it may be meant that the light contained within the silicon waveguide can transfer to the III-V semiconductor based waveguide.

The patterned surface may be formed within the silicon device layer, which may form the bed of the cavity. In such examples, a portion of a region of the silicon device layer may have been etched away so as to provide the cavity within which the III-V semiconductor based device is located. The remaining silicon device layer may be bounded on one side by a buried oxide layer, which is located between the silicon device layer and the silicon substrate.

The patterned surface may be formed within the silicon substrate, which may form the bed of the cavity. In such example, the entirety of a region of the silicon device layer may have been etched away, as well as the entirety of a region of a buried oxide layer, so as to provide the cavity within which the III-V semiconductor based device is located.

The bed of the cavity may be formed of a dielectric, and the patterned surface may be formed within the dielectric. In such examples, either a portion or the entirety of a region of the silicon device layer may have been etched away, and subsequently the dielectric disposed within the resulting cavity. The sidewalls therefore may be provided, at least in part, by the silicon device layer, whilst the bed of the cavity is provided by the dielectric. The dielectric may be benzocyclobutene. By benzocyclobutene, it may be meant a polymer formed from benzocyclobutene. For example, the dielectric may be a BCB-based polymer dielectric.

The optoelectronic device may comprise one or more heaters, located within or on the bed of the cavity, and configured to tune an operating wavelength of the optoelectronic device. The heater may be a doped region of the bed of the cavity. The heater may be a metal strip, disposed on the bed of the cavity. The optoelectronic device may further comprise a heatsink structure, located within the bed of the cavity. The heatsink structure may be an epitaxial crystalline silicon structure. The heatsink structure may extend from the silicon device layer through a buried oxide layer to contact the silicon substrate. The heatsink structure may be formed from silicon, or metal (for example titanium or titanium nitride).

The patterned surface may be a grating, and the grating and the III-V semiconductor based device may form a distributed feedback or distributed Bragg reflector laser. The grating may be a partial grating which extends only part way along the III-V semiconductor based device, the III-V semiconductor based device being a laser. Such a partial grating can operate to enhance the spectral purity in the laser by blending the best spectral characteristics of a distributed feedback laser and Fabry-Perot laser. A distributed feedback laser, with uniform grating throughout the laser cavity, can provide a single frequency output only under a narrow range of phase conditions at the rear facet. A Fabry-Perot laser provides uniform power output regardless of phase condition at the rear facet. With a partial-grating type distributed feedback laser, the laser cavity portion without a grating allows wide-range of phase conditions at rear facet where the laser will provide single frequency output. The patterned surface may comprise a first grating region and a second grating region, spaced in a guiding direction of the III-V semiconductor based waveguide by a non-grating region. The first grating region may have a depth, into which it extends into the bed of the cavity, which is less than that of a corresponding depth of the second grating region. The first grating region may be adjacent to the silicon waveguide. The second grating region may be at a position in the bed of the cavity which is on an opposing side of the first grating region to the silicon waveguide. The second grating may function as a broadband mirror. The III-V semiconductor based device may include a high reflectively facet on a side of the III-V semiconductor based device proximal to the second grating and distal to the first grating. The III-V semiconductor based device may include an antireflective facet on a side of the III-V semiconductor based device proximal to the first grating and distal to the second grating.

In examples where the III-V semiconductor based device is a laser, there may be no oxide between the III-V semiconductor based device and the cavity.

The patterned surface may be a reflective pattern (e.g. highly reflective pattern), so as to confine an optical mode of the III-V semiconductor based waveguide to the III-V semiconductor based waveguide. The reflective pattern may be a grating having a grating period smaller than an operating wavelength of the optoelectronic device. In some examples, the operating wavelength of the optoelectronic device is 1310 nm and so the grating period is less than 1310 nm. The grating period may equal to the operating wavelength divided by twice the waveguide effective refractive index. The grating period may be between 150 nm and 300 nm inclusive.

The patterned surface may be a wave-guiding pattern. The wave-guiding pattern may comprise two regions having a first refractive index, the two regions being separated by a guiding region having a second refractive index, the first refractive index may be lower than the second refractive index. The III-V semiconductor based waveguide may be wider at one end than a width in a central region of the III-V semiconductor based waveguide, such that light travelling in the III-V semiconductor based waveguide towards the end of said waveguide is guided by the wave-guiding pattern.

In a second aspect, embodiments of the present invention provide a silicon-on-insulator platform, suitable for a micro transfer printing process used to fabricate an optoelectronic device, the silicon-on-insulator platform including; a silicon waveguide; and a cavity, a sidewall of which forms a connecting optical facet to the silicon waveguide; wherein a region of a bed of the cavity includes a patterned surface, which is configured to interact with light within a III-V semiconductor based waveguide of a III-V semiconductor based device, when the III-V semiconductor based device is bonded to the cavity.

Integration of the silicon-on-insulator platform and a simpler III-V semiconductor based device without a grating results in an optoelectronic device which can be fabricated for a relatively low cost, and at relatively high volumes. Moreover, the resulting optoelectronic device fabricated with the micro transfer printing process is thinner and more compact than previous examples, allowing for relatively precise placement accuracy allowing for coupling losses between the III-V semiconductor based waveguide and the silicon waveguide can be minimised.

The silicon-on-insulator platform of the second aspect may have any one or, to the extent that they are compatible, any combination of the optional features of the silicon-on-insulator platform of the first aspect.

The bed of the cavity may be formed of a dielectric, and the patterned surface may be formed within the dielectric. In such examples, either a portion or the entirety of a region of the silicon device layer may have been etched away, and subsequently the dielectric disposed within the resulting cavity. The sidewalls therefore may be provided, at least in part, by the silicon device layer, whilst the bed of the cavity is provided by the dielectric. The dielectric may be benzocyclobutene.

The silicon-on-insulator platform may include one or more heaters, located within or on the bed of the cavity, and configured to tune an operating wavelength of the optoelectronic device. The heater may be a doped region of the cavity. The heater may be a metal strip, disposed on the bed of the cavity. The silicon-on-insulator platform may include a heatsink structure, located within the bed of the cavity. The heatsink structure may be an epitaxial crystalline silicon structure. The heatsink structure may extend from the silicon device layer through a buried oxide layer to contact the silicon substrate. The heatsink structure may be formed from silicon, or metal (for example titanium or titanium nitride).

The patterned surface may be a grating, suitable for use with a III-V semiconductor based distributed feedback or distributed Bragg reflector laser. The grating may be a partial grating which extends only part way along the III-V semiconductor based distributed feedback or distributed Bragg reflector laser. Such a partial grating can operate to enhance the spectral purity of the laser. A patterned surface may comprise a first grating region and a second grating region, spaced in a guiding direction of the III-V semiconductor based waveguide by a non-grating region. The first grating region may have a depth, into which it extends into the bed of the cavity, which is less than that of a corresponding depth of the second grating region. The first grating region may be adjacent to the silicon waveguide. The second grating region may be at a position in the bed of the cavity which is on an opposing side of the first grating region to the silicon waveguide.

The patterned surface may be a reflective pattern, so as to confine an optical mode of the III-V semiconductor based waveguide to the III-V semiconductor based waveguide when it is bonded to the cavity. The reflective grating may be a grating having a grating period smaller than an operating wavelength of the optoelectronic device. In some examples, the operating wavelength of the optoelectronic device is 1310 nm and so the grating spacing is less than 1310 nm. The grating period may equal to the operating wavelength divided by twice the wavelength effective refractive index. The grating period may be between 150 nm and 300 nm inclusive.

The patterned surface may be a wave-guiding pattern. The wave-guiding pattern may comprise two regions having a first refractive index, the two regions being separated by a guiding region having a second refractive index, the first refractive index may be lower than the second refractive index.

In a third aspect, embodiments of the invention provide a method of preparing a silicon-oninsulator platform for a micro transfer printing process, the silicon-on-insulator platform including a silicon waveguide and a cavity, adjacent to the silicon waveguide, wherein the method comprises the steps of: etching a patterned surface into a region of a bed of the cavity, the patterned surface being configured to interact with light within a III-V semiconductor based waveguide of a III-V semiconductor based device when the III-V semiconductor based device is bonded to the cavity.

The resulting silicon-on-insulator platform can be integrated with a III-V semiconductor based device resulting in an optoelectronic device which can be fabricated for a relatively low cost, and at relatively high volumes. Moreover, the resulting optoelectronic device is more compact. Further, coupling losses between the III-V semiconductor based waveguide and the silicon waveguide can be minimised.

The method may have any one or, to the extent that they are compatible, any combination of the following optional features.

The etching step may be performed by either holographic lithography or electron-beam (E-beam) lithography.

The pattern etching step may be performed either before or after the cavity etching step.

The method may include a step of disposing a bonding layer on at least the bed of the cavity, and etching the patterned surface into the bonding layer. The bonding layer may be a dielectric layer. The dielectric layer may be formed of benzocyclobutene.

In a fourth aspect, embodiments of the present invention provide a method of fabricating an optoelectronic device, comprising the steps of: providing a silicon-on-insulator platform according to the second aspect; providing a III-V semiconductor based device, including a III-V semiconductor based waveguide; and transfer printing the III-V semiconductor based device into the cavity of the silicon-on-insulator platform.

In a fifth aspect, embodiments of the present invention provide an optoelectronic device fabricated according to the method of the fourth aspect.

In a sixth aspect, embodiments of the present invention provide a silicon-on-insulator platform, suitable for a micro transfer printing process used to fabricate an optoelectronic device, the silicon-on-insulator platform including: a silicon waveguide; and a cavity, a sidewall of which forms a connecting optical facet to the silicon waveguide; wherein a region of a bed of the cavity includes a heatsink structure.

The heatsink structure may extend from the region of the bed of the cavity, through an insulation layer of the silicon-on-insulator platform so as to contact a silicon substrate.

The heatsink structure may be formed from epitaxial crystalline silicon. The heatsink structure may be formed from titanium or titanium nitride.

The heatsink structure may be a via extending through the region of the bed of the cavity.

The silicon-on-insulator platform may comprise two heatsink structures, located on opposing sides of a bonding region in the bed of the cavity.

A bonding region in the bed of the cavity may include a patterned surface, which is configured to interact with light within a III-V semiconductor based waveguide of a III-V semiconductor based device, when the III-V semiconductor based device is bonded to the cavity.

The silicon-on-insulator platform may further comprise one or more heaters, on a region of the bed of the cavity.

The one or more heaters may be located between the or each heatsink structure and a bonding region in the bed of the cavity to which a III-V semiconductor based device is to be bonded.

In a seventh aspect, embodiments of the invention provide an optoelectronic device comprising the silicon-on-insulator platform of the sixth aspect, and a III-V semiconductor based device bonded to the bed of the cavity.

In an eighth aspect, embodiments of the present invention provide a method of preparing a silicon-on-insulator platform for a micro transfer printing process, the silicon-on-insulator platform including a silicon waveguide and a cavity adjacent to the silicon waveguide, wherein the method comprises the step of: providing a heatsink structure in a bed of the cavity.

Providing the heatsink structure may include etching a portion of the bed, and growing the heatsink structure into the etched portion.

The etch may be performed to remove both a silicon-on-insulator layer and an insulating layer of the silicon-on-insulator platform, and the heatsink structure may be grown from a substrate of the silicon-on-insulator platform.

In a ninth aspect, embodiments of the invention provide a silicon-on-insulator platform, suitable for a micro transfer printing process used to fabricate an optoelectronic device, the silicon-on-insulator platform including: a silicon waveguide; and a cavity, a sidewall of which forms a connecting optical facet to the silicon waveguide; wherein one or more sidewalls of the cavity contain a thermally isolating cavity which extends from an upper surface of the silicon-on-insulator platform at least partially through the platform.

The or each cavity may extend through an insulator layer of the platform. The or each cavity may extend partially into a substrate of the platform.

Two opposing sidewalls of the cavity may contain thermally isolating cavities. Neither opposing sidewall of the cavity may contain a connecting optical facet.

The cavity may be rectangular, and the opposing sidewalls may be those on the longer side of the rectangular cavity.

Three of four sidewalls of the cavity may contain thermally isolating cavities.

The thermally isolating cavities may extend along a longitudinal axis of the cavity.

In a tenth aspect, embodiments of the invention provide an optoelectronic device, comprising the silicon-on-insulator platform of the ninth aspect, and a III-V semiconductor based device coupon bonded to the bed of the cavity.

In an eleventh aspect, embodiments of the invention provide a method of preparing a silicon-on-insulator platform for a micro transfer printing process, the silicon-on-insulator platform including a silicon waveguide and a cavity, adjacent to the silicon waveguide, wherein the method comprises the step of: providing one or more thermally isolating cavities in one or more sidewalls of the cavity.

Providing the one or more thermally isolating cavities in the one or more sidewalls of the cavity may include performing an etching step which extends at least through a silicon-oninsulator layer of the silicon-on-insulator platform. The etch may extend through an insulating layer of the silicon-on-insulator platform.

In an twelfth aspect, embodiments of the invention provide a silicon-on-insulator platform, suitable for a micro transfer printing process used to fabricate an optoelectronic device, the silicon-on-insulator platform including: a silicon waveguide; and a cavity, a sidewall of which forms a connecting optical facet to the silicon waveguide; wherein a region of a bed of the cavity includes one or more heaters.

The heater may be a doped portion of the bed of the cavity. The heater may be located within a bonding region of the bed of the cavity, to which a III-V semiconductor based device coupon can be bonded.

The silicon-on-insulator platform may comprise a first heater and a second heater, located on respectively opposing sides of a bonding region of the bed of the cavity. The or each heater may be a metal strip located atop the bed of the cavity.

In a thirteenth aspect, embodiments of the present invention provide an optoelectronic device comprising the silicon-on-insulator of the twelfth aspect and a Ill-V semiconductor based device coupon bonded to the bed of the cavity.

In a fourteenth aspect, embodiments of the present invention provide a method of preparing silicon-on-insulator platform for a micro transfer printing process, the silicon-on-insulator platform including a silicon waveguide and a cavity adjacent to the silicon waveguide, wherein the method comprises the step of: providing a heater in a region of a bed of the cavity.

Providing the heater may include a step of doping the region of the bed of the cavity. The heater may be provided in a bonding region of the bed of the cavity.

Providing the heater may include a step of depositing a metal on the region of the bed of the cavity. The heater may be provided between a bonding region of the cavity and a sidewall of the cavity.

In a fifteenth aspect, embodiments of the invention provide a III-V semiconductor based device coupon, suitable for use in a micro transfer printing process used to fabricate an optoelectronic device, the device coupon comprising a III-V semiconductor based waveguide, wherein the III-V semiconductor based waveguide has a width measured transversal to a guiding direction of the waveguide, the width of the III-V semiconductor based waveguide in a central region being smaller than the width of the III-V semiconductor based waveguide in one or both end regions of the waveguide.

Both end regions of the III-V semiconductor based waveguide may be wider than the central region of the III-V semiconductor based waveguide.

In a sixteenth aspect, embodiments of the present invention provide an optoelectronic device comprising: a silicon-on-insulator platform, including a silicon waveguide formed in a silicon device layer, a silicon substrate, and a cavity; and a III-V semiconductor based device, located within the cavity of the silicon-on-insulator platform and containing a III-V semiconductor based waveguide which is optically coupled to the silicon waveguide; wherein the III-V semiconductor based waveguide has a width measured transversal to a guiding direction of the waveguide, the width of the III-V semiconductor based waveguide in a central region being smaller than the width of the III-V semiconductor based waveguide in one or both end regions of the waveguide.

A region of a bed of the cavity may include a patterned surface, which is configured to interact with light within the III-V semiconductor based waveguide.

The patterned surface may be a wave-guiding pattern. The wave-guiding pattern may comprise two regions having a first index, the two regions being separated by a guiding region having a second refractive index, the first refractive index being lower than the second refractive index.

In a seventeenth aspect, embodiments of the present invention provide a method of fabrication of an optoelectronic device, comprising the step of bonding the silicon-on-insulator platform of any of the above aspects with a III-V semiconductor based device coupon or the III-V semiconductor based device coupon of any of the above aspects.

The optional features set out herein with reference to the aspects of the invention are applicable to any other aspect where such a combination is not obviously incompatible or has been expressly forbidden.

Further aspects of the present invention provide: a computer program comprising code which, when run on a computer, causes the computer to perform the method of the third, fourth, eighth, fourteenth, and seventeenth aspect; a computer readable medium storing a computer program comprising code which, when run on a computer, causes the computer to perform the method of the third, fourth, eighth, fourteenth, and seventeenth aspect; and a computer system programmed to perform the method of the third, fourth, eighth, fourteenth, and seventeenth aspect.

Brief Description of the Drawings

Embodiments of the invention will now be described by way of example with reference to the accompanying drawings in which: Figure 1A shows a top-down view of a silicon-on-insulator platform; Figure 1B shows a top-down view of a III-V device coupon; Figure 1C shows a top-down view of the III-V device coupon of Figure 1B integrated with the silicon-on-insulator platform of Figure 1B; Figure 2A shows a side-on cross-sectional view of the III-V device coupon of Figure 1B being integrated with the silicon-on-insulator platform of Figure 1A-Figure 2B shows an end-on cross-sectional view of the III-V device coupon of Figure 1B being integrated with the silicon-on-insulator platform of Figure 1A; Figure 3A shows a partial side-on cross-sectional view of the III-V device coupon of Figure 1B after integration with the silicon-on-insulator platform of Figure 1A; Figure 3B shows a partial end-on cross-sectional view of the III-V device coupon of Figure 1B after integration with the silicon-on-insulator platform of Figure 1A; Figure 3C shows a partial end-on cross-sectional view of the III-V device coupon of Figure 1B after integration with the silicon-on-insulator platform of Figure 1A including an optical mode supported by the III-V semiconductor based waveguide; Figure 4A shows a side-on cross-sectional view of the III-V device coupon of Figure 1B being integrated with a variant silicon-on-insulator platform; Figure 4B shows an end-on cross-sectional view of the III-V device coupon of Figure 1B being integrated with a variant silicon-on-insulator platform; Figure 5A shows a partial side-on cross-sectional view of the III-V device coupon of Figure 1B after integration with the variant silicon-on-insulator platform of Figure 4A; Figure 5B shows a partial end-on cross-sectional view of the III-V device coupon of Figure 1B after integration with the variant silicon-on-insulator platform of Figure 4A; Figure 5C shows a partial end-on cross-sectional view of the III-V device coupon of Figure 1B after integration with the variant silicon-on-insulator platform of Figure 4A including an optical mode supported by the III-V semiconductor based waveguide; Figure 6A shows a top-down view of a variant silicon-on-insulator platform; Figure 6B shows a top-down view of the variant silicon-on-insulator platform of Figure 6A after the III-V device coupon of Figure 1B has been integrated; Figure 7A shows an end-on cross-sectional view of the III-V device coupon and variant silicon-on-insulator platform of Figure 6B; Figure 7B shows an end-on cross-sectional view of the III-V device coupon and a further variant silicon-on-insulator platform; Figure 7C shows an end-on cross-sectional view of the III-V device coupon and a further variant silicon-on-insulator platform; Figure 8 shows a top-down view of a variant silicon-on-insulator platform; Figure 9 shows an end-on cross-sectional view of the variant silicon-on-insulator platform of Figure 8 after the III-V device coupon of Figure 1B has been integrated; Figure 10A shows a top-down view of a further variant silicon-on-insulator platform; Figure 10B shows the further variant silicon-on-insulator platform of Figure 10A after the III-V device coupon of Figure 1B has been integrated; Figure 11A shows a side-on cross-sectional view of a variant silicon-on-insulator platform after the III-V device coupon of Figure 1B has been integrated; Figure 11B shows an end-on cross-sectional view of the variant silicon-on-insulator platform and III-V device coupon of Figure 11A; Figure 11C shows a top-down view of the variant silicon-on-insulator platform of Figure 11A before the III-V device coupon has been integrated; Figures 12A -12J show various views of two variant silicon-on-insulator platforms before and after the III-V device coupon has been integrated; Figure 13A shows an end-on cross-sectional view of a variant silicon-on-insulator platform after the III-V device coupon of Figure 1B has been integrated; Figure 13B shows a top-down view of the variant silicon-on-insulator platform before the III-V device coupon has been integrated; Figure 14A shows a top-down view of a variant III-V device coupon; Figure 14B shows a top-down view of the variant silicon-on-insulator platform of Figure 13B after the variant III-V device coupon of Figure 14A has been integrated Figure 15 shows an end-on cross-sectional view of the variant silicon-on-insulator platform of Figure 14B at a first point along a length of the waveguide; Figure 16 shows an end-on cross-sectional view of the variant silicon-on-insulator platform of Figure 14B at a second point along a length of the waveguide; Figure 17A is a side-on cross-sectional view of a variant silicon-on-insulator platform after the III-V device coupon of Figure 1B has been integrated; Figure 17B is an end-on cross-sectional view of the variant silicon-on-insulator platform of Figure 17A; Figure 18 is an end-on cross-sectional view of a silicon-on-insulator platform without a reflective pattern; Figure 19 is an end-on cross-sectional view of the variant silicon-on-insulator platform of Figure 17A; Figures 20A -200 are variations of the examples shown in Figures 7A -70; and Figure 21 is a variation of the example shown in Figure 9. Detailed Description and Further Optional Features Aspects and embodiments of the present invention will now be discussed with reference to the accompanying figures. Further aspects and embodiments will be apparent to those skilled in the art.

Figure 1A shows a top-down view of a silicon-on-insulator platform 100. The platform includes a silicon device layer 101, and a cavity 102 formed in the silicon device layer. A patterned surface 103 is provided in a bed of the cavity. A silicon waveguide 104, formed from or positioned atop the silicon device layer 101 is coupled to the cavity. A connecting facet of the silicon waveguide may form a portion of a sidewall of the cavity.

Figure 1B shows a top-down view of a III-V device coupon 110. Broadly, the device coupon comprises a waveguide rib or ridge, 111 and a waveguide slab 112 which together with the epitaxially defined active region of separate confinement heterostructure, SCH, region and other ancillary structures (not shown) provide the III-V semiconductor based waveguide. The waveguide slab 122 and SCH layer in some examples has a height, as measured from the patterned surface 103 to the rib or ridge 111 which is less than 1 pm. The bottom surface of the slab region is provided for bonding to the bed of the cavity. The device coupon may include further features, such as doped regions to provide p-n or p-i-n junctions which may extend vertically or horizontally across the waveguide. In some examples, electrodes which electrically contact to the n or p doped regions of the p-n or p-i-n junctions are provided in the device coupon 110. In other examples, the electrodes are provided in the silicon-on-insulator platform, and traces are used to connect the doped regions to the electrodes.

Figure 1C shows a top-down view of the III-V device coupon of Figure 1B integrated with the silicon-on-insulator platform of Figure 13. The device coupon 110 sits atop at least a portion of the patterned surface 103, within the cavity 102. The rib or ridge 111 is aligned with the silicon waveguide 104. Whilst a gap is shown between the rib or ridge 111 of the III-V semiconductor based waveguide and the silicon waveguide 104, in some examples there is no or substantially no gap. In yet further examples, a gap is present which is subsequently filled by a bridge-waveguide (for example formed from amorphous silicon) or a bridge material (for example a dielectric such as benzocyclobutene).

Figure 2A shows a side-on view of the device coupon 110 of Figure 1B being integrated with the silicon-on-insulator platform 100 of Figure 1A. The coupon is positioned above the patterned surface 103 which, in this example, is formed in the silicon device layer. Figure 2B shows an end-on view of the device coupon 110 of Figure 1B being integrated with the silicon-on-insulator platform 100 of Figure 1A. Of note, is the alignment between the waveguide rib or ridge 111 of the III-V semiconductor based waveguide which is or forms a part of the device coupon and the silicon waveguide 104 at one end of the cavity. Figures 2A and 23 also depict the detailed structure of the silicon-on-insulator platform 100. Notably, the platform comprises a silicon substrate 106, atop which is a buried oxide (BOX) layer 105. The buried oxide layer is, in this example, formed from silicon dioxide or silica. The silicon device layer is positioned on top of the buried oxide layer.

Figure 3A shows a partial side-on view of the device coupon 110 of Figure 1B after integration with the silicon-on-insulator platform 100 of Figure 1A. Notably, a bottom surface of the waveguide slab 112 is adjacent and bonded to the patterned surface 103. Figure 33 shows a partial end-on view of the device coupon of Figure 1B after integration with the silicon-on-insulator platform of Figure 1A.

Figure 30 shows a partial end-on cross-sectional view of the device coupon 110 of Figure 18 after integration with the silicon-on-insulator platform 100 of Figure 1A including an optical mode 300 supported by the III-V semiconductor based waveguide. The optical mode 300 exists chiefly within the waveguide slab 112. The waveguide rib or ridge 111 acts to provide lateral localization of the optical mode. Notably, in this example, the optical mode 300 extends into and interacts with the patterned surface 103.

Figure 4A shows a side-on cross-sectional view of the device coupon 110 of Figure 1B being integrated with a variant silicon-on-insulator platform 400. Where the coupon and platform share features with the examples discussed previously, like features are shown by like reference numerals. The variant silicon-on-insulator platform 400 differs from the platform 100 shown previously in that the patterned surface 103 is provided within the silicon substrate 106. In this example, the entirety of a region of the silicon device layer defining the cavity is etched away. Subsequently, the entirety of the buried oxide layer now exposed is also etched away, leaving the silicon substrate exposed. Figure 4B shows an end-on cross-sectional view of the device coupon 110 of Figure 1B being integrated with the variant silicon-on-insulator platform 400.

Figure 5A shows a partial side-on cross-sectional view of the device coupon of Figure 1B after integration with the variant silicon-on-insulator platform of Figure 4A. Figure 5B shows a partial end-on cross-sectional view of the device coupon of Figure 1B after integration with the variant silicon-on-insulator platform of Figure 4A. As can be seen, the bottommost surface of the waveguide slab 112 is adjacent and bonded to the silicon substrate 106 which contains the patterned surface 103. Figure 50 shows a partial end-on cross-sectional view of the III-V device coupon 110 of Figure 1B after integration with the variant silicon-on-insulator platform 400 of Figure 4A including an optical mode 450 supported by the III-V semiconductor based waveguide. The optical mode 400 exists chiefly within the waveguide slab 112. The waveguide rib or ridge 111 acts to provide lateral localization of the optical mode. Notably, in this example, the optical mode 400 extends into and interacts with the patterned surface 103.

Figure 6A shows a top-down view of a variant silicon-on-insulator platform 600 and Figure 68 shows a top-down view of the variant silicon-on-insulator platform of Figure 6A after the device coupon of Figure 1B has been integrated. Where the coupon and platform share features with the examples discussed previously, like features are shown by like reference numerals. The silicon-on-insulator platform 600 differs from those shown previously by the inclusion of a first 601a and second 601b heater. The heaters are provided as longitudinal strips, which are coextensive with the patterned surface103. Each heater is connected to a positive electrode 602 and negative electrode 603. The heaters are configured, during operation of the optoelectronic device, to heat the III-V semiconductor based device so as to tune an operating wavelength thereof.

Figure 7A shows an end-on cross-sectional view of the device coupon and variant silicon-on-insulator platform of Figure 6B. As can be seen, the heaters 601a and 601b are provided as doped regions of the silicon device layer 101. Preferably, the heaters are formed by the provision of an n-type species of dopant.

Figure 7B shows an end-on cross-sectional view of the device coupon and a further variant silicon-on-insulator platform 710. Where the coupon and platform share features with the examples discussed previously, like features are shown by like reference numerals. The silicon-on-insulator platform 710 differs from the platform 600 in that the heaters 701a and 701b, still provided as doped regions, are in this example located between the waveguide slab 112 and the buried oxide layer 105. The doped regions are still laterally spaced from the patterned surface 103.

Figure 7C shows an end-on cross-sectional view of the device coupon and a further variant silicon-on-insulator platform 720. Where the coupon and platform share features with the examples discussed previously, like features are shown by like reference numerals. The silicon-on-insulator platform 720 differs from the platforms shown previously in that the heaters 702a and 702b are provided as metal strips, disposed on the silicon device layer 101. The metal may be any one of: titanium, titanium nitride, chromium, or nickel. In further variants, not shown, the silicon-on-insulator platform 600 shown in Figures 6A -7C do not contain the patterned surface 603 discussed above but does contain the heaters.

Figure 8 shows a top-down view of a variant silicon-on-insulator platform 800 and Figure 9 shows an end-on cross-sectional view of the variant silicon-on-insulator platform of Figure 8 after the device coupon of Figure 1B has been integrated. Where the platform shares features with the examples discussed previously, like features are shown by like reference numerals. The platform 800 differs from platform 600 shown previously is by the inclusion of a silicon heat sink via structure 801a and 801b. The silicon heat sink structure vias are provided by the steps of: lithographically defining the via pattern; etching through the silicon device layer 101 and buried oxide layer 105 to create vias to expose the silicon substrate 106. The heat sink material is then epitaxially grown from the silicon substrate or deposited into the vias to fill the vias. The heat sink structure allows for improved heat sinking when the III-V semiconductor based device is a laser when the device is bonded to the silicon device layer (rather than examples where the buried oxide has been removed, and the device is bonded to either a dielectric or the silicon substrate). The distance 'd' is chosen so as to provide a heat flow path from the III-V semiconductor based device to the silicon substrate with a relatively low resistance, whilst also allowing the heaters to heat the III-V semiconductor based device more efficiently than if no buried oxide at all was present. This provides a good level of heat sinking whilst also allowing thermal tuning of the patterned surface 103 (when, for example, it is a grating). In a further variant, not shown, the siliconon-insulator platform 800 does not contain the heaters or the patterned surface 103, but does include the heat sink via structure.

Figure 10A shows a top-down view of a further variant silicon-on-insulator platform 1000, and Figure 10B shows the further variant silicon-on-insulator platform of Figure 10A after the device coupon of Figure 1B has been integrated. Where the platform shares features with the examples discussed previously, like features are shown by like reference numerals. The patterned surface in platform 1000 differs from those shown previously, in that it comprises two gratings 103a and 103b separated by a grating phase shift region 1001. The strength of the grating, i.e. the degree to which it interacts with the optical mode in the III-V semiconductor based waveguide, can be controlled by varying the depth of the etch into the bed of the cavity as well as varying the thickness of a lower optical cladding layer in the device coupon.

Figure 11A shows a side-on cross-sectional view of the silicon-on-insulator platform 1000 after the device coupon of Figure 1B has been integrated and Figure 11B shows an end-on cross-sectional view of the variant silicon-on-insulator platform and device coupon of Figure 11A.

Figure 11C shows a top-down view of a variant silicon-on-insulator platform 1100, before the device coupon has been integrated. Where the platform shares features with the examples discussed previously, like features are shown by like reference numerals. In this example, the patterned surface is a penetration reducing pattern 1102 in that it provides a region having a lower refractive index than the waveguide slab 112. This lower refractive index reduces or eliminates the degree to which an optical mode in the waveguide rib and slab penetrates into the silicon-on-insulator platform and optionally removes the need for a BOX layer between the silicon device layer and the silicon substrate. Notably, the patterned surface 1102 provides a checkerboard type view, due to the intersecting gratings which extend both in the 'x' and 'z' direction.

Figures 12A -12J show various views of two variant silicon-on-insulator platforms before and after the III-V device coupon has been integrated. The SOI platform 1220 shown in a top-down view in Figure 12A contains a partial grating 103b, i.e. one which has a length (measured in the z direction, which is parallel or substantially parallel to the guiding direction of waveguide 104) which is less than that of the waveguide rib 112 and slab 111 in the device coupon 110. In some examples, the length measured in the z direction of the partial grating 103b that is directly underneath waveguide rib is approximately 50% of the length of the waveguide rib 112. This may enhance the spectral purity in subsequent lasing. Once the device coupon 110 is bonded to the cavity 102, as shown in Figure 12B, it is substantially aligned with the grating 103b. In this example, the device coupon contains a laser (preferably a III-V semiconductor based laser), the partial grating 103b is provided along the output portion of the laser. This arrangement is shown in cross-section in Figures 12C -12E, with Figure 12D being a cross-section through the partial grating, and Figure 12E being a cross-section through a region of the cavity not containing the partial grating. The device coupon 110 with partial grating 103b is provided with an antireflective facet on the output facet near the partial grating 103b and a high-reflectivity facet on the rear facet, furthest from the partial grating 103b, to enhance lasing characteristic of output power.

The SOI platform 1240 shown in a top-down view in Figure 12F contains a first partial grating 103b and a second partial grating 103c. The first partial grating 103b is the same as that shown in Figures 12A -12E, and has the same properties. The second partial grating 103c is a broadband grating mirror located at the end of the device coupon distal to the silicon waveguide 104. That is, it is located on an opposing side of the first partial grating 103b to the silicon waveguide 104, and with a gap between the first and second partial gratings. The second partial grating 103c provides a highly reflective facet at an opposing end of the laser (within the device coupon) to the antireflective facet adjacent to the silicon waveguide 104. This provides a DFB laser with an accurate wavelength, since the rear facet can include an antireflective facet to eliminate any interaction with a highly reflective facet.

In this embodiment, the resonator cavity does not suffer any phase errors, which would otherwise have been introduced due to the fabrication tolerances typically involved in forming a HR facet. Figures 12H -12J show various cross-sections through the SOI platform 1240 and device coupon. Notably, it can be seen that the first partial grating 103b is shallower (i.e. extends into the silicon on insulator layer for a smaller distance) than the second partial grating 103c. The first partial grating may extend no more than 50% into the silicon on insulator layer, whereas the second partial grating may extend at least 50% into the silicon on insulator layer. Figure 121 shows a cross-section through the first partial grating 103b, and Figure 12J shows a cross-section through the second partial grating 103c.

In one example of the 501 platforms 1220 and 1240 discussed above, there is no oxide between the cavity and the device coupon. This allows the higher refractive index of the silicon on insulator layer to attract the optical mode within the device coupon to interact with the gratings.

Figure 13A shows an end-on cross-sectional view of a variant silicon-on-insulator platform 1200 after the device coupon of Figure 1B has been integrated and Figure 13B shows a top-down view of the variant silicon-on-insulator platform before the device coupon has been integrated. Where the platform shares features with the examples discussed previously, like features are shown by like reference numerals. In this example, the patterned surface is divided into two low refractive index regions 1103a and 1103b (their refractive index having been lowered by etching) and a high refractive index region 1104 located between the two low refractive index regions. This patterned surface provides additional wave-guiding, and so can be used to aid alignment of the optical modes, and optionally removes the need for a BOX layer between the silicon device layer and the silicon substrate.

Figure 14A shows a top-down view of a variant device coupon and Figure 14B shows a top-down view of the variant silicon-on-insulator platform of Figure 13B after the variant device coupon of Figure 14A has been integrated. Where the platform shares features with the examples discussed previously, like features are shown by like reference numerals. The variant device coupon of Figure 14A differs from those shown previously in that the waveguide rib widens at one end. This allows the wave guiding in the III-V semiconductor based device to be controlled by the patterned surface 1103a and 1103b in the silicon-oninsulator platform instead of by the III-V semiconductor based device waveguide, relaxing or eliminating the need for precise alignment between the III-V semiconductor based device waveguide and the Si waveguide. In a further example, not shown, the waveguide rib 1301 is wider at both ends than in the central region (between the two ends).

Figure 15 shows an end-on cross-sectional view of the variant silicon-on-insulator platform of Figure 14B at a first point along a length of the waveguide and Figure 16 shows an end-on cross-sectional view of the variant silicon-on-insulator platform of Figure 14B at a second point along a length of the waveguide. As can be seen in Figure 15, a degree of misalignment between the waveguide ridge 1301 and the high refractive index region 1104 causes the optical mode to be slightly misaligned. Whereas, in the wider section of the waveguide rib 1301, the misalignment is corrected as the wave guiding is now being performed or aided by the low refractive index regions 1103a and 1103b. The low refractive index regions can be self-aligned with the silicon waveguide 104 during fabrication, and so alignment between the optical mode in the III-V semiconductor based waveguide and the silicon waveguide can be achieved without the need for accurate alignment of the III-V semiconductor based device to the Si waveguide. The alignment can be improved beyond that which is possible conventionally due to the alignment tolerances during bonding.

Figure 17A is a side-on cross-sectional view of a variant silicon-on-insulator platform 1600 after the device coupon of Figure 1B has been integrated and Figure 17B is an end-on cross-sectional view of the variant silicon-on-insulator platform of Figure 17A. Where the platform shares features with the examples discussed previously, like features are shown by like reference numerals. In this example, the patterned surface is a reflective grating. The reflective grating has a grating spacing smaller than an operating wavelength of the optoelectronic device. For example, if the operating wavelength is 1310 nm, the grating spacing may be smaller than this.

Figure 18 is an end-on cross-sectional view of a silicon-on-insulator platform without a reflective pattern; Figure 19 is an end-on cross-sectional view of the variant silicon-on-insulator platform of Figure 17A. As can be seen in Figure 18, without the patterned surface the optical mode 1601 extends at least partially into the bed of the cavity. Whereas, the provision of the patterned surface 1501 as shown in Figure 19 confines the optical mode 1701 to being within the rib 111 and slab 112. This can aid coupling from the III-V semiconductor based waveguide to the silicon waveguide, and so decrease the optical losses in the optoelectronic device, and also optionally removes the need for a BOX layer between the silicon device layer and the silicon substrate.

Figures 20A -200 show variations of the coupons and platforms shown in Figures 7A -70. Where the variations share features with the examples shown in Figures 7A -70, like features are indicated by like reference numerals. The variations in Figures 20A -200 differ from the examples shown in Figures 7A -7C by their inclusion of one or more thermally isolating trenches 200. In some examples, there may be a single trench present on one lateral side of the platform. In the examples shown in Figures 20A -200, a pair of trenches are shown on opposing lateral sides of the platform. These trenches, in some examples, surround the cavity around its perimeter i.e. define a single trench when viewed from above. The trenches increase the thermal efficiency of the resulting devices. In further variations, the platforms do not contain the patterned surface, heaters, or heat sink via structure discussed previously, but do contain the thermally isolating trenches 200.

Figure 21 is a variation of the example shown in Figure 9. Where it shares features with the example shown in Figure 9, like features are indicated by like reference numerals. The variation in Figure 21 differs from the example shown in Figure 9 by its inclusion of one or more thermally isolating trenches 200. In some examples, there may be a single trench present on one lateral side of the platform. In the example shown in Figure 21, a pair of trenches are shown on opposing lateral sides of the platform. These trenches, in some examples, surround the cavity around its perimeter i.e. define a single trench when viewed from above. The trenches increase the thermal efficiency of the resulting devices.

While the invention has been described in conjunction with the exemplary embodiments described above, many equivalent modifications and variations will be apparent to those skilled in the art when given this disclosure. Accordingly, the exemplary embodiments of the invention set forth above are considered to be illustrative and not limiting. Various changes to the described embodiments may be made without departing from the spirit and scope of the invention.

List of Features Sal Platform 1220 501 Platform 101 Silicon device layer 1240 SOI platform 102 Cavity 103 Patterned surface 104 Silicon waveguide Buried oxide layer 106 Silicon substrate Device Coupon 111 Waveguide rib 112 Waveguide slab 300, 450 Optical mode 400, 600 SOI Platform 601a/b Heater 602 Positive electrode 603 Negative electrode 710, 720 SOI platform 701a/b Heater 702a/b Heater 800 SOI platform 801a/b Silicon heat sink 1000 SOI platform 1001 Grating phase shift 1100 SOI platform 1101 BCB layer 1102 Patterned surface 1103a/b Low refractive index region 1104 High index region 1200 SOI Platform 1301 Coupon waveguide rib 1401, 1402 Optical mode 1600 SOI Platform 1601, 1701 Optical mode Thermally isolating trench

Claims

CLAIMS1. A III-V semiconductor based device coupon, suitable for use in a micro transfer printing process used to fabricate an optoelectronic device, the device coupon comprising a III-V semiconductor based waveguide, wherein the III-V semiconductor based waveguide has a width measured transversal to a guiding direction of the waveguide, the width of the III-V semiconductor based waveguide in a central region being smaller than the width of the III-V semiconductor based waveguide in one or both end regions of the waveguide.
2. The III-V semiconductor based device coupon of claim 1, wherein both end regions of the III-V semiconductor based waveguide are wider than the central region of the III-V semiconductor based waveguide.
3. An optoelectronic device, comprising: a silicon-on-insulator platform, including a silicon waveguide formed in a silicon device layer, a silicon substrate, and a cavity; and a III-V semiconductor based device, located within the cavity of the silicon-on-insulator platform and containing a III-V semiconductor based waveguide which is optically coupled to the silicon waveguide; wherein the III-V semiconductor based waveguide has a width measured transversal to a guiding direction of the waveguide, the width of the III-V semiconductor based waveguide in a central region being smaller than the width of the III-V semiconductor based waveguide in one or both end regions of the waveguide.
4. The optoelectronic device of claim 3, wherein both end regions of the III-V semiconductor based waveguide are wider than the central region of the III-V semiconductor based waveguide.
5. The optoelectronic device of either claim 3 or claim 4, wherein a region of a bed of the cavity includes a patterned surface, which is configured to interact with light within the III-V semiconductor based waveguide.
6. The optoelectronic device of claim 5, wherein the patterned surface is a wave-guiding pattern.
7. The optoelectronic device of claim 6, wherein the wave-guiding pattern comprises two regions having a first refractive index, the two regions being separated by a guiding region having a second refractive index, the first refractive index being lower than the second refractive index.
8. A method of fabricating an optoelectronic device, comprising the step of bonding the III-V semiconductor based device coupon of claim 1 or claim 2 to a bed of a cavity of a silicon-on-insulator platform.