CN109560462A - Silicon substrate hybrid integrated laser array and preparation method thereof - Google Patents
Silicon substrate hybrid integrated laser array and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/40—Arrangement of two or more semiconductor lasers, not provided for in groups H01S5/02 - H01S5/30
- H01S5/4025—Array arrangements, e.g. constituted by discrete laser diodes or laser bar
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
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Abstract
The invention discloses a kind of silicon substrate hybrid integrated laser arrays and preparation method thereof.Silicon substrate hybrid integrated laser array includes: the silicon substrate hybrid integrated laser for the multiple parallel arrangements being produced on SOI substrate and III-V semiconductor epitaxial layers；Wherein, each silicon substrate hybrid integrated laser includes: silicon ridge waveguide；Heat-conducting layer, in the specific region of silicon ridge waveguide two sides, which is that SOI substrate removes the region obtained after top layer silicon and buried oxide layer；Intrinsic layer, shape are the shape of a saddle, protruding portion and interconnecting piece including both ends, wherein the protruding portion at a both ends is covered in above heat-conducting layer；Successively there are N-type ducting layer, active area, p-type cap rock on intrinsic layer interconnecting piece；III-V waveguide is formed by III-V semiconductor epitaxial pattern layers, is connected with silicon ridge waveguide；P-type ohmic contact layer, P electrode and N electrode.Thermal diffusivity is good, preparation process simple and stable, reproducible, low manufacture cost.
Description
Technical field
The disclosure belongs to field of laser device technology, is related to a kind of silicon substrate hybrid integrated laser array and preparation method thereof.
Background technique
With the development of technology, people are higher and higher to message transmission rate, transmission bandwidth and horsepower requirements, certainly by electronics
The restriction of body physical characteristic, it is traditional based on the electrical interconnection for being electrically integrated chip when transmitting high speed signal, have that energy consumption is high, bandwidth
The problem of narrow and bottleneck that optoelectronic intagration system cost is high；And photon has superelevation transmission speed, superelevation concurrency, superelevation band
The characteristics of width is with ultra low transmission with power consumption is interacted.Since silicon integreted phontonics combine ultra-large logic, the superelevation of CMOS technology
Accurate manufacturing technique, low-cost advantage, therefore, silicon-based optical interconnection are expected to break through the bottleneck of above-mentioned rate, power consumption, bandwidth and cost.
Silicon integreted phontonics technology has been greatly developed by the research of early period, but light source is still global difficulty
Topic.Since Intel in 2006 has invented first electrical pumping silicon substrate hybrid integrated laser, silicon substrate hybrid integrated laser at present
Device has obtained extensive research.But modern communication technology generallys use multiplexing technique and improves message capacity, is badly in need of silicon
The research of base hybrid integrated iii-v laser array.
Realize that the method for silicon substrate hybrid integrated laser array is common by three kinds of methods at present.First method is to pass through
SOI silica-base material and III-V epitaxial material are bonded together by direct wafer bonding or the method for medium bonding, in SOI or
Multiple parallel ridge waveguides are made on III-V epitaxial material, and micro-structure is made on ridge waveguide or curved waveguide is used to select
Wavelength realizes silicon substrate hybrid integrated laser array.But the silicon substrate hybrid integrated laser array being previously mentioned in the program does not all have
There is influence problem of the heat dissipation characteristics difference for considering buried oxide layer (BOX) in SOI to laser array.Second method is on SOI
By the direct epitaxial growth III-V semiconductor material of MOCVD or MBE, ridge waveguide is made on SOI or III-V, in ridge waveguide
Upper production micro-structure is used to select wavelength.Although the program can realize that autoregistration silicon substrate hybrid integrated swashs on a SOI material
Light device does not need the exact alignment techniques between SOI and III-V, but the requirement to epitaxy technology is very high, and technology is still at present
Prematurity, it is also necessary to explore, also the influence without the heat dissipation characteristics difference of buried oxide layer in research SOI substrate to device.The third side
Method is that the III-V laser array prepared is integrated or sealed by 3D after the parallel silica-based waveguides of SOI production a lot of
Multiple silica-based waveguides end couplings in the form and SOI of dress.3D is integrated or the form of encapsulation, needs the silicon on SOI material
Waveguide is precisely aligned with light end everywhere in III-V semiconductor laser array, and the requirement to encapsulation technology is very high, cost also compared with
Height, while being also contemplated that how to improve end coupling efficiency.
Summary of the invention
(1) technical problems to be solved
Present disclose provides a kind of silicon substrate hybrid integrated laser arrays and preparation method thereof, more than at least partly solving
The technical issues of proposed.
(2) technical solution
According to one aspect of the disclosure, a kind of silicon substrate hybrid integrated laser array is provided, comprising: be produced on SOI
The silicon substrate hybrid integrated laser of multiple parallel arrangements in substrate and III-V semiconductor epitaxial layers；Wherein, each silicon substrate mixing
Integration laser includes: silicon ridge waveguide；Heat-conducting layer, in the specific region of silicon ridge waveguide two sides, which is SOI base
Bottom removes the region obtained after top layer silicon and buried oxide layer；Intrinsic layer, shape are the shape of a saddle, protruding portion and connection including both ends
Portion, wherein the protruding portion at a both ends is covered in above heat-conducting layer；N-type ducting layer, is formed on the interconnecting piece of intrinsic layer；It is active
Area is formed on N-type ducting layer；P-type cap rock, is formed on active area；III-V waveguide, by III-V semiconductor epitaxial layers
Patterning is formed, and both ends are connected with the front and back ends of silicon ridge waveguide, and the structure of two sides is the p-type lid not being etched after patterning
Layer and the active area of lower section；P-type ohmic contact layer is located on III-V waveguide；P electrode, be located at p-type ohmic contact layer it
On；And N electrode, it is located on N-type ducting layer.
In some embodiments of the present disclosure, SOI substrate is incorporated in by way of being bonded with III-V semiconductor epitaxial layers
Together, the mode of the bonding includes: that metal bonding, medium bonding or direct wafer bonding, silicon ridge waveguide and III-V waveguide are
Respectively by being made on SOI substrate and III-V semiconductor epitaxial layers, then by by one liang of the intrinsic layer of the shape of a saddle
The protruding portion at end is covered on heat-conducting layer, and both SOI substrate and III-V semiconductor epitaxial layers are combined together.
In some embodiments of the present disclosure, each III-V waveguide and each silicon ridge waveguide are one-to-one, and are being hung down
Histogram to be alignment.
In some embodiments of the present disclosure, SOI substrate successively includes: substrate silicon, buried oxide layer and top layer from bottom to top
Silicon, which is SOI substrate makes by patterning, be by SOI substrate top layer silicon is patterned, etching
It is formed afterwards；III-V semiconductor epitaxial layers successively include: intrinsic layer from bottom to top, N-type ducting layer, active area, p-type cap rock with
And p-type ohmic contact layer, the III-V waveguide are III-V semiconductor epitaxial layers by patterning, then etch p-type Ohmic contact
What layer, p-type cap rock, active area and N-type ducting layer were made.
In some embodiments of the present disclosure, the structure along the direction of silicon ridge waveguide, the silicon ridge waveguide both ends includes: wedge
Shape ridge waveguide and/or straight ridge waveguide；Structure along the direction of III-V waveguide, the III-V waveguide both ends includes: wedge-shaped waveguide
And/or straight wave guide.
In some embodiments of the present disclosure, III-V waveguide includes: the wedge-shaped waveguide of front and rear sections and the straight wave of interlude
It leads, front and rear sections wedge-shaped waveguide is patterned to be etched to N-type ducting layer bottom, is connected with the front and back ends of silicon ridge waveguide, intermediate
Section straight wave guide is etched to p-type cap rock lower part；The remaining p-type cap rock not being etched is located at the two sides of the III-V waveguide, active
Area is located under p-type cap rock, also equally is located at the two sides of the III-V waveguide.
In some embodiments of the present disclosure, the material of heat-conducting layer includes: metal or alloy material, comprising: SnAu, Sn,
Ag, Cu, Au, Al, Fe or CuAl；Semiconductor material, comprising: polysilicon, monocrystalline silicon, amorphous silicon or germanium；Inorganic non-metallic material,
It include: graphene, graphite, carbon fiber, C/C composite material or carbon black；And heat-conducting polymer material；And/or III-V semiconductor
P-type ohmic contact regions in epitaxial layer, p-type cap rock, active area, N-type ducting layer and intrinsic layer material include: indium phosphide, arsenic
Change gallium, the binary system of gallium antimonide material system, ternary system, in quaternary material it is any two or more.
In some embodiments of the present disclosure, silicon substrate hybrid integrated laser array, further includes: micro-structure is formed in silicon
On ridge waveguide or the structure of III-V waveguide.
In some embodiments of the present disclosure, the pattern of micro-structure includes: one-dimensional, two micro-, three-dimensional geometries, structure
It include: grating, photonic crystal or microflute；It, can by adjusting the parameter of the micro-structure in each silicon substrate hybrid integrated laser
Realize the control and adjusting of the excitation wavelength range of the silicon substrate hybrid integrated laser array.
A kind of preparation method of silicon substrate hybrid integrated laser array another aspect of the present disclosure provides, packet
It includes: making the silicon ridge waveguide of multiple parallel arrangements on SOI substrate；Given zone is made on the SOI substrate containing silicon ridge waveguide
Domain, and heat-conducting layer is grown on the specific area；Using III-V semiconductor material successively epitaxial growth intrinsic layer, N-type ducting layer,
Active area, p-type cap rock and P type ohmic contact layer form III-V semiconductor epitaxial layers；On III-V semiconductor epitaxial layers
Patterned process is carried out, intrinsic layer, III-V waveguide and the structure of III-V waveguide two sides of the shape of a saddle, growth P electricity are etched
Pole, N electrode；By the SOI substrate containing silicon ridge waveguide and heat-conducting layer and the III-V half containing III-V waveguide, P electrode, N electrode
The bonding of conductor epitaxial layer is got up；And micro-structure is made on silicon ridge waveguide or the structure of III-V waveguide, complete silicon substrate mixing
The preparation of integration laser array.
(3) beneficial effect
It can be seen from the above technical proposal that silicon substrate hybrid integrated laser array and its preparation side of disclosure offer
Method has the advantages that
In every road silicon substrate hybrid integrated laser of forming array, top is got rid of in the specific region of silicon ridge waveguide two sides
Layer silicon and buried oxide layer expose substrate silicon, have then inserted metal or highly heat-conductive material in this region, production when active area is shone
Raw heat is entered substrate silicon and is dissipated by metal in N-type ducting layer, intrinsic layer and the region and highly heat-conductive material, is solved
The problem for being influenced silicon substrate hybrid integrated laser heat dissipation characteristics difference in SOI material due to buried oxide layer thermal conduction characteristic difference, is improved
The heat dissipation characteristics and photoelectric characteristic of silicon substrate hybrid integrated laser array；In addition, III-V semiconductor epitaxial material by MBE or
Extension of MOCVD forms, and does not need secondary epitaxy and selective area growth technology, and simple process is stablized；Structure on SOI can be with
Mature CMOS technology is compatible, process stabilizing, reproducible, low manufacture cost；Structure on III-V semiconductor material can be with
It is compatible with traditional photoelectron technology, there is higher repeatability in production.
Detailed description of the invention
Fig. 1 is the structural schematic diagram according to embodiment of the present disclosure silicon substrate hybrid integrated laser array.
Fig. 2 is according to a silicon substrate hybrid integrated laser in embodiment of the present disclosure silicon substrate hybrid integrated laser array
Structural schematic diagram.
Fig. 3 is according to a silicon substrate hybrid integrated laser in embodiment of the present disclosure silicon substrate hybrid integrated laser array
Structural profile illustration.
Fig. 4 is the silicon substrate hybrid integrated according to embodiment of the present disclosure silicon ridge waveguide two sides without containing specific region and heat-conducting layer
The profile thermal distribution schematic diagram of laser.
Fig. 5 swashs for the silicon substrate hybrid integrated for containing specific region and heat-conducting layer according to embodiment of the present disclosure silicon ridge waveguide two sides
The profile thermal distribution schematic diagram of light device.
[symbol description]
100- silicon substrate hybrid integrated laser array；400- silicon substrate hybrid integrated laser；
200-SOI substrate；
201- substrate silicon；202- buried oxide layer；
203- top layer silicon；204- silicon ridge waveguide；
300-III-V semiconductor epitaxial layers；
301-P type ohmic contact layer；302-P type cap rock；
303- active area；304-N type ducting layer；
305- intrinsic layer；306-III-V waveguide；
307-P electrode；308-N electrode；
500- micro-structure；700- heat-conducting layer.
Specific embodiment
Present disclose provides a kind of silicon substrate hybrid integrated laser arrays and preparation method thereof, have good heat dissipation characteristics
And photoelectric characteristic, and III-V semiconductor epitaxial material is formed by extension of MBE or MOCVD, does not need secondary epitaxy and constituency
Growing technology, simple process are stablized；Structure on SOI can be compatible with mature CMOS technology, process stabilizing, it is reproducible,
Low manufacture cost；Structure on III-V semiconductor material can be compatible with traditional photoelectron technology, have in production compared with
High repeatability.
For the purposes, technical schemes and advantages of the disclosure are more clearly understood, below in conjunction with specific embodiment, and reference
The disclosure is further described in attached drawing.
In first exemplary embodiment of the disclosure, a kind of silicon substrate hybrid integrated laser array is provided.
Fig. 1 is the structural schematic diagram according to embodiment of the present disclosure silicon substrate hybrid integrated laser array.Fig. 2 is according to this
The structural schematic diagram of a silicon substrate hybrid integrated laser in open embodiment silicon substrate hybrid integrated laser array.Fig. 3 is
Shown according to the structural profile of a silicon substrate hybrid integrated laser in embodiment of the present disclosure silicon substrate hybrid integrated laser array
It is intended to.
In conjunction with shown in Fig. 1-Fig. 3, the silicon substrate hybrid integrated laser array 100 of the disclosure, including it is produced on SOI substrate
The silicon substrate hybrid integrated laser 400 of Multichannel Parallel arrangement on 200 and III-V semiconductor epitaxial layers 300, each silicon substrate mixing
Integration laser 400 includes: substrate silicon 201；Buried oxide layer 202；Silicon ridge waveguide 204；Heat-conducting layer 700 is located at 204 liang of silicon ridge waveguide
In the specific region of side；Intrinsic layer 305, shape are the shape of a saddle, protruding portion and interconnecting piece including both ends, wherein a both ends is prominent
Portion is located at the two sides of silicon ridge waveguide 204, is covered in 700 top of heat-conducting layer out；N-type ducting layer 304, positioned at silicon ridge waveguide 204
Top is formed on the interconnecting piece of intrinsic layer 305；Active area 303 is formed on N-type ducting layer 304；P-type cap rock 302,
It is formed on active area 303；III-V waveguide 306 is formed by the patterning of III-V semiconductor epitaxial layers 300, with silicon ridge waveguide
204 rear end is connected, and two sides are the active area 303 of the p-type cap rock 302 and lower section that are not etched after patterning；P-type ohm
Contact layer 301 is located on III-V waveguide 306；P electrode 307 is formed on p-type ohmic contact layer 301；N electrode 308,
It is formed on N-type ducting layer 304；And micro-structure 500, it is formed in the structure of silicon ridge waveguide 204 or III-V waveguide 306；
Wherein, specific region is located at silicon ridge waveguide two sides, and heat-conducting layer 700 is by will give birth to after the top layer silicon and buried oxide layer removal in region
What long Heat Conduction Material obtained.
Below with reference to Fig. 2 and Fig. 3, the various pieces of the silicon substrate hybrid integrated laser array of the present embodiment are carried out detailed
It introduces.
In the present embodiment, SOI substrate 200 successively includes: substrate silicon 201, buried oxide layer 202 and top layer silicon from bottom to top
203。
In the present embodiment, the buried oxide layer 202 of SOI substrate 200 with a thickness of 2 μm；Top layer silicon with a thickness of 220nm；It is pushing up
The width for multiple parallel silicon ridge waveguides 204 that layer silicon makes above is 3 μm.
Silicon ridge waveguide 204 is that SOI substrate 200 is made by patterning, is by the top layer silicon of SOI substrate 200
It is 203 patterned, formed after etching.
In the present embodiment, wedge-shaped ridge can be along the structure in the direction of silicon ridge waveguide 204,204 both ends of silicon ridge waveguide
Waveguide or straight ridge waveguide, width and height can be arbitrary numerical value, patterned by the top layer silicon 203 of SOI substrate 200
It is formed；In the production process, the structure of 204 two sides of silicon ridge waveguide is also the patterned shape of top layer silicon 203 by SOI substrate 200
At referring to the pattern formed in the top layer silicon 203 of SOI substrate 200 in Fig. 1 being in Y glyph shape；204 two sides of silicon ridge waveguide
Structure and the pattern of silicon ridge waveguide 204 can design on a photolithography plate, then using being once lithographically formed silicon ridge waveguide
The pattern of 204 and its two sides.
Heat-conducting layer 700, positioned at the two sides of silicon ridge waveguide 204, by the top layer of 204 two sides of silicon ridge waveguide in SOI substrate 200
Silicon 203 and buried oxide layer 202 grow Heat Conduction Material above substrate silicon 201 after being etched away and are formed.In the present embodiment, heat-conducting layer institute
Specific region be located at 204 two sides of silicon ridge waveguide, at 15 μm of silicon ridge waveguide, the size of the specific region is as follows: length
For 100 μm, width 1mm.
In the present embodiment, the material of heat-conducting layer 700 includes but is not limited to: the gold such as SnAu, Ag, Cu, Au, Al, Fe, CuAl
Category or alloy material, the semiconductor materials such as polysilicon, monocrystalline silicon, amorphous silicon, germanium, graphene, graphite, carbon fiber, C/C composite wood
The inorganic non-metallic materials such as material, carbon black and heat-conducting polymer material etc.；The good metal material of preferred thermal conductivity in the present embodiment
Or highly heat-conductive material.
In the present embodiment, III-V semiconductor epitaxial layers 300 are formed by epitaxial growth of MBE or MOCVD, are not needed
Secondary epitaxy and selective area growth technology, simple process are stablized.300 structure of III-V semiconductor epitaxial layers is at least wrapped from top to bottom
It includes: p-type ohmic contact layer 301, p-type cap rock 302, active area 303, N-type ducting layer 304 and intrinsic layer 305, in III-V half
The structure made on conductor epitaxial layer 300 includes at least: III-V waveguide 306, P electrode 307 and the N electricity of multiple parallel arrangements
Pole 308, wherein P electrode 307 is produced on p-type ohmic contact layer 301, N electrode 308 be produced on N-type ducting layer 304 it
On.
In the present embodiment, p-type ohmic contact regions 301, p-type cap rock 302, active area in III-V semiconductor epitaxial layers 300
303, the material of N-type ducting layer 304 and intrinsic layer 305 includes but is not limited to following material: phosphatization steel, GaAs, gallium antimonide
The binary system of material system, ternary system, in quaternary material it is any two or more, any one ternary system, quaternary material
Component can be different numerical value, be also possible to the numerical value of gradual change.
III-V waveguide 306, by the intrinsic layer 305 in III-V semiconductor epitaxial layers 300, N-type ducting layer 304, active area
303, p-type cap rock 302 and the patterning of p-type ohmic contact regions 301 are formed, including front and rear sections wedge-shaped waveguide and the straight wave of interlude
It leads, wherein front and rear sections wedge-shaped waveguide is etched to 304 bottom of N-type ducting layer, is connected with the front and back ends of silicon ridge waveguide 204,
Interlude straight wave guide is etched to 302 lower part of p-type cap rock, and the remaining p-type cap rock 302 not being etched is located at the III-V waveguide
306 two sides；Active area is located under p-type cap rock 302, also equally is located at the two sides of the III-V waveguide 306.
In the present embodiment, wedge shape can be along the structure in the direction of III-V waveguide 306,306 both ends of III-V waveguide
Waveguide or straight wave guide, width and height can be arbitrary numerical value, by the intrinsic layer in III-V semiconductor epitaxial layers 300
305, N-type ducting layer 304, active area 303, p-type cap rock 302 and p-type ohmic contact regions 301 pattern formation, the present embodiment
In the III-V waveguide 306 include front and rear sections wedge-shaped waveguide and interlude straight wave guide, wherein front and rear sections wedge-shaped waveguide is etched
To 304 bottom of N-type ducting layer, it is connected with the front and back ends of silicon ridge waveguide 204, interlude straight wave guide is etched to p-type cap rock
302 lower parts there remains part p-type cap rock 302 and not be etched away.In the production process, the structure of 306 two sides of III-V waveguide
To be patterned by III-V semiconductor epitaxial layers 300, referring to fig. 2 in 306 two sides of III-V waveguide straight wave guide shape,
Including active area 303 and the p-type cap rock 302 not being etched；The structure of 306 two sides of III-V waveguide and the figure of III-V waveguide 306
Case can design on a photolithography plate, then using the different degree of a photoetching, etching to form 204 and of silicon ridge waveguide
The pattern of its two sides.
Shown in referring to Figures 1 and 2, intrinsic layer 305, shape is the shape of a saddle, protruding portion and interconnecting piece including both ends, wherein
The protruding parts at one both ends are covered in the top of Heat Conduction Material 700 in the two sides of silicon ridge waveguide 204；The shape of the intrinsic layer 305
It is also to be formed by patterning III-V semiconductor epitaxial layers 300.
In the disclosure, each III-V waveguide 306 is one-to-one with each silicon ridge waveguide 204, and in vertical direction
It is alignment.
In the present embodiment, the material of III-V semiconductor epitaxial layers 300 includes but is not limited to indium phosphorus system, gallium arsenic system and gallium antimony
It is the one or more of these three material systems；Active area is using the Quantum Well or quantum dot being made of indium phosphorus system, gallium arsenic system
Structure, and it is not limited to both material systems and Quantum Well, quantum dot both structures.
Preferably, the p-type cap rock 302 in III-V semiconductor epitaxial layers 300 selects InP material, with a thickness of 1.5 μm；P-type
The material of ohmic contact layer 301 is InGaAs, and production has multiple flat on p-type InP cap rock and P type InGaAs ohmic contact layer
The p-type III-V ridge waveguide of row arrangement, the width of the ridge waveguide are 5 μm, and etching depth is about near 1.3 μm, the wedge shape at both ends
The terminal end width of III-V ridge waveguide is 400nm；Active area 303 uses AlGaInAs material, and gain peak is near 1.55 μm.
In the present embodiment, SOI substrate 200 be bonded with III-V semiconductor epitaxial layers 300 by metal bonding, medium or
The mode of the bondings such as direct wafer bonding is combined together, and silicon ridge waveguide 204 and III-V waveguide 306 are respectively by SOI
Be made on substrate 200 and III-V semiconductor epitaxial layers 300, then by by the intrinsic layer 305 of the shape of a saddle with the side of physics
Formula rides over and is combined together both SOI substrate 200 and III-V semiconductor epitaxial layers 300 on heat-conducting layer 700.
Heat-conducting layer 700 is in contact with intrinsic layer 305, so that the mode that the heat that active area 303 generates leads to heat transfer passes through
It is passed in heat-conducting layer 700 by N-type ducting layer 304, intrinsic layer 305, is then passed in substrate silicon 201, is effectively improved by heat-conducting layer
The heat dissipation characteristics of silicon substrate hybrid integrated laser.
In the present embodiment, P electrode 307 is formed on p-type ohmic contact layer 301；N electrode 308 is formed in N-type wave
On conducting shell 304, there are spacing between the structure of 306 two sides of III-V waveguide, referring to shown in Fig. 3.
In the present embodiment, the setting of micro-structure 500 is to realize the lasing for adjusting the silicon substrate hybrid integrated laser 400
The effect of wavelength.The micro-structure 500 is formed in the structure of silicon ridge waveguide 204 or III-V waveguide 306, and pattern can be one
Dimension, two micro-, three-dimensional geometries, including but not limited to both structures of grating, photonic crystal.By adjusting silicon substrate mixing collection
At the parameter of the micro-structure 500 in each silicon substrate hybrid integrated laser 400 in laser array 100, the silicon may be implemented
The control and adjusting of the excitation wavelength range of base hybrid integrated laser array 100.
In the present embodiment, production has one-dimensional micro-structure 500 on silicon ridge waveguide 204, and the period is in 230 nm or so.
The metal heat-conducting layer in intrinsic layer 305 and specific region in the present embodiment, in III-V semiconductor epitaxial layers 300
700 are in contact, and N-type ducting layer 304 is in contact with silicon ridge waveguide 204, what the light that active area 303 issues was coupled by evanescent wave
Mode is coupled into silicon ridge waveguide 204 by N-type ducting layer 304, and the heat that active area 303 issues passes through N-type ducting layer
304, intrinsic layer 305 and the metal heat-conducting layer 700 of specific region import substrate silicon 201 and lose.
In second exemplary embodiment of the disclosure, a kind of preparation of silicon substrate hybrid integrated laser array is provided
Method.
The preparation method of the silicon substrate hybrid integrated laser array of the disclosure, comprising:
Step S402: the silicon ridge waveguide of multiple parallel arrangements is made on SOI substrate；
In the present embodiment, the silicon ridge waveguide 204 of multiple parallel arrangements is by the photoetching of CMOS technology, lithographic technique or photoelectron
Such as common photoetching of technique, electron beam exposure, holographic exposure, etching, focused ion beam FIB technology make in top layer silicon 203.
In the present embodiment, the buried oxide layer 202 of SOI substrate 200 with a thickness of 2 μm；Top layer silicon with a thickness of 220nm；It is pushing up
The width for multiple parallel silicon ridge waveguides 204 that layer silicon makes above is 3 μm.
Step S404: making specific region on the SOI substrate containing silicon ridge waveguide, and grows on the specific area thermally conductive
Layer 700；
In the present embodiment, specific region using CMOS technology photoetching, lithographic technique or for example common photoetching of photoelectron technique,
The technologies such as electron beam exposure, holographic exposure, etching, FIB remove the Portions of top layer silicon 203 of SOI substrate 200 and buried oxide layer 202
After formed.
Heat-conducting layer 700 is that the technologies of preparing such as thermal evaporation, magnetron sputtering are successively by way of physically or chemically depositing
Substep grows different Heat Conduction Materials and is prepared, and the succession of different Heat Conduction Materials can change；A variety of heat conduction materials are set
Material helps to improve the heat dissipating of the silicon substrate hybrid integrated laser array.
In the present embodiment, the specific region where heat-conducting layer 700 is located at 204 two sides of silicon ridge waveguide, apart from 15 μ of silicon ridge waveguide
At m, the size of the specific region is as follows: length is 100 μm, width is 1 mm.
Step S406: III-V semiconductor material successively epitaxial growth intrinsic layer, N-type ducting layer, active area, p-type lid are utilized
Layer and p-type ohmic contact layer form III-V semiconductor epitaxial layers；
In the present embodiment, III-V semiconductor epitaxial layers 300 are prepared by extension of MBE or MOCVD.
P-type ohmic contact regions 301, p-type cap rock 302, active area 303, N-type ducting layer in III-V semiconductor epitaxial layers 300
304 and the material of intrinsic layer 305 include but is not limited to following material: indium phosphide, GaAs, gallium antimonide material system binary
System, ternary system, in quaternary material it is any two or more, any one ternary system, quaternary material component can be
Different numerical value is also possible to the numerical value of gradual change.
Preferably, p-type cap rock 302 selects InP material, with a thickness of 1.5 μm；The material of p-type ohmic contact layer 301 is
InGaAs, active area 303 use AlGalnAs material, and gain peak is near 1.55 μm.
Step S408: carrying out patterned process on III-V semiconductor epitaxial layers, etch the shape of a saddle intrinsic layer,
The structure of III-V waveguide and III-V waveguide two sides grows P electrode, N electrode；
Step S408 includes: using designed figure to patterned process is carried out on III-V semiconductor epitaxial layers, so
Rear portion is sequentially etched p-type ohmic contact layer 301, p-type cap rock 302, active area 303, N-type ducting layer 304 until N-type waveguide
304 bottom of layer, form the front and rear sections wedge-shaped waveguide of III-V waveguide；Another part is sequentially etched p-type ohmic contact layer 301, p-type
Cap rock 302 forms the interlude straight wave guide of III-V waveguide until 302 lower part of p-type cap rock；P-type cap rock 302 and active area 303
The part of both sides of edges is etched away, N electrode vitellarium is formed；The remaining p-type cap rock 302 not being etched is located at the III-V wave
306 two sides are led, active area 303 is located under p-type cap rock 302, also equally is located at the two sides of the III-V waveguide 306, is formed
The structure of III-V waveguide two sides；P electrode 307 is being made on p-type ohmic contact layer 301, on N-type ducting layer 304
N electrode vitellarium make N electrode 308.
P-type III-V ridge waveguide 306 uses but is not limited to following technology of preparing, such as photoetching, electron beam exposure, holographic exposure
Light, wet etching or dry etching etc. are prepared.The preparation method of N electrode and P electrode uses this field routine preparation method,
Including thermal evaporation, magnetron sputtering etc., do not repeat here.
In the present embodiment, there are spacing between N electrode 308 and the structure of III-V waveguide two sides.
Above-mentioned designed figure includes: the shape of a saddle of protruding portion and interconnecting piece with both ends, and is in the shape of a saddle
The III-V waveguide shapes of interconnecting piece with III-V waveguide include front and rear sections wedge-shaped waveguide and interlude straight wave guide in the present embodiment
It illustrates.
Step S410: by the SOI substrate containing silicon ridge waveguide and heat-conducting layer and contain III-V waveguide, P electrode, N electrode
III-V semiconductor epitaxial layers bonding get up；
In the present embodiment, by N-type in the surface of silicon ridge waveguide 204 in SOI substrate 200 and III-V semiconductor epitaxial layers 300
The surface of ducting layer 304 contacts with each other, and is combined together in such a way that bonding chip, metal bonding or medium are bonded.
Step S412: making micro-structure on silicon ridge waveguide or the structure of III-V waveguide, completes silicon substrate hybrid integrated laser
The preparation of device array.
In the present embodiment, micro-structure 500 be can be by CMOS technology in silicon ridge waveguide 204 or photoelectron technique such as normal light
The technologies such as quarter, electron beam exposure, holographic exposure, etching, FIB are prepared in III-V waveguide 306.
The micro-structure 500 can be one-dimensional, two micro-, three-dimensional geometries, including but not limited to grating, photonic crystal knot
Structure, and number of cycles and geometric parameter can be any number.
In order to verify the beneficial effect of the silicon substrate hybrid integrated laser array, the emulation for having done two comparison structures is real
It tests, a kind of structure is silicon substrate hybrid integrated laser of the silicon ridge waveguide two sides without containing specific region and heat-conducting layer, another kind knot
Structure is the silicon substrate hybrid integrated laser that specific region and heat-conducting layer are contained in silicon ridge waveguide two sides, mixed to the silicon substrate of both structures
It closes integration laser and has carried out the experiment of heat distribution.
Fig. 4 is the silicon substrate hybrid integrated according to embodiment of the present disclosure silicon ridge waveguide two sides without containing specific region and heat-conducting layer
The profile thermal distribution schematic diagram of laser.Fig. 5 is to contain specific region and thermally conductive according to embodiment of the present disclosure silicon ridge waveguide two sides
The profile thermal distribution schematic diagram of the silicon substrate hybrid integrated laser of layer.
As shown in figure 4, silicon substrate hybrid integrated laser of the silicon ridge waveguide two sides without containing specific region and heat-conducting layer has
306 DEG C of the maximum temperature of source region, and the silicon substrate hybrid integrated laser of specific region and heat-conducting layer is contained in silicon ridge waveguide two sides
The maximum temperature of active area is 40.3 DEG C, as shown in Figure 5, it is seen then that the SOI material of the structural improvement containing specific region and heat-conducting layer
The problem of laser array heat dissipation characteristics difference caused by buried oxide layer thermal conduction characteristic difference in material, the heat in active area is passed through specific
The metal in region imports substrate silicon and dissipates, and thermal characteristics and the photoelectricity that can improve entire silicon substrate hybrid integrated laser array are special
Property.
In conclusion having good present disclose provides a kind of silicon substrate hybrid integrated laser array and preparation method thereof
Heat dissipation characteristics and photoelectric characteristic, and III-V semiconductor epitaxial material is formed by extension of MBE or MOCVD, does not need two
Selective area growth technology is extended to outside secondary, simple process is stablized；Structure on SOI can be compatible with mature CMOS technology, and technique is steady
Fixed, reproducible, low manufacture cost；Structure on III-V semiconductor material can be simultaneous with traditional photoelectron technology
Hold, has higher repeatability in production.
Certainly, according to actual needs, silicon substrate hybrid integrated laser array of the disclosure and preparation method thereof also includes it
His element, technique and step, since the innovation of the same disclosure is unrelated, details are not described herein again.
It should also be noted that, the direction term mentioned in embodiment, for example, "upper", "lower", "front", "rear", " left side ",
" right side " etc. is only the direction with reference to attached drawing, not is used to limit the protection scope of the disclosure.Through attached drawing, identical element by
Same or similar appended drawing reference indicates.When may cause understanding of this disclosure and cause to obscure, conventional structure will be omitted
Or construction.And the shape and size of each component do not reflect actual size and ratio in figure, and only illustrate the embodiment of the present disclosure
Content.In addition, in the claims, any reference symbol between parentheses should not be configured to the limit to claim
System.
Furthermore word "comprising" or " comprising " do not exclude the presence of element or step not listed in the claims.Positioned at member
Word "a" or "an" before part does not exclude the presence of multiple such elements.
In addition, unless specifically described or the step of must sequentially occur, there is no restriction in the above institute for the sequence of above-mentioned steps
Column, and can change or rearrange according to required design.And above-described embodiment can be based on the considerations of design and reliability, that
This mix and match is used using or with other embodiments mix and match, i.e., the technical characteristic in different embodiments can be freely combined
Form more embodiments.
Particular embodiments described above has carried out further in detail the purpose of the disclosure, technical scheme and beneficial effects
Describe in detail it is bright, it is all it should be understood that be not limited to the disclosure the foregoing is merely the specific embodiment of the disclosure
Within the spirit and principle of the disclosure, any modification, equivalent substitution, improvement and etc. done should be included in the guarantor of the disclosure
Within the scope of shield.
Claims (10)
1. a kind of silicon substrate hybrid integrated laser array, comprising: be produced on more on SOI substrate and III-V semiconductor epitaxial layers
The silicon substrate hybrid integrated laser of a parallel arrangement；
Wherein, each silicon substrate hybrid integrated laser includes: silicon ridge waveguide；Heat-conducting layer, positioned at the given zone of silicon ridge waveguide two sides
In domain, which is that SOI substrate removes the region obtained after top layer silicon and buried oxide layer；Intrinsic layer, shape are the shape of a saddle,
Protruding portion and interconnecting piece including both ends, wherein the protruding portion at a both ends is covered in above heat-conducting layer；N-type ducting layer, is formed in
On the interconnecting piece of intrinsic layer；Active area is formed on N-type ducting layer；P-type cap rock, is formed on active area；III-V
Waveguide is formed by III-V semiconductor epitaxial pattern layers, and both ends are connected with the front and back ends of silicon ridge waveguide, and the structure of two sides is
The active area of the p-type cap rock and lower section that are not etched after patterning；P-type ohmic contact layer is located on III-V waveguide；P electricity
Pole is located on p-type ohmic contact layer；And N electrode, it is located on N-type ducting layer.
2. silicon substrate hybrid integrated laser array according to claim 1, wherein the SOI substrate and III-V semiconductor
Epitaxial layer is combined together by way of bonding, and the mode of the bonding includes: that metal bonding, medium bonding or chip are direct
Bonding, respectively by being made on SOI substrate and III-V semiconductor epitaxial layers, then silicon ridge waveguide and III-V waveguide are
It, will be outside SOI substrate and III-V semiconductor by the way that the protruding portion at a both ends of the intrinsic layer of the shape of a saddle to be covered on heat-conducting layer
Prolong both layers to be combined together.
3. silicon substrate hybrid integrated laser array according to claim 1, wherein each III-V waveguide and each
The silicon ridge waveguide is one-to-one, and is alignment in vertical direction.
4. silicon substrate hybrid integrated laser array according to claim 1, in which:
The SOI substrate successively includes: substrate silicon, buried oxide layer and top layer silicon from bottom to top, and the silicon ridge waveguide is SOI substrate
Made by patterning, be by SOI substrate top layer silicon it is patterned, etching after formed；
The III-V semiconductor epitaxial layers successively include: intrinsic layer from bottom to top, N-type ducting layer, active area, p-type cap rock and
P-type ohmic contact layer, the III-V waveguide are III-V semiconductor epitaxial layers by patterning, then etch p-type Ohmic contact
What layer, p-type cap rock, active area and N-type ducting layer were made.
5. silicon substrate hybrid integrated laser array according to claim 4, in which:
Along the direction of the silicon ridge waveguide, the structure at the silicon ridge waveguide both ends includes: wedge-shaped ridge waveguide and/or straight ridge waveguide；
Along the direction of the III-V waveguide, the structure at the III-V waveguide both ends includes: wedge-shaped ridge waveguide and/or straight ridge ripple
It leads.
6. silicon substrate hybrid integrated laser array according to claim 5, wherein the III-V waveguide includes: forward and backward
The wedge-shaped waveguide of section and the straight wave guide of interlude, front and rear sections wedge-shaped waveguide is patterned to be etched to N-type ducting layer bottom, with silicon
The front and back ends of ridge waveguide are connected, and interlude straight wave guide is etched to p-type cap rock lower part；The remaining p-type cap rock not being etched
Positioned at the two sides of the III-V waveguide, active area is located under p-type cap rock, also equally is located at the two sides of the III-V waveguide.
7. silicon substrate hybrid integrated laser array according to claim 1, in which:
The material of the heat-conducting layer includes:
Metal or alloy material, comprising: SnAu, Sn, Ag, Cu, Au, Al, Fe or CuAl；
Semiconductor material, comprising: polysilicon, monocrystalline silicon, amorphous silicon or germanium；
Inorganic non-metallic material, comprising: graphene, graphite, carbon fiber, C/C composite material or carbon black；And
Heat-conducting polymer material；And/or
P-type ohmic contact regions in the III-V semiconductor epitaxial layers, p-type cap rock, active area, N-type ducting layer and intrinsic layer
Material includes: indium phosphide, GaAs, the binary system of gallium antimonide material system, ternary system, any two kinds or more in quaternary material
Kind.
8. silicon substrate hybrid integrated laser array according to any one of claims 1 to 7, further includes:
Micro-structure is formed in the structure of silicon ridge waveguide or III-V waveguide.
9. silicon substrate hybrid integrated laser array according to claim 8, wherein the pattern of the micro-structure includes: one
Dimension, two micro-, three-dimensional geometries, structure includes: grating, photonic crystal or microflute；By adjusting each silicon substrate hybrid integrated
The parameter of micro-structure in laser, can be realized the excitation wavelength range of the silicon substrate hybrid integrated laser array control and
It adjusts.
10. a kind of preparation method of silicon substrate hybrid integrated laser array, comprising:
The silicon ridge waveguide of multiple parallel arrangements is made on SOI substrate；
Specific region is made on the SOI substrate containing silicon ridge waveguide, and grows heat-conducting layer on the specific area；
Utilize III-V semiconductor material successively epitaxial growth intrinsic layer, N-type ducting layer, active area, p-type cap rock and p-type ohm
Contact layer forms III-V semiconductor epitaxial layers；
Patterned process is carried out on III-V semiconductor epitaxial layers, etch the intrinsic layer of the shape of a saddle, III-V waveguide and
The structure of III-V waveguide two sides grows P electrode, N electrode；
By the SOI substrate containing silicon ridge waveguide and heat-conducting layer with containing III-V waveguide, P electrode, N electrode III-V semiconductor outside
Prolong layer bonding；And
Micro-structure is made on silicon ridge waveguide or the structure of III-V waveguide, completes the preparation of silicon substrate hybrid integrated laser array.
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