CN109449209A - Power device and preparation method thereof - Google Patents
Power device and preparation method thereof Download PDFInfo
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- CN109449209A CN109449209A CN201811277070.6A CN201811277070A CN109449209A CN 109449209 A CN109449209 A CN 109449209A CN 201811277070 A CN201811277070 A CN 201811277070A CN 109449209 A CN109449209 A CN 109449209A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 229920005591 polysilicon Polymers 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 23
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 3
- 240000007594 Oryza sativa Species 0.000 claims 1
- 235000007164 Oryza sativa Nutrition 0.000 claims 1
- 235000009566 rice Nutrition 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 description 13
- 230000004888 barrier function Effects 0.000 description 11
- 239000000463 material Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000001657 homoepitaxy Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000001534 heteroepitaxy Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- 238000004140 cleaning Methods 0.000 description 1
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- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 230000026267 regulation of growth Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thyristors (AREA)
Abstract
It includes substrate that the present invention, which provides a kind of power device, form the first epitaxial layer on substrate, groove is formed down from the upper surface of the first epitaxial layer, it is formed in the second epitaxial layer of the bottom of groove, through the groove of the second epitaxial layer, third epitaxial layer is filled in groove, it is formed in the fourth epitaxial layer of the upper surface of third epitaxial layer and the second epitaxial layer, the concentration of third epitaxial layer is greater than the concentration of fourth epitaxial layer, body area is downwardly extending positioned at the upper surface of the two sides of fourth epitaxial layer from the first epitaxial layer, the source region being downwardly extending from the intersection in fourth epitaxial layer and body area, it is formed in the first epitaxial layer, the oxide layer of the upper surface of body area and fractional source regions, polysilicon layer positioned at the upper surface of oxide layer, dielectric layer positioned at the upper surface of polysilicon layer and fractional source regions, positioned at dielectric layer, fractional source regions and fourth epitaxial layer The metal layer of upper surface.The present invention also provides the preparation methods of power device, enhance the ability of working performance and pulse avalanche energy.
Description
Technical field
The invention belongs to semiconductor chip fabrication process technical field more particularly to power devices and preparation method thereof.
Background technique
Pulse avalanche energy (abbreviation EAS) is planar vertical double diffused metal-oxide semiconductor field effect crystal
A very important parameter of (VDMOS) device is managed, is the vertical double diffused metal-oxidation of single avalanche condition lower plane type
The ceiling capacity that object semiconductor FET device can consume.Answering for larger due to voltage spikes can be generated in source electrode and drain electrode
With under environment, it is necessary to consider planar vertical double diffused metal-oxide semiconductor field effect transistor device pulse
Avalanche energy.
Planar vertical double diffused metal-oxide semiconductor field effect transistor is one of power device, due to
There are a parasitic triodes between epitaxial layer-body area-source region for itself, when the device is switched off, the reverse current between source and drain
When flowing through body area, pressure drop can be generated.If generate pressure drop be greater than parasitic triode cut-in voltage, this reverse current can because
Parasitic triode is connected the amplification of parasitic triode, causes out of control, and the pulse avalanche energy of power device is made to fail.
Above-mentioned power device failure in order to prevent, needs that parasitic triode is prevented to be connected, and the prior art mainly passes through polycrystal etching window,
Or stopped using side wall, do the injection of the area autoregistration Shen Ti.The area Shen Ti and ring region are injected simultaneously to be driven in, since the area Shen Ti is in source region
It is formed after production, therefore cannot drive in too deep, otherwise influence whether source region and channel, but the shallower area Shen Ti again cannot be effective
Promote the ability of the pulse avalanche energy of the power device.
Summary of the invention
In view of this, the present invention provides a kind of power device for reducing body area resistance, enhancing working performance, it is above-mentioned to solve
, on the one hand, the present invention is realized using following technical scheme.
A kind of power device comprising:
The substrate of first conduction type；
Form the first epitaxial layer of the first conduction type over the substrate；
Groove is formed down from the upper surface of first epitaxial layer；
It is formed in the second epitaxial layer of the first conduction type of the bottom of the groove；
The third epitaxial layer of the second conduction type is filled in the groove of second epitaxial layer, the groove；
It is formed in the fourth epitaxial of the second conduction type of the upper surface of the third epitaxial layer and second epitaxial layer
Layer, the concentration of the third epitaxial layer are greater than the concentration of the fourth epitaxial layer；
It second is led positioned at what the upper surface of the two sides of the fourth epitaxial layer from first epitaxial layer was downwardly extending
The body area of electric type；
The source region for the first conduction type being downwardly extending from the intersection in the fourth epitaxial layer and the body area；
Be formed in first epitaxial layer, the body area and the part source region upper surface oxide layer；
Polysilicon layer positioned at the upper surface of the oxide layer；
Dielectric layer positioned at the upper surface of the polysilicon layer and the part source region；Positioned at the dielectric layer, part institute
State the metal layer of the upper surface of source region and the fourth epitaxial layer.
The present invention provides the having the beneficial effect that by making second epitaxial layer, the third extension of a kind of power device
Layer and second epitaxial layer form similar super-junction structure, and when the power device is reverse-biased, the super-junction structure can be prevented
The punch through of the body area and first epitaxial layer occurs, to improve the working performance of the power device.Described
The concentration of three epitaxial layers is greater than the concentration of the fourth epitaxial layer, and the fourth epitaxial layer can reduce the area in the body area,
The resistance for reducing the body area effectively prevent parasitic triode (the first epitaxial layer-body area-source region) to be connected, promotes the function
The ability of the pulse avalanche energy of rate device, enhances the stability of the power device.
On the other hand, the present invention also provides a kind of preparation methods of the power device of power device comprising following technique
Step:
S401: the substrate of first conduction type is provided, is formed outside the first of the first conduction type over the substrate
Prolong layer；
S402: one layer of thin oxide layer is first deposited on first epitaxial layer, then removes the upper of first epitaxial layer
The part on the surface thin oxide layer exposes first epitaxial layer, and corresponding position performs etching to be formed from first epitaxial layer
The downward groove in upper surface；
S403: the groove bottom formed the first conduction type the second epitaxial layer, to second epitaxial layer into
It goes back and carves the groove that formation runs through second epitaxial layer, the third epitaxial layer of the second conduction type is filled in the groove；
S404: it is formed outside the 4th of the second conduction type in the upper surface of second epitaxial layer and the third epitaxial layer
Prolong layer, the concentration of the third epitaxial layer is greater than the concentration of the fourth epitaxial layer；
S405: the is downwardly extending in the upper surface of the two sides from first epitaxial layer that are located at the fourth epitaxial layer
The body area of two conduction types；
S406: first in the upper surface formation oxide layer for stating the first epitaxial layer, the body area and the part source region, position
Polysilicon layer is formed in the upper surface of the oxide layer；
S407: the source for the first conduction type being downwardly extending from the intersection in the fourth epitaxial layer and the body area
Area；
S408: dielectric layer is formed in the upper surface for being located at the polysilicon layer and the part source region, is located at the medium
The upper surface of layer, the part source region and the fourth epitaxial layer forms metal layer, finally obtains power device.
The present invention is deposited on first epitaxial layer by the way that the first epitaxial layer of the first conduction type is formed on the substrate
One layer of thin oxide layer, the thin oxide layer can reduce the surface stress of first epitaxial layer, can be with as etching barrier layer
The etching of selectivity forms the groove.The third epitaxial layer is between second epitaxial layer, and the third extension
Layer is different from the conduction type of second epitaxial layer, makes second epitaxial layer, outside the third epitaxial layer and described second
Prolong layer and form super-junction structure, when the power device is reverse-biased, the super-junction structure realizes high voltage, prevents the body area and institute
The punch through for stating the first epitaxial layer occurs, and improves the reliability of the power device.The third is formed in the groove
Epitaxial layer and the fourth epitaxial layer reduce the area in the body area, reduce the resistance in the body area, make outside described first
Prolonging the parasitic triode that floor, the body area and the source region are constituted can not be connected, and improve the pulse snow of the power device
The ability for collapsing energy enhances the reliability of the power device.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is the structural schematic diagram of power device of the present invention；
Fig. 2 to Figure 14 is the preparation process figure of power device of the present invention；
Figure 15 is the preparation flow figure of power device of the present invention；
In figure: power device 1；Substrate 10；First epitaxial layer 20；Thin oxide layer 30；Groove 31；Second epitaxial layer 32；Nitrogen
SiClx layer 33；Side wall 34；Groove 35；Third epitaxial layer 36；Fourth epitaxial layer 37；Body area 38；Oxide layer 40；Polysilicon layer 41；
Source region 42；Dielectric layer 43；Metal layer 44.
Specific embodiment
In order to be more clearly understood that the specific technical solution of the present invention, feature and advantage, with reference to the accompanying drawing and have
The present invention is further described in detail for body embodiment.
In the description of the present invention, it should be noted that term " on ", "lower", "left", "right", " transverse direction ", " longitudinal direction ",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings, or be somebody's turn to do
Invention product using when the orientation or positional relationship usually put, be merely for convenience of description of the present invention and simplification of the description, without
It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore not
It can be interpreted as limitation of the present invention.In addition, term " first ", " second ", " third " etc. are only used for distinguishing description, and cannot manage
Solution is indication or suggestion relative importance.
Refering to fig. 1, on the one hand, the present invention provides a kind of power device 1 comprising:
The substrate 10 of first conduction type；
It is formed in the first epitaxial layer 20 of the first conduction type on the substrate 10；
Groove 31 is formed down from the upper surface of first epitaxial layer 20；
It is formed in the second epitaxial layer 32 of the first conduction type of the bottom of the groove 31；
Through the groove 35 of second epitaxial layer 32, the third extension of the second conduction type is filled in the groove 35
Layer 36；
It is formed in the 4th of the second conduction type of the upper surface of the third epitaxial layer 36 and second epitaxial layer 32 the
Epitaxial layer 37, the concentration of the third epitaxial layer 36 are greater than the concentration of the fourth epitaxial layer 37；
Upper surface positioned at the two sides of the fourth epitaxial layer 37 from first epitaxial layer 20 is downwardly extending second
The body area 38 of conduction type；
The source for the first conduction type being downwardly extending from the intersection in the fourth epitaxial layer 36 and the body area 38
Area 42；
Be formed in first epitaxial layer 20, the body area 38 and the part source region 42 upper surface oxide layer 40；
Polysilicon layer 41 positioned at the upper surface of the oxide layer 40；
Dielectric layer 43 positioned at the upper surface of the polysilicon layer 41 and the part source region 42；
Metal layer 44 positioned at the dielectric layer 43, the upper surface of the part source region 42 and the fourth epitaxial layer 36.
The present invention is formed in first epitaxial layer 20 and is alternatively arranged by forming the first epitaxial layer 20 on substrate 10
The second epitaxial layer 32, form the third epitaxial layer 36 of the second conduction type between second epitaxial layer 32, make described second
Epitaxial layer 32, the third epitaxial layer 35 and second epitaxial layer 32 form super-junction structure, reverse-biased in the power device 1
When, the super-junction structure can prevent the body area 38 and the punch through of first epitaxial layer 20 from occurring, to improve institute
State the working performance of power device 1.The concentration of the third epitaxial layer 36 is greater than the concentration of the fourth epitaxial layer 37, completes
After preparing the third epitaxial layer 35, the fourth epitaxial layer 36 is set to fill up the groove 31, the fourth epitaxial layer
37 can reduce the area in the body area 38, reduce the resistance in the body area 38, effectively prevent first epitaxial layer 20, institute
The parasitic triode conducting that the area Shu Ti 38 and the source region 42 are constituted, promotes the pulse avalanche energy of the power device 1
Ability enhances the stability of the power device 1.
Further, second epitaxial layer 32 is identical as the junction depth of the third epitaxial layer 36, the knot in the body area 38
The deep junction depth for being less than the fourth epitaxial layer 37.In the present embodiment, second epitaxial layer 32 is arranged at the ditch
The bottom of slot 31 forms the fourth epitaxial layer 37 that doping concentration is less than the third epitaxial layer 36, institute convenient for subsequently epitaxial growing
The junction depth in the area Shu Ti 38 is less than the fourth epitaxial layer 37, reduces the resistance in the body area 38, reduces the power device 1
Forward voltage drop improve the stability of the power device 1 to make parasitic triode that can not be connected.It is described being parallel to
On the direction of the upper surface of substrate 10, second epitaxial layer 32, the third epitaxial layer 36 and 32 shape of the second epitaxial layer
At super-junction structure, when the power device 1 is reverse-biased, the pressure-resistant performance of the power device 1 is can be improved in the super-junction structure.
Further, the doping concentration of the substrate 10 is greater than the doping concentration of first epitaxial layer 20, the body area
38 concentration is less than the concentration of the fourth epitaxial layer 37.In the present embodiment, the substrate 10 is N-type, outside described first
Prolonging layer 20 is N-type, and the body area 38 is p-type, and the fourth epitaxial layer 37 is p-type, and the fourth epitaxial layer 37 reduces described
The area in body area 38 reduces the resistance in the body area 38, and the reverse current in the power device 1 flows through the source region 42
And when the fourth epitaxial layer 37, do not turn on parasitic triode, to improve the pulse snowslide energy of the power device 1
The ability of amount.
Refering to Fig. 2 to Figure 15, on the other hand, the present invention also provides a kind of preparation methods of power device 1 comprising following
Processing step:
S401: providing the substrate 10 of first conduction type, and the of the first conduction type is formed on the substrate 10
One epitaxial layer 20；
Referring to Fig.2, the material of the substrate 10 can be silicon specifically, providing the substrate 10 of first conduction type
Or germanium, in the present embodiment, the substrate is heavy doping, and resistivity is in 0.002-0.01 ohm of * cm ranges, described the
One epitaxial layer 20 is to be lightly doped, and selects material of the high purity silicon as substrate 10, in this way, being easy to implement, and can reduce manufacture
Cost.Epitaxial growth can be homogeneity epitaxial layer, be also possible to epitaxially deposited layer, preferred homoepitaxy in present embodiment, i.e.,
The substrate 10 is the first conduction type, and first epitaxial layer 20 is the first conduction type, in other embodiments, according to
The conduction type of actual conditions, the substrate 10 and first epitaxial layer 20 can be the same or different.Same realization is outer
Prolonging growth also has a many methods, including molecular beam epitaxy, ultra-high vacuum CVD, normal pressure and reduced pressure epitaxy etc., can be with
First epitaxial layer 20 met the requirements.In present embodiment, using low pressure homoepitaxy, extension: refer in monocrystalline
On substrate, press the technical process that 10 crystal orientation of substrate grows monocrystal thin films.Homoepitaxy: one epitaxial layer 20 of growth regulation and substrate 10 are
Same material, this technique are homoepitaxy, this kind of simple process, but higher cost.Hetero-epitaxy: the film of epitaxial growth
Material and substrate 10 material are different, grow in other words chemical constituent, even physical structure and substrate it is entirely different first outside
Prolong layer 20, corresponding technique is just called hetero-epitaxy, and this kind of complex process, cost is relatively low, it is available meet the requirements it is certain
First epitaxial layer 20 of thickness is convenient for subsequent preparation process.
S402: one layer of thin oxide layer 30 is first deposited on first epitaxial layer 20, then removes first epitaxial layer
The part of the 20 upper surface thin oxide layer 30 exposes first epitaxial layer 20, and corresponding position performs etching to be formed described in
The downward groove 31 in the upper surface of first epitaxial layer 20；
Refering to Fig. 3, specifically, first use thermal oxidation method the upper surface of first epitaxial layer 20 formed a layer thickness for
Thin oxide layer 30 between 0.8~1 micron removes the part thin oxide layer 30, remaining part using dry etching later
The thin oxide layer 30 is used as etching barrier layer, exposes first epitaxial layer 20 using dry method removing the thin oxide layer 30
Etching forms the groove 31 that depth is 8~10 microns, and in the present embodiment, the thin oxide layer 30 can remove described first
The surface stress of epitaxial layer 20, is convenient for subsequent preparation process, and the thin oxide layer 30 is also used as etching barrier layer selection
Property etching form the groove 31 that meets the requirements.
S403: the second epitaxial layer 32 of the first conduction type is formed in the bottom of the groove 31, to second extension
Layer 32 carries out back forming the groove 35 for running through second epitaxial layer 32 quarter, filled with the second conduction type in the groove 35
Third epitaxial layer 36；
Refering to Fig. 4 and Fig. 5, specifically, first forming the first conduction type using Low Pressure Epitaxial Technique in the groove 31
The second epitaxial layer 32, there is a spaced thin oxide layer 30 in the upper surface of first epitaxial layer 20, outside described second
Prolong layer 32 to fill up the groove 31, later planarize second epitaxial layer 32, convenient for subsequent to second epitaxial layer
32 perform etching.The second epitaxial layer 32 in the groove 31 is performed etching, the institute for being located at the bottom of the groove 31 is retained
State the second epitaxial layer 32 with a thickness of between 4~5 microns, be convenient for subsequent preparation process.
In addition, before forming the groove 35 through second epitaxial layer 32 further include: in the thin oxide layer 30 and
The upper surface of second epitaxial layer 32 deposits one layer of silicon nitride layer 33, carve formation positioned at institute to the silicon nitride layer 33
The side wall 34 of the side wall of groove 31 is stated, etching removal later is not passed through by second epitaxial layer 32 formation that the side wall 34 covers
The groove 35 for wearing second epitaxial layer 32 removes the thin oxide layer 30 and the side wall 34 after the completion.
Refering to Fig. 6, Fig. 7 and Fig. 8, specifically, first in the upper surface of second epitaxial layer 32 and the thin oxide layer 30
The silicon nitride layer 33 that a layer thickness is 2~3 microns is deposited, the silicon nitride layer in the groove 31 is removed using dry etching technology
33 and the thin oxide layer 30 upper surface silicon nitride layer 33, retain the side wall of the groove 31 silicon nitride layer 33 formed side
Wall 34 is not run through by second epitaxial layer 32 formation that the silicon nitride layer 33 covers using dry etching technology removal later
The groove 35 of second epitaxial layer 32 removes the thin oxide layer 30 and the side wall using wet etching technique after the completion
34, the third epitaxial layer 36 is formed using Low Pressure Epitaxial Technique in the groove 35, second epitaxial layer 32 with it is described
The conduction type of third epitaxial layer 36 is different, in the present embodiment, outside the thickness of the third epitaxial layer 35 and described second
The thickness for prolonging layer 32 is identical, is convenient for subsequent second epitaxial layer 32, the third epitaxial layer 36 and second epitaxial layer 32
It forms super-junction structure and realizes partial pressure, improve the reverse withstand voltage performance of the power device 1.
S404: the of the second conduction type is formed in the upper surface of second epitaxial layer 32 and the third epitaxial layer 36
Four epitaxial layers 37, the concentration of the third epitaxial layer 36 are greater than the concentration of the fourth epitaxial layer 37；
Refering to Fig. 9, specifically, in the upper surface of second epitaxial layer 32 and the third epitaxial layer 35 using outside low pressure
Prolong technology and form the fourth epitaxial layer 37 for just filling up the groove 31, is carried out in the upper surface of first epitaxial layer 20 flat
Change processing, the fourth epitaxial layer 36 can reduce the area for being subsequently formed the body area 38, the fourth epitaxial layer 36 it is dense
Degree is less than the concentration of the third epitaxial layer 36, can reduce between the third epitaxial layer 36 and the fourth epitaxial layer 37
Contact resistance can also reduce the resistance in the subsequent body area 38, improve the energy of the pulse avalanche energy of the power device 1
Power.
S405: shape is extended downwardly in the upper surface of the two sides from first epitaxial layer 20 that are located at the fourth epitaxial layer 37
At the body area 38 of the second conduction type；
Refering to fig. 10, specifically, the body area 38 is formed using dry etching in the two sides of the fourth epitaxial layer 37,
In present embodiment, the detailed process in the body area 38 is formed are as follows: outside described the first of the two sides of the fourth epitaxial layer 37
Prolong and form etching barrier layer on layer 20, then form photoresist layer on etching barrier layer, later using with the body area 38
The mask plate of figure is exposed the photoresist layer, then develops, and obtains the photoresist with 37 figure of body area
Layer.Using the photoresist layer with 38 figure of body area as exposure mask, using lithographic methods such as reactive ion etching methods, hindered in etching
Etching forms the figure opening in the body area 38 in barrier.Then it is with the etching barrier layer being open with 38 figure of body area
Exposure mask removes first epitaxial layer 20 for the barrier layer covering that is not etched using the methods of wet etching or dry etching
Region, and then the body area 38 is formed in first epitaxial layer 20, the removal photoetching of the methods of chemical cleaning hereafter can be used
Glue-line and etching barrier layer.It in above process, can also be between photoresist layer and etching barrier layer in order to guarantee exposure accuracy
Form anti-reflecting layer.After being formed in the fourth epitaxial layer 36 due to the body area 38, the fourth epitaxial layer 37 is reduced
The area in the body area 38 subtracts the forward voltage drop of the subsequent power device 1 to reduce the resistance in the body area 38
It is small, further improve the ability of the pulse avalanche energy of the power device 1.
S406: oxygen first is formed in the upper surface of first epitaxial layer 20, the body area 38 and the fourth epitaxial layer 37
Change layer 40, forms polysilicon layer 41 positioned at the upper surface of the oxide layer 40；
Refering to fig. 11, it is first heavy in the upper surface of first epitaxial layer 20, the body area 38 and the fourth epitaxial layer 37
Product layer of oxide layer 40, removes the oxide layer 40, Zhi Hou of the upper surface in the fourth epitaxial layer 36 and part the body area 37
The upper surface of the oxide layer 40 forms polycrystal layer 41.In the present embodiment, the oxide layer 40 is formed using thermal oxidation method,
The oxide layer 40 is the gate oxide of the power device 1, and the polysilicon layer 41 is the polysilicon gate of the power device 1
Pole, it will be understood that preferably first prepare the gate structure to form the power device 1, prepare to form the power device 1 later
Source configuration, it is ensured that the parameter stability of the power device 1.
S407: the first conduction type is downwardly extending from the intersection in the fourth epitaxial layer 37 and the body area 38
Source region 42；
Refering to fig. 12, specifically, in the intersection of the body area 38 and the fourth epitaxial layer 37 using light shield, exposure.
The figure for showing the source region 42, the ion for injecting the first conduction type later form source region 42.In present embodiment
In, the ion of first conduction type is phosphorus, and the doping concentration of the source region 42 is greater than the doping concentration in the body area 38, institute
The parasitic triode that the first epitaxial layer 20, the body area 38 and the source region 42 form the power device 1 is stated, is reduced described
The area in body area 38, the body area 38 and the contact resistance of the source region 42 reduce, described in the power device 1 shutdown
Parasitic triode does not turn on, so that it is guaranteed that the ability of the pulse snowslide energy energy of the power device 1, enhances the function
The reliability of rate device 1.
S408: dielectric layer 43 is formed in the upper surface for being located at the polysilicon layer 41 and the part source region 42, is located at institute
The upper surface for stating dielectric layer 43, the part source region 42 and the fourth epitaxial layer 36 forms metal layer 44, finally obtains power
Device 1.
3 and Figure 14 refering to fig. 1, specifically, in the polysilicon layer 41, the source region 42 and the fourth epitaxial layer 37
Upper surface forms dielectric layer 43, removes the dielectric layer 43, Zhi Hou of the upper surface of the source region 42 and the fourth epitaxial layer 37
The upper surface of the dielectric layer 43, the part source region 42 and the fourth epitaxial layer 37 is using magnetron sputtering technique filling gold
Belong to, rapid thermal annealing forms metal layer 44 later.In the present embodiment, the material of the preferably described metal layer 44 is aluminium, finally
Obtain the power device 1.
In the present embodiment, the first conduction type is N-type, and the second conduction type is p-type, and the oxide layer 40 is described
The grid oxic horizon of power device 1, the polysilicon layer 41 are the polysilicon gate of the power device 1, the metal layer 44
For the source metal of the power device 1.
The present invention on substrate 10 by forming the first epitaxial layer 20 of the first conduction type, in first epitaxial layer 20
One layer of thin oxide layer 30 of upper deposition, the thin oxide layer 30 can reduce the surface stress of first epitaxial layer 20, and conduct
The etching of the etching barrier layer property of can choose forms the groove 31.The third epitaxial layer 35 is located at second epitaxial layer 32
Between, and the third epitaxial layer 36 is different from the conduction type of second epitaxial layer 32, makes second epitaxial layer 32, institute
It states third epitaxial layer 36 and second epitaxial layer 32 forms super-junction structure, when the power device 1 is reverse-biased, the superjunction knot
Structure realizes high voltage, prevents the body area 38 and the punch through of first epitaxial layer 20 from occurring, improves the power device
The reliability of part 1.The third epitaxial layer 36 and the fourth epitaxial layer 37 are formed in the groove 31, reduces the body area
38 junction area reduces the resistance in the body area 38, makes 42 structure of first epitaxial layer 20, the body area 38 and the source region
At parasitic triode can not be connected, improve the ability of the pulse avalanche energy of the power device 1, enhance the function
The reliability of rate device 1.
The above described is only a preferred embodiment of the present invention, being not intended to limit the present invention in any form.This
Although invention has been used as preferred embodiment to announce as above, however, it is not intended to limit the invention.It is any to be familiar with this field
Technical staff utilizes the methods and techniques of the disclosure above in the case where not departing from Spirit Essence of the invention and technical solution
Content makes many possible changes and modifications or equivalent example modified to equivalent change to technical solution of the present invention,
Still fall within the range of technical solution of the present invention protection.
Claims (10)
1. a kind of power device, characterized in that it comprises:
The substrate of first conduction type；
Form the first epitaxial layer of the first conduction type over the substrate；
Groove is formed down from the upper surface of first epitaxial layer；
It is formed in the second epitaxial layer of the first conduction type of the bottom of the groove；
The third epitaxial layer of the second conduction type is filled in the groove of second epitaxial layer, the groove；
It is formed in the fourth epitaxial layer of the second conduction type of the upper surface of the third epitaxial layer and second epitaxial layer, institute
The concentration for stating third epitaxial layer is greater than the concentration of the fourth epitaxial layer；
The second conductive-type being downwardly extending positioned at the upper surface of the two sides of the fourth epitaxial layer from first epitaxial layer
The area Xing Ti；
The source region for the first conduction type being downwardly extending from the intersection in the fourth epitaxial layer and the body area；
Be formed in first epitaxial layer, the body area and the part source region upper surface oxide layer；
Polysilicon layer positioned at the upper surface of the oxide layer；
Dielectric layer positioned at the upper surface of the polysilicon layer and the part source region；
Metal layer positioned at the dielectric layer, the upper surface of the part source region and the fourth epitaxial layer.
2. power device according to claim 1, it is characterised in that: second epitaxial layer and the third epitaxial layer
Junction depth is identical, and the junction depth in the body area is less than the junction depth of the fourth epitaxial layer.
3. power device according to claim 1, it is characterised in that: the doping concentration of the substrate is greater than outside described first
Prolong the doping concentration of layer, the concentration in the body area is less than the concentration of the fourth epitaxial layer.
4. a kind of preparation method of power device as described in claim 1, which is characterized in that it is comprised the following steps that:
S401: the substrate of first conduction type is provided, forms the first epitaxial layer of the first conduction type over the substrate；
S402: one layer of thin oxide layer is first deposited on first epitaxial layer, then removes the upper surface of first epitaxial layer
The part thin oxide layer expose first epitaxial layer, corresponding position performs etching to be formed from the upper of first epitaxial layer
The downward groove in surface；
S403: the second epitaxial layer of the first conduction type is formed in the bottom of the groove, second epitaxial layer is returned
The groove for being formed and running through second epitaxial layer is carved, the third epitaxial layer of the second conduction type is filled in the groove；
S404: the fourth epitaxial of the second conduction type is formed in the upper surface of second epitaxial layer and the third epitaxial layer
Layer, the concentration of the third epitaxial layer are greater than the concentration of the fourth epitaxial layer；
S405: second is downwardly extending in the upper surface of the two sides from first epitaxial layer that are located at the fourth epitaxial layer and is led
The body area of electric type；
S406: oxide layer first is formed in the upper surface of first epitaxial layer, the body area and the fourth epitaxial layer, is located at institute
The upper surface for stating oxide layer forms polysilicon layer；
S407: the source region of the first conduction type is downwardly extending from the intersection in the fourth epitaxial layer and the body area；
S408: dielectric layer is formed in the upper surface for being located at the polysilicon layer and the part source region, is located at the dielectric layer, portion
Divide the upper surface of the source region and the fourth epitaxial layer to form metal layer, finally obtains power device.
5. the preparation method of power device according to claim 4, it is characterised in that: described thin in the step S402
Oxide layer with a thickness of between 0.8~1 micron, the groove is formed using dry etching technology, the depth of the groove is 8~
Between 10 microns.
6. the preparation method of power device according to claim 4, it is characterised in that: in the step S403, form institute
Planarized after stating the second epitaxial layer, second epitaxial layer of reservation with a thickness of between 4~5 microns, second epitaxial layer
Concentration be greater than first epitaxial layer concentration.
7. the preparation method of power device according to claim 4, which is characterized in that in the step S403, formed
It is arranged at before the second epitaxial layer of the channel bottom further include: in the thin oxide layer and second epitaxial layer
Upper surface deposits one layer of silicon nitride layer, carries out back carving the side wall for forming the side wall for being located at the groove to the silicon nitride layer, it
Second epitaxial layer that etching removal is not covered by the side wall afterwards, removes the thin oxide layer and the side wall.
8. the preparation method of power device according to claim 7, it is characterised in that: the silicon nitride layer with a thickness of 2
~3 microns, the concentration of second epitaxial layer is 8E15~1E16, and the concentration of the third epitaxial layer is 5E15~8E15, institute
The concentration for stating fourth epitaxial layer is 2E15~3E15.
9. the preparation method of power device according to claim 7, it is characterised in that: remove institute using wet etching technique
Thin oxide layer and the side wall are stated, the thickness of the third epitaxial layer identical as the thickness of second epitaxial layer is 4~5 micro-
Between rice.
10. the preparation method of power device according to claim 4, it is characterised in that: described in the step S407
The doping concentration in body area is less than the doping concentration of the fourth epitaxial layer, and the junction depth in the body area is less than the fourth epitaxial layer
Junction depth.
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| JP2008205497A (en) * | 1994-12-30 | 2008-09-04 | Siliconix Inc | Low on-state resistance trench type mosfet with delta layer |
| JP2006294968A (en) * | 2005-04-13 | 2006-10-26 | Shindengen Electric Mfg Co Ltd | Semiconductor device and its manufacturing method |
| CN202434527U (en) * | 2011-02-15 | 2012-09-12 | 台湾半导体股份有限公司 | Super junction metal oxide semiconductor field effect transistor structure |
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