CN210837711U - Metal oxide semiconductor field effect transistor with deep and shallow grooves - Google Patents
Metal oxide semiconductor field effect transistor with deep and shallow grooves Download PDFInfo
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- CN210837711U CN210837711U CN201921015706.XU CN201921015706U CN210837711U CN 210837711 U CN210837711 U CN 210837711U CN 201921015706 U CN201921015706 U CN 201921015706U CN 210837711 U CN210837711 U CN 210837711U
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Abstract
The utility model discloses a metal oxide semiconductor field effect transistor of depth slot and preparation method thereof, the metal oxide semiconductor field effect transistor of depth slot includes vertically crossing deep groove and shallow slot, and deep groove and shallow slot lateral wall and bottom all grow there is the one deck oxide layer, and inside packing has polycrystalline silicon. The utility model provides a three-dimensional structure realizes high breakdown voltage, the characteristic of low opening voltage. The method comprises the depth grooves which are vertically crossed, a photoetching plate does not need to be added in the whole groove preparation process, and the complicated structure in the groove is not required to be realized through multiple times of deposition and etching, so that the preparation process is simpler, and the process is easier to control.
Description
Technical Field
The utility model relates to a semiconductor field, more exactly is a metal oxide semiconductor field effect transistor of depth slot.
Background
The prior art generally divides the structure into two structures in order to achieve low turn-on voltage and high breakdown voltage. One is a groove structure of the thin gate oxide on the upper half part of the thick gate oxide at the bottom, and the other is a split gate structure. The internal shapes of the grooves of the two structures are relatively complex, the preparation process is complicated and is not easy to control, and the preparation efficiency of the device is reduced.
SUMMERY OF THE UTILITY MODEL
It is an object of the present invention to provide a mosfet with deep and shallow trenches, which can solve the above-mentioned disadvantages in the prior art.
The utility model adopts the following technical scheme:
a method for preparing a metal oxide semiconductor field effect transistor with a deep and shallow groove comprises the following steps:
the epitaxial wafer consists of a substrate with low resistivity and an epitaxial layer with specific resistivity;
growing a masking layer on the epitaxial layer;
carrying out groove photoetching, etching the masking layer and etching a groove etching window;
removing the photoresist, performing deep trench etching, and forming a deeper trench under the masking action of the masking layer, wherein the depth of the deep trench is far deeper than that of the trench region;
removing the masking layer, performing sacrificial oxidation, and removing the oxide layer; growing a thicker oxide layer, depositing an insulating medium layer, and filling the groove and the silicon surface;
depositing a layer of photoresist, and etching a shallow trench etching window in the direction vertical to the deep trench;
removing the photoresist, and etching a shallow trench;
growing a thin oxide layer at the bottom and on the side wall of the shallow trench;
removing the dielectric layer, and etching the dielectric layer deposited on the surface and inside the deep trench;
depositing heavily doped polysilicon to fill the inside of the deep shallow trench;
and etching the redundant polysilicon to enable the surface of the polysilicon to be level with the surface of the source region, namely etching the polysilicon on the surface of the source region, but reserving the polysilicon in the groove to form the gate of the MOSFET.
Further comprising the steps of:
depositing an oxide layer on the surface, and etching, wherein the reserved thickness of the oxide layer surface is 100-300A;
carrying out photoetching and injection on a channel injection region, removing photoresist, injecting P-type impurity ions in an ion injection mode, and heating and annealing to form expected channel region impurity distribution;
and carrying out source region photoetching and injection, and removing the photoresist. And implanting high-concentration N-type impurity ions in an ion implantation mode, annealing, activating impurities and forming a source electrode.
Further comprising the steps of:
depositing a dielectric layer, wherein the material is phosphorosilicate glass generally;
depositing photoresist and carrying out contact hole photoetching;
removing the photoresist, etching and injecting a contact hole, and annealing;
and depositing metal and etching the surface redundant metal.
Further comprising the steps of:
and thinning the back of the chip, and plating a metal layer in a chemical plating mode to form a device drain electrode.
Further comprising the steps of: the metal layer is any one of TiNiAg, AgSn or Au.
The composition of the masking layer material may be silicon oxide, silicon nitride, or a combination of both.
The dielectric layer is typically SiN.
A metal oxide semiconductor field effect transistor with a deep and shallow groove is prepared by the method.
The gate oxide layer is grown on the side wall and the bottom of each of the deep groove and the shallow groove, the polycrystalline silicon is filled in the gate oxide layers, and the thickness of the first gate oxide layer in the deep groove is thicker than that of the second gate oxide layer in the shallow groove.
The deep groove and the shallow groove are arranged in an epitaxial wafer, the epitaxial wafer is composed of a substrate with low resistivity and an epitaxial layer with specific resistivity, and the resistivity of the epitaxial layer is selected according to actual needs.
The thickness of the gate oxide layer in the deep groove is thicker than that in the shallow groove.
An oxide layer is deposited on the epitaxial layer between the deep trench and the shallow trench, and a channel region injection layer and a source region injection layer are arranged inside the epitaxial layer.
A dielectric layer is deposited on the oxide layer.
A contact hole is further formed between the deep groove and the shallow groove, a contact hole injection layer is arranged at the bottom of the contact hole, and the contact hole injection layer is arranged inside the channel region injection layer.
And metal layers are deposited on the outer side of the dielectric layer and inside the contact hole.
The back of the substrate is provided with a metal coating to form a drain electrode.
The utility model has the advantages that: the utility model provides a three-dimensional structure to realize the characteristics of high breakdown voltage and low opening voltage; the method comprises the depth grooves which are vertically crossed, a photoetching plate does not need to be added in the whole groove preparation process, and the complicated structure in the groove is not required to be realized through multiple times of deposition and etching, so that the preparation process is simpler, and the process is easier to control.
Drawings
The invention is explained in more detail below with reference to exemplary embodiments and the accompanying drawings, in which:
fig. 1 to 34 are schematic flow charts of the preparation method of the present invention.
Fig. 35 is a schematic structural diagram of the present invention.
Fig. 36 is a top view of a single cell of the present invention.
Fig. 37 is a schematic diagram showing the distribution of the depletion layer in the X direction when a reverse voltage is applied.
Detailed Description
The following further illustrates embodiments of the present invention:
as shown in fig. 1 to 34, the utility model discloses a twice slot sculpture forms violently indulges crossing deep groove and shallow trench on whole disk, and thick bars oxygen and thin bars oxygen grow respectively in the ditch groove, and the shallow trench of thin bars oxygen has guaranteed lower opening voltage, and the deep groove of thick bars oxygen provides higher breakdown voltage.
The utility model provides a shallow trench degree of depth is 0.5 ~ 2um usually, and deep trench thickness is 2 ~ 10um usually, according to actual product parameter decision.
The deep groove and the shallow groove are different in etching depth and gate oxide layer thickness, and the etching width and the distance of the grooves are kept the same.
Defining the etching direction of the deep groove as x direction, defining the direction of the shallow groove as y direction, and enabling the x direction to be vertical to the y direction.
The specific preparation process steps of the whole cells of the utility model are as follows: (x direction/y direction represents the direction of the sectional view):
selecting a proper epitaxial wafer according to the characteristic requirements of the MOSFET, wherein the wafer consists of a substrate 1 with low resistivity and an epitaxial layer 2 with specific resistivity, and is shown in figure 1;
growing a masking layer 3 on the epitaxial layer 2, wherein the masking layer 3 is used for masking the subsequent trench etching, the component of the masking layer material can be silicon oxide, silicon nitride or a combination of the silicon oxide and the silicon nitride, and a photoresist 4 is deposited on the outer side of the masking layer, as shown in fig. 2-3, and is in the x direction);
performing trench lithography, etching the masking layer to form a trench etching window 5, as shown in fig. 4, in the x direction;
removing the photoresist, etching the deep trench 6, and forming a deeper trench under the masking action of the masking layer, wherein the depth of the deep trench is far deeper than that of the trench region, as shown in fig. 5, in the x direction;
and removing the masking layer, performing sacrificial oxidation, and removing the oxide layer. The sacrificial oxide layer generally grows to about 500A, and mainly functions to remove impurities on the surface, as shown in fig. 6, in the x direction;
growing a thicker oxide layer 7, generally dry-method growth, and growing a first gate oxide layer on the side wall, the bottom and the wafer surface of the trench, as shown in fig. 7, wherein the thickness of the first gate oxide layer is generally 1000A-6000A in the x direction, and the specific thickness is determined according to actual product parameters;
depositing an insulating dielectric layer 8 to fill the trench and the silicon surface, wherein the dielectric layer may be made of SiN, as shown in fig. 8, in the x direction;
depositing a layer of photoresist 9, and etching a shallow trench etching window in the direction vertical to the deep trench. As shown in fig. 9, the x direction, as shown in fig. 10, and the y direction, fig. 9 is a cross-sectional view of the deep trench structure, and fig. 10 is a cross-sectional view of the structure in the shallow trench direction perpendicular to the deep trench.
Removing the photoresist and etching the shallow trench 10 in the y direction as shown in fig. 11;
growing a layer of thinner second gate oxide layer 11 on the bottom and the side wall of the shallow trench, as shown in fig. 12, wherein the thickness of the second gate oxide layer in the y direction is 200-400A, and the specific thickness is determined according to actual product parameters;
removing the dielectric layer, and etching away the dielectric layer deposited on the surface and inside the deep trench, as shown in fig. 13, in the y direction, and in the x direction of fig. 14;
depositing heavily doped polysilicon 12 to fill the inside of the deep shallow trench, as shown in fig. 15, y direction, fig. 16, x direction;
etching off the redundant polysilicon to make the surface of the polysilicon level with the surface of the source region, i.e. the polysilicon on the surface of the source region is etched off, but the polysilicon in the trench remains to form the gate of the MOSFET, as shown in fig. 17, in the y direction, as shown in fig. 18, in the x direction;
depositing an oxide layer 13 on the surface, and etching, wherein the reserved thickness of the oxide layer surface is about 100-300A, as shown in a y direction in fig. 19, and as shown in an x direction in fig. 20);
and photoetching and implanting the channel implantation region 14, and removing the photoresist. Implanting P-type impurity ions by ion implantation, and performing thermal annealing to form a desired channel region impurity profile in the y direction as shown in FIG. 21 and in the x direction as shown in FIG. 22;
and carrying out source region photoetching and injection, and removing the photoresist to form a source region injection layer 15. High concentration N-type impurity ions are implanted by ion implantation, and annealing is performed to activate the impurity and form a source in the y direction as shown in fig. 23 and in the x direction as shown in fig. 24.
Depositing a dielectric layer 16, typically a phosphosilicate glass material, in the y-direction as shown in FIG. 25 and in the x-direction as shown in FIG. 26;
photoresist is deposited and contact hole 18 photolithography is performed, in the y direction as shown in fig. 27, in the x direction as shown in fig. 28,
the photoresist is removed, contact hole etching and implantation are performed to form a contact hole implantation layer 19, and annealing is performed, as shown in the y direction of fig. 29 and the x direction of fig. 30.
Depositing metal 20 and etching the surface redundant metal, wherein the metal material is tungsten, and the y direction is shown in figure 31, and the x direction is shown in figure 32;
the back metal plating layer 21 is formed by thinning the back of the chip according to actual requirements, plating a metal layer, which is generally TiNiAg or AgSn or Au, with a thickness of several micrometers, by means of electroless plating, and forming a device drain, as shown in the y direction in fig. 33 and as shown in the x direction in fig. 34.
The entire cell region fabrication process is as described above, and does not involve the fabrication of the termination region, but is compatible with conventional MOS termination fabrication processes. The relevant parameters of deposition, injection, etching and annealing are conventional process flows, and can be adjusted according to actual specific parameter requirements.
As shown in fig. 35 and 36, the metal oxide semiconductor field effect transistor with the deep and shallow trenches is prepared by the above method, and includes the deep trench 6 and the shallow trench 10 which are vertically intersected, a layer of gate oxide layer is grown on the side walls and the bottoms of the deep trench 6 and the shallow trench 10, the gate oxide layer is filled with polysilicon 12, and the thickness of the first gate oxide layer 7 in the deep trench is thicker than that of the second gate oxide layer 11 in the shallow trench. The deep groove 6 and the shallow groove 10 are both arranged in an epitaxial wafer, the epitaxial wafer is composed of a substrate 1 with low resistivity and an epitaxial layer 2 with specific resistivity, and the deep groove and the shallow groove are arranged in the epitaxial layer.
An oxide layer 13 is deposited on the epitaxial layer between the deep trench and the shallow trench, and a channel region injection layer 14 and a source region injection layer 15 are arranged inside the epitaxial layer. A dielectric layer 16 is deposited over the oxide layer 13. A contact hole 18 is further arranged between the deep trench and the shallow trench, a contact hole injection layer 19 is arranged at the bottom of the contact hole 18, and the contact hole injection layer 19 is arranged inside the channel region injection layer. A metal layer is deposited on the outside of dielectric layer 16 and inside contact hole 18. The back side of the substrate is provided with a metal plating layer 21 to form a drain electrode.
The utility model discloses a metal oxide semiconductor field effect transistor of dark shallow slot passes through the perpendicular crossing of deep groove and shallow groove, and shallow groove bottom and lateral wall grow and have the gate oxide layer of relatively thinner, and deep groove bottom and lateral wall grow the gate oxide layer of relatively thicker. When forward voltage is applied, the device is easier to open due to the thinner gate oxide of the shallow trench, and lower opening voltage is provided; when a reverse voltage is applied, the adjacent deep trench and the thicker gate oxide deplete carriers in the lower region of the shallow trench and ensure a higher breakdown voltage.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (6)
1. The metal oxide semiconductor field effect transistor with the deep and shallow grooves is characterized by comprising a deep groove and a shallow groove which are vertically intersected, wherein a layer of gate oxide layer grows on the side wall and the bottom of the deep groove and the bottom of the shallow groove, polycrystalline silicon is filled in the gate oxide layers, and the thickness of the first gate oxide layer in the deep groove is thicker than that of the second gate oxide layer in the shallow groove.
2. The deep trench mosfet of claim 1 wherein an oxide layer is deposited on the epitaxial layer between the deep trench and the shallow trench, and a channel region implant layer and a source region implant layer are formed inside the epitaxial layer.
3. The deep trench mosfet of claim 2 further comprising a dielectric layer deposited on the oxide layer.
4. The MOSFET of claim 3, wherein a contact hole is further formed between the deep trench and the shallow trench, a contact hole injection layer is formed at the bottom of the contact hole, and the contact hole injection layer is formed inside the channel region injection layer.
5. The MOSFET of claim 4, wherein a metal layer is deposited on the outside of the dielectric layer and inside the contact hole.
6. The MOSFET of claim 5, wherein the drain is formed by a metallization layer on the back side of the substrate.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921015706.XU CN210837711U (en) | 2019-07-02 | 2019-07-02 | Metal oxide semiconductor field effect transistor with deep and shallow grooves |
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| CN201921015706.XU CN210837711U (en) | 2019-07-02 | 2019-07-02 | Metal oxide semiconductor field effect transistor with deep and shallow grooves |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110223959A (en) * | 2019-07-02 | 2019-09-10 | 上海格瑞宝电子有限公司 | The Metal Oxide Semiconductor Field Effect Transistor and preparation method thereof of depth groove |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110223959A (en) * | 2019-07-02 | 2019-09-10 | 上海格瑞宝电子有限公司 | The Metal Oxide Semiconductor Field Effect Transistor and preparation method thereof of depth groove |
| CN110223959B (en) * | 2019-07-02 | 2024-01-23 | 上海格瑞宝电子有限公司 | Metal oxide semiconductor field effect transistor with deep and shallow grooves and preparation method thereof |
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