CN210200737U

CN210200737U - Trench MOSFET structure with polycrystalline silicon as source region

Info

Publication number: CN210200737U
Application number: CN201921016229.9U
Authority: CN
Inventors: Meng Dai; 代萌; Chengjie Li; 李承杰; Jiaqing Gu; 顾嘉庆
Original assignee: Shanghai Greenpower Electronic Co Ltd
Current assignee: Shanghai Greenpower Electronic Co Ltd
Priority date: 2019-07-02
Filing date: 2019-07-02
Publication date: 2020-03-27
Anticipated expiration: 2029-07-02

Abstract

The utility model discloses a ditch groove MOSFET structure and preparation method thereof as source region of polycrystalline silicon, MOSFET structure, including substrate and epitaxial layer, and the deposit has the heavy doping polycrystalline silicon layer to form the source region on the epitaxial layer, is equipped with the slot in the epitaxial layer, and the deposit has gate oxide layer on the inside and the lateral wall of slot, and the thickness of the gate oxide layer of the inside gate oxide layer of epitaxial layer is less than the thickness of the gate oxide layer in the source region. The utility model has the advantages that: compared with the traditional MOSFET, the whole process flow of the MOSFET is simpler, the width of a source region formed by depositing polycrystalline silicon is easier to control, the reliability of the source region is enhanced, and the length of a channel is not influenced.

Description

Trench MOSFET structure with polycrystalline silicon as source region

Technical Field

The utility model relates to the field of semiconductors, in particular to a trench MOSFET structure with polycrystalline silicon as a source region and a preparation method thereof.

Background

The trench MOSFET is a new generation power MOSFET developed in recent years, and takes an N-type trench MOSFET cell as an example, and the process flow is as follows. Firstly, a groove is etched on the surface of the N-epitaxial layer, a gate oxide layer grows in the groove, and N-type heavily doped polysilicon is deposited and filled to form a gate. Then injecting boron ions into the surface of the epitaxial layer, heating and diffusing to form a P-channel region, and then injecting phosphorus ions with low energy to form an N + source region. And etching a contact hole on the surface of the epitaxial layer, filling metal, connecting the channel region and the source region, and taking the back N + substrate as a drain region. Compared with the traditional MOSFET, the MOSFET has the advantages of high switching speed, low on resistance, high voltage resistance, large current, good thermal stability and the like, and is widely applied. The cell structure is shown in fig. 16.

The process for forming the trench MOSFET source region generally comprises the steps of implanting low-energy heavily-doped impurities into the surface of an epitaxial layer through ion implantation after channel implantation, and then forming the trench MOSFET source region through thermal diffusion. The width of the source region formed in this way is affected by the energy and dose of ion implantation in the source region and the channel region, and is not easy to control, and the performance of the MOSFET device is affected by the too narrow source region or the too short channel.

In view of the above, the utility model provides an application deposit at the structure of the heavily doped polycrystalline silicon of epitaxial layer surface as source region to the process flow of preparing this structure has been expounded, compares with traditional slot MOSFET process flow, and new construction preparation flow is more simple and easy, and does not influence MOSFET basic electrical parameter, and the regional size of better control source has saved source region ion implantation and diffusion technology, the reliability of the source region that has strengthened.

SUMMERY OF THE UTILITY MODEL

It is an object of the present invention to provide a method for manufacturing a trench MOSFET structure using polysilicon as a source region, which can solve the above-mentioned disadvantages of the prior art.

The utility model adopts the following technical scheme:

a preparation method of a trench MOSFET structure with polysilicon as a source region comprises the following steps:

manufacturing an epitaxial wafer, wherein the epitaxial wafer consists of an N-type substrate with low resistivity and an N-type epitaxial layer with specific resistivity;

injecting P-type impurities into the surface of the epitaxial layer, wherein the injection energy is 100-200 keV, and annealing to form a channel region;

depositing a layer of heavily doped polysilicon with the thickness of 2-4 microns on the surface of the epitaxial layer, and annealing to form a source region;

growing a layer of masking layer on the surface of the polycrystalline silicon;

depositing a layer of photoresist on the masking layer, carrying out groove photoetching, etching the masking layer at the position of the groove to be etched to form an etching window;

removing the redundant photoresist on the surface, and etching the groove under the action of the masking layer;

growing a layer of oxide layer to be sacrificed and then removing the oxide layer; thermally growing a 100-800A sacrificial oxide layer on the surface of the epitaxial layer and the surface of the epitaxial layer, and then etching and removing the sacrificial oxide layer;

after removing the sacrificial oxide layer, growing a thin oxide layer on the surface of the groove and the surface of the polycrystalline silicon to form gate oxide, wherein the thickness of the oxide layer is 200-1000A, and the oxide layer can be selected according to actual parameter requirements of products;

depositing N-type heavily doped polysilicon to fill the trench and reduce the resistivity;

etching off redundant polysilicon to ensure that the surface of the polysilicon in the groove is level to the polysilicon in the source region and ensure that a device channel can be formed, and depositing a dielectric layer on the surface;

carrying out contact hole opening photoetching;

removing the redundant photoresist, and etching the contact hole;

injecting a contact hole;

filling the contact hole metal, depositing a layer of contact hole metal and etching the surface redundant metal.

A trench MOSFET structure with polysilicon as a source region is prepared by the method.

The silicon-based MOS transistor comprises a substrate and an epitaxial layer, wherein a heavily doped polycrystalline silicon layer is deposited on the epitaxial layer to form a source region, a groove is arranged in the epitaxial layer, a gate oxide layer is deposited inside the groove and on the side wall of the groove, and the thickness of the gate oxide layer inside the epitaxial layer is smaller than that of the gate oxide layer in the source region.

The contact hole trench is arranged between the trenches, a contact hole injection region is arranged at the bottom of the contact hole trench, and the contact hole injection region is positioned in the channel region.

The contact hole injection region is a P-type doping injection.

And a dielectric layer is padded on the heavily doped polysilicon layer of the source region.

And metal layers are padded in the contact hole groove and on the dielectric layer.

The back of the substrate is provided with a metal coating to form a drain electrode.

The utility model has the advantages that: compared with the traditional MOSFET, the whole MOSFET is simpler, the width of a source region formed by depositing polycrystalline silicon is easier to control, and the length of a channel cannot be influenced.

Drawings

The invention is explained in more detail below with reference to exemplary embodiments and the accompanying drawings, in which:

fig. 1 to 14 are schematic flow charts of the preparation method of the present invention.

Fig. 15A is a schematic diagram of an analog simulation verification result in the prior art of the present invention.

Fig. 15B is a schematic diagram of the simulation verification result of the structure of the present invention.

Fig. 16 is a schematic diagram of a prior art structure of the present invention.

Detailed Description

The following further illustrates embodiments of the present invention:

make the channel region and compare with the earlier sculpture slot of traditional MOSFET preparation technology earlier after, the utility model discloses put the slot sculpture after channel region and source area sculpture. After the channel region is implanted and annealed, heavily doped polysilicon is deposited on the silicon surface to form a source region, and the source region formed by ion implantation of the traditional trench MOSFET is replaced. And then etching the groove, growing gate oxide, filling polycrystalline silicon, and ensuring that the height of the gate polycrystalline silicon is at least consistent with that of the source polycrystalline silicon to form a complete channel.

The preparation method of the utility model is as follows:

selecting a proper epitaxial wafer according to the characteristic requirements of the MOSFET, wherein the wafer consists of an N-type substrate 1 with low resistivity and an N-type epitaxial layer 2 with specific resistivity, and is shown in figure 1;

p-type impurities are implanted into the surface of the epitaxial layer 2, and annealing is performed to form a channel region 3. The general implantation energy is 100-200 keV, and the specific ion implantation dosage and energy are controlled according to the actual trench depth or the required starting voltage range, as shown in FIG. 2;

depositing a layer of heavily doped polysilicon on the surface of the epitaxial layer 2, wherein the thickness is about 2-4 um, and annealing to form a source region 4, as shown in fig. 3;

growing a layer of masking layer 5 on the surface of the polysilicon, wherein the role of the masking layer 5 is to provide masking for the subsequent trench etching, and the composition of the masking layer material can be silicon oxide, silicon nitride or a combination of the two, as shown in fig. 4;

depositing a layer of photoresist 6 on the masking layer, performing trench lithography, etching away the masking layer at the trench to be etched to form an etching window, wherein the size of the etching window is determined according to the characteristic requirements of the MOSFET, as shown in FIG. 5;

removing the redundant photoresist 6 on the surface, and etching the groove 7 under the action of the masking layer, wherein dry etching is generally adopted for etching, as shown in fig. 6;

before the oxide layer is grown, a very thin sacrificial oxide layer is generally grown and then removed, so that impurities and surface states on the silicon surface are removed, the appearance of a groove is improved, a higher-quality gate oxide layer can be grown, and a flow chart is not particularly independently described; namely, a sacrificial oxide layer of about 500A is thermally grown on the surface of the epitaxial layer and the surface of the epitaxial layer, and then is removed by etching. After removing the sacrificial oxide layer, growing a thin oxide layer on the surface of the groove and the surface of the polycrystalline silicon to form a gate oxide 8, wherein the thickness of the oxide layer is 200-1000A, and the oxide layer can be selected according to actual parameter requirements of products. At this time, because of the concentration difference between the source polysilicon on the surface of the trench and the epitaxial layer silicon, the oxide layer on the surface of the polysilicon in actual growth is slightly thicker than the oxide layer grown on the surface of the silicon, as shown in fig. 7;

depositing N-type heavily doped polysilicon 9, filling the trench to reduce the resistivity, as shown in FIG. 8;

and etching off redundant polysilicon to ensure that the surface of the polysilicon in the groove is level to the polysilicon in the source region, ensure the formation of a device channel, and depositing a dielectric layer 10 on the surface. The polysilicon is etched in this step, typically by chemical mechanical planarization. The deposited dielectric layer 10 may be silicon oxide or silicon nitride, etc. in order to provide a mask for the subsequent contact hole etching, as shown in fig. 9;

and carrying out contact hole opening photoetching. Depositing a layer of photoresist 11 on the surface of the dielectric layer, and etching away the dielectric layer at the position of the contact hole and the oxide layer on the surface of the source region polysilicon as shown in fig. 10;

removing the redundant photoresist, etching the contact hole 12, which is also generally dry etching, with the depth of the contact hole ensuring the contact channel region, as shown in fig. 11;

the contact hole 13 is implanted, typically with an impurity of boron difluoride (BF)₂) Or Boron ions (Boron), as shown in fig. 12;

contact hole metal filling, depositing a layer of contact hole metal and etching the surface excess metal 14, typically tungsten, as shown in fig. 13.

The back metal plating layer 15 is formed by thinning the back of the chip according to actual requirements, plating a metal layer in an electroless plating mode, wherein the metal layer is generally TiNiAg or AgSn or Au, the thickness is generally several micrometers, and a device drain electrode is formed, as shown in FIG. 14.

A trench MOSFET structure with polysilicon as a source region is prepared by the method. The silicon-based epitaxial wafer comprises a substrate 1 and an epitaxial layer 2, a heavily-doped polycrystalline silicon layer is deposited on the epitaxial layer 2 to form a source region 3, a groove 7 is arranged in the epitaxial layer, a gate oxide layer 8 is deposited inside the groove and on the side wall of the groove, and the thickness of the gate oxide layer inside the epitaxial layer is smaller than that of the gate oxide layer in the source region.

The utility model discloses still include contact hole slot 12, it is located between the slot, and contact hole slot's bottom is equipped with contact hole injection zone 13, and contact hole injection zone is in channel region 3. The contact hole injection region is a P-type doping injection. A dielectric layer 10 is padded on the heavily doped polysilicon layer of the source region. And a metal layer 14 is filled in the contact hole groove and on the dielectric layer.

The utility model adopts the MOSFET cellular structure with the polycrystalline silicon as the source electrode; as shown in fig. 15, the structural and process feasibility was verified by simulation. Simulation results show that the existing structure is shown in fig. 15A, compared with the structure of the present invention, as shown in fig. 15B, the new structure has improved channel length while ensuring the width of the source region. The concentration of the deposited doped polysilicon can be selected to be proper according to actual requirements. After the thermal process, the impurities in the polysilicon can diffuse like the inside of the epitaxial layer, i.e., the epitaxial layer near the surface can also form a source region due to diffusion. As shown in fig. 15B, according to the simulation results, when the threshold voltage of the new structure is adjusted to be the same as that of the conventional structure, the leakage current (IR) of the new structure is smaller, and the increase of the leakage current (IR) with the reverse voltage is more gradual.

The utility model discloses a preparation method is that the slot is refabricated after preparing channel region and source region earlier. It is also feasible to fabricate the trench first and then the channel and source regions in the general trench MOSFET fabrication sequence. However, the trench polysilicon is leveled with the surface source region polysilicon, and the trench breaking is not occurred, so that the whole process is difficult to realize and relatively complex, unlike the method of the present invention which is simple and practical. Compared with the traditional MOSFET, the method of the utility model is simpler, the width of the source region formed by depositing polycrystalline silicon is easier to control, and the length of the channel is not influenced.

The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims

1. The utility model provides a ditch groove MOSFET structure of polycrystalline silicon as source region which characterized in that, includes substrate and epitaxial layer, and the epitaxial layer is gone up the deposit and is had heavily doped polycrystalline silicon layer to form the source region, is equipped with the slot in the epitaxial layer, has deposited gate oxide layer inside the slot and on the lateral wall, and the thickness of the gate oxide layer of epitaxial layer inside is less than the thickness of the gate oxide layer in the source region.

2. The trench MOSFET structure having a source region of polysilicon as claimed in claim 1 further comprising a contact hole trench disposed between the trenches and having a contact hole implant region disposed at the bottom of the contact hole trench and within the channel region.

3. The trench MOSFET structure with polysilicon as source region of claim 2 wherein the contact hole implant region is a P-type dopant implant.

4. The trench MOSFET structure with polysilicon as the source region of claim 3, wherein the heavily doped polysilicon layer of the source region is lined with a dielectric layer.

5. The trench MOSFET structure with polysilicon as the source region as claimed in claim 4, wherein the contact hole trench is filled with a metal layer and a dielectric layer.

6. A trench MOSFET structure with polysilicon as source region according to claim 5, wherein the back surface of the substrate is provided with a metal plating layer to form the drain electrode.