CN109427684B - 鳍式场效应晶体管器件和方法 - Google Patents
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- CN109427684B CN109427684B CN201810042939.2A CN201810042939A CN109427684B CN 109427684 B CN109427684 B CN 109427684B CN 201810042939 A CN201810042939 A CN 201810042939A CN 109427684 B CN109427684 B CN 109427684B
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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Abstract
方法包括在衬底的第一区域中的第一鳍上方形成半导体覆盖层,在半导体覆盖层上方形成介电层,以及在介电层上方形成绝缘材料,该绝缘材料的上表面比第一鳍的上表面更远离衬底延伸。该方法还包括使绝缘材料凹进以暴露第一鳍的顶部;以及在第一鳍的顶部上方形成栅极结构。本发明的实施例还涉及鳍式场效应晶体管器件和方法。
Description
技术领域
本发明的实施例涉及鳍式场效应晶体管器件和方法。
背景技术
由于各个电组件(例如,晶体管、二极管、电阻器、电容器等)的集成密度的持续改进,半导体工业已经经历了快速增长。对于大部分而言,这种集成密度的改进来自于最小部件尺寸的连续减小,这使得更多的组件集成到给定的区域。
鳍式场效应晶体管(FinFET)器件在集成电路中越来越普遍。FinFET器件具有包括从衬底突出的半导体鳍的三维结构。配置为控制FinFET器件的导电沟道内的电荷载流子的流动的栅极结构包裹半导体鳍。例如,在三栅极FinFET器件中,栅极结构包裹半导体鳍的三个侧面,从而在半导体鳍的三个侧面上形成导电沟道。
发明内容
本发明的实施例提供了一种形成鳍式场效应晶体管器件的方法,包括:在衬底的第一区域中的第一鳍上方形成半导体覆盖层;在所述半导体覆盖层上方形成介电层;在所述介电层上方形成绝缘材料,所述绝缘材料的上表面比所述第一鳍的上表面更远离所述衬底延伸;使所述绝缘材料凹进以暴露所述第一鳍的顶部;以及在所述第一鳍的顶部上方形成栅极结构。
本发明的另一实施例提供了一种形成鳍式场效应晶体管(FinFET)器件的方法,所述方法包括:在衬底的PMOS区域中形成第一鳍;在所述衬底的邻近于所述PMOS区域的NMOS区域中形成第二鳍;在所述第一鳍和所述第二鳍上方形成硅覆盖层;对所述硅覆盖层实施氮化处理;在所述硅覆盖层上方形成第一介电材料;在所述第一鳍和所述第二鳍之间以及所述第一鳍和所述第二鳍上方沉积第二介电材料,其中,所述第一介电材料位于所述硅覆盖层和所述第二介电材料之间;实施热工艺以固化所述第二介电材料;在所述热工艺之后,使所述第二介电材料凹进以暴露所述第一鳍的顶部和所述第二鳍的顶部;以及在所述第一鳍上方形成第一栅极结构并且在所述第二鳍上方形成第二栅极结构。
本发明的又一实施例提供了一种鳍式场效应晶体管(FinFET)器件,包括:鳍,突出在隔离区域的上表面之上,所述隔离区域位于所述鳍的相对侧上;硅覆盖层,位于所述鳍和所述隔离区域之间;第一介电材料,位于所述硅覆盖层和所述隔离区域之间;以及第二介电材料,位于所述第一介电材料和所述隔离区域之间并且与所述第一介电材料不同,所述第二介电材料包括所述第一介电材料的氧化物。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该指出,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1示出了根据一些实施例的鳍式场效应晶体管(FinFET)的立体图。
图2至图13、图14A、图14B、图14C、图15至图20、图21A和图21B示出了根据一些实施例的处于各个制造阶段的FinFET器件的截面图。
图22示出了根据一些实施例的用于形成半导体器件的方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。
本发明的实施例在形成FinFET器件的上下文中讨论,并且具体地,在在半导体鳍上方形成衬垫层以防止或减少热退火工艺期间的半导体鳍的氧化的上下文中。然而,本领域技术人员将容易理解,本发明中公开的方法可以用于其它器件或应用,例如平面器件。
图1示出了FinFET 30的实例的立体图。FinFET 30包括具有鳍64的衬底50。鳍64突出在设置在鳍64的相对侧上的相邻的隔离区域62之上。栅极电介质66沿着鳍64的侧壁并且位于鳍64的顶面上方,栅电极68位于栅极电介质66上方。源极/漏极区域80位于栅极电介质66和栅极电极68的相对侧上的鳍中。图1进一步示出了在随后的附图中使用的参照截面。截面B-B沿着FinFET 30的栅电极68的纵轴延伸。截面A-A垂直于截面B-B,并且沿着鳍64的纵轴延伸并且在例如在源极/漏极区域80之间的电流的方向上。截面C-C与截面B-B平行并且横跨源极/漏极区域80。为了清楚起见,随后的附图涉及这些参照截面。
图2至图13、图14A、图14B、图14C、图15至图20、图21A和图21B是根据一些实施例的处于各个制造阶段的FinFET器件100的截面图。除了多个鳍之外,FinFET器件100与图1中的FinFET 30类似。图2至图12示出了沿着截面B-B的FinFET器件100的截面图,图13和图14A示出了沿着截面A-A的FinFET器件100的截面图,图14B和图14C示出了沿着截面C-C的FinFET器件100的截面图,图15至图20和图21A示出了沿着截面A-A的FinFET器件100的截面图,并且图21B示出了沿着截面B-B的FinFET器件100的截面图。
图2示出了衬底50的截面图。衬底50可以是掺杂的(例如,掺杂有p型或n型掺杂剂)或未掺杂的半导体衬底,诸如块状半导体、绝缘体上半导体(SOI)衬底等。衬底50可以是晶圆,诸如硅晶圆。通常,SOI衬底包括形成在绝缘层上的半导体材料层。绝缘层可以是例如埋氧(BOX)层、氧化硅层等。在通常为硅或玻璃衬底的衬底上提供绝缘层。也可以使用诸如多层的或梯度衬底的其它衬底。在一些实施例中,衬底50的半导体材料可以包括硅;锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或它们的组合。
如图2示出的,衬底包括区域200中的第一部分和区域300中的第二部分。衬底50的区域200中的第一部分可以用于形成P型器件,诸如P型金属氧化物半导体场效应晶体管(MOSFET),并且衬底50的区域300中的第二部分可以用于形成N型器件,诸如N型MOSFET。因此,区域200可以称为PMOS区域,并且区域300可以称为NMOS区域。在一些实施例中,在区域200和区域300中形成P型器件(或N型器件)。
下一步,参照图3,用半导体材料50A替换衬底50的区域200中的部分,半导体材料50A诸如适用于形成区域200中的对应类型的器件(例如,P型器件)的外延半导体材料。例如,半导体材料50A可以是或者包括外延生长的硅锗。为了形成半导体材料50A,使用化学汽相沉积(CVD)、物理汽相沉积(PVD)、旋涂或其它合适的沉积方法在衬底50上方形成掩模层53(其可以是诸如光刻胶的感光层)。之后,使用例如光刻和图案化技术来图案化掩模层53。如图3示出的,图案化的掩模层53覆盖区域300,但暴露区域200。之后,通过诸如反应离子蚀刻(RIE)、中性束蚀刻(NBE)等或它们的组合的合适的蚀刻工艺去除衬底500的区域200中的暴露部分,以在区域200中形成凹槽(未示出)。
下一步,实施外延以在区域200中的凹槽中生长半导体材料50A。可以在生长期间原位掺杂外延生长的半导体材料50A,这可以避免对之前和之后的注入的需要,尽管原位和注入掺杂可以一起使用。在外延之后,掩模层53可以通过诸如蚀刻或等离子体灰化的合适的去除工艺去除。之后可实施诸如化学机械抛光(CMP)的平坦化工艺以使半导体材料50A的顶面与衬底50的顶面齐平。图3也示出了半导体材料50A和衬底50之间的界面63,其可以是或可以不是如图3所示的直线。
可选地,可以形成另一个图案化的掩模层(未示出)以覆盖区域200,同时暴露区域300,并且可以去除衬底50的区域300中的暴露部分并且用外延生长的半导体材料50B(图3中以虚线示出)替换。半导体材料50B可以是或者包括适用于形成区域300中的对应类型的器件(例如,N型器件)的外延半导体材料。例如,半导体材料50B可以是或包括外延生长的碳化硅。
在一些实施例中,将形成的FinFET器件100是逻辑器件,PMOS区域(例如,区域200)具有由半导体材料50A(例如,硅锗)替换的顶部,并且NMOS区域(例如,区域300)不具有由半导体材料50B替换的顶部,因此,NMOS区域(例如,区域300)具有与衬底50相同的材料(例如,硅)。在另一实施例中,将形成的FinFET器件100是高功率器件,在这种情况下,PMOS区域(例如,区域200)和NMOS区域(例如,区域300)均具有它们由相同的半导体材料碳化硅(例如,50A和50B为碳化硅)替换的顶部。
在其它实施例中,半导体材料50B(例如,外延半导体材料)替换衬底50的区域300中的部分,并且衬底50的区域200中的部分可以可选地由半导体材料50A(例如,外延半导体材料)替换。在又其它实施例中,没有形成上述外延半导体材料(例如,50A和50B),因此可以省略图3中示出的工艺。下面的讨论使用衬底50的示例配置,其中,在第一区域200中形成半导体材料50A并且没有在区域300中形成半导体材料50B,应该理解,图4至图21B中示出的工艺也可以应用于上述其它衬底配置。在下文的讨论中,衬底51用于指衬底50和半导体材料50A/50B(如果形成的话)。
半导体材料50A和50B(例如,外延半导体材料)可以具有大于、基本上等于或小于衬底50的晶格常数的晶格常数。半导体材料50A和50B的晶格常数由产生的FinFET的导电类型(例如,N型或P型)所选择的材料确定。此外,在NMOS区域中外延生长与PMOS区域中的材料不同的材料可能是有利的。在各个实施例中,半导体材料(例如,50A、50B)可以包括硅锗、碳化硅、纯或基本上纯的锗、III-V化合物半导体、II-VI化合物半导体等。例如,用于形成III-V族化合物半导体的可用材料包括但不限于InAs、AlAs、GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlP、GaP等。
下一步,参照图4,使用例如光刻和蚀刻技术图案化衬底51。例如,在衬底51上方形成掩模层,诸如垫氧化物层(未示出)和上面的垫氮化物层(未示出)。垫氧化物层可以是例如,使用热氧化工艺形成的包括氧化硅的薄膜。垫氧化物层可以用作衬底51和上面的垫氮化物层之间的粘合层。在一些实施例中,垫氮化物层由氮化硅、氮氧化硅、碳化硅、碳氮化硅等或它们的组合形成,并且可以使用例如低压化学汽相沉积(LPCVD)或等离子体增强化学汽相沉积(PECVD)形成。
可以使用光刻技术图案化掩模层。通常,光刻技术利用沉积、照射(曝光)以及显影的光刻胶材料(未示出),以去除部分光刻胶材料。剩余的光刻胶材料保护下面的材料(诸如该实例中的掩模层)免受诸如蚀刻的随后的工艺步骤(诸如蚀刻)的影响。在该实例中,使用光刻胶材料来图案化垫氧化物层及垫氮化物以形成图案化掩模58。如图4中示出的,图案化掩模58包括图案化垫氧化物52及图案化垫氮化物56。
如图4示出的,随后使用图案化掩模58图案化衬底51的暴露部分以形成沟槽61,从而限定邻近的沟槽之间的半导体鳍64(也称为鳍)。在一些实施例中,通过使用例如反应离子蚀刻(RIE)、中性束蚀刻(NBE)等或它们的组合在衬底51中蚀刻沟槽来形成半导体鳍64(例如,64A和64B)。该蚀刻可以是各向异性的。在一些实施例中,沟槽可以是彼此平行的带(从顶部看),并且相对彼此紧密间隔开。在一些实施例中,沟槽可以是连续的并且围绕半导体鳍64。
可以通过任何合适的方法图案化鳍64。例如,可以使用一个或多个光刻工艺(包括双重图案化或多重图案化工艺)图案化鳍64。通常,双重图案化或多重图案化工艺结合光刻和自对准工艺,允许创建具有例如比使用单一直接光刻工艺另外可获得的间距更小的间距的图案。例如,在一个实施例中,在衬底上方形成牺牲层并且使用光刻工艺图案化牺牲层。使用自对准工艺在图案化的牺牲层旁边形成间隔件。之后去除牺牲层,之后可以使用剩余的间隔件或芯轴图案化鳍。
如图4示出的,在第一区域200中形成鳍64A,并且在第二区域300中形成鳍64B。前面说过,衬底50的区域200中的顶部由半导体材料50A替换。因此,位于半导体材料50A和衬底50之间的界面63之上的鳍64A的部分(例如,上半部分)由半导体材料50A形成,并且位于界面63之下的鳍64A的部分(例如,下半部分)由衬底50的材料形成。在示出的实例中,鳍64B完全由衬底50的材料形成。在示例性实施例中,界面63之上的鳍64A的部分由硅锗(例如,SiGe)形成,界面63之下的鳍64A的部分由硅(Si)形成,并且鳍64B由硅(Si)形成。
图4的实例示出了沟槽61的底部延伸至界面63之下的情况。在其它实施例中,沟槽61的底部在界面63之上或在界面63处延伸,在这种情况下,鳍64A完全由半导体形成材料50A形成,并且鳍64B完全由衬底50的材料形成。虽然图4示出了区域200中的一个鳍64A和区域300中的一个鳍64B,但是可以在区域200和/或区域300中形成多于一个鳍。这些和其它变化旨在完全地包括在本发明的范围内。为了简单起见,可以在所有随后的附图中不示出界面63。
在一些实施例中,图案化垫氮化物56的厚度T1在约18.5nm至约21.5nm的范围内,并且图案化垫氧化物52的厚度T2在约1.5nm至约2.5nm的范围内。在鳍64的顶面和接近鳍64的衬底50的上表面50U之间测量的鳍高度H1可以在从约109.5nm到约117.5nm的范围内。在一些实施例中,鳍64A的鳍宽度W1(例如,在鳍的顶面处测量的)在约8.8nm至约12.4nm的范围内,并且鳍64B的鳍宽度W2(例如,在鳍的顶面处测量的)在从约8.9nm至约13.1nm的范围内。在示出的实施例中,两个邻近的鳍64A和64B之间的间距P1在从约24.5nm至约27.5nm的范围内。
现在参照图5,在衬底50上方和鳍64上方共形地形成覆盖层83。在一些实施例中,覆盖层83是半导体覆盖层,诸如硅覆盖层(例如,硅层)。因此,覆盖层83也可以称为硅衬垫。可以使用诸如CVD、PVD、原子层沉积(ALD)等或它们的组合的任何合适的沉积方法形成覆盖层83。除了硅之外,诸如氧化硅、氮化硅、它们的组合或它们的多层的其它合适的材料也可以用于覆盖层83。下面的讨论可以将覆盖层83称为硅覆盖层或硅衬垫,应该理解,除了硅以外,其它合适的材料也可以用于覆盖层83。
根据实施例,覆盖层83是硅覆盖层,并且通过使用诸如二硅烷(例如,Si2H6)的含硅前体和诸如氢(例如,H2)的载气的CVD形成。在一些实施例中,Si2H6的流率在从约160标准立方厘米每分钟(sccm)至约200sccm的范围内,H2的流率在从约2标准升每分钟(slm)至约5slm的范围内。在一些实施例中,沉积工艺的压力在从约580托至约690托的范围内。在一些实施例中,形成的覆盖层83的厚度在从约1.3nm至约1.6nm的范围内。
在形成覆盖层83之后,对覆盖层83实施氮化处理410。在一些实施例中,使用诸如氨(例如NH3)的含氮气体实施氮化处理410。氮化处理410将覆盖层83的顶层(例如,外部)转化为氮化物(例如,氮化硅),该氮化物可以防止或减少鳍64的氧化。
在一些实施例中,以从约2.5slm至约4slm的范围内的NH3的流率实施氮化处理410。氮化处理410的温度可以在从约680℃至约750℃的范围内。氮化处理410的压力可以在从约4.6托至约5.2托的范围内。氮化处理410可以实施在约30秒至约120秒的之间持续时间。
在氮化处理之后,覆盖层83的外部(其外部可以包括例如覆盖层83的总厚度的约2%至约3%)转化为氮化物(例如,氮化硅,图5中没有单独示出)。在示例性实施例中,覆盖层83是硅覆盖层,并且覆盖层83的顶层(例如,厚度的顶部2%至3%)通过氮化处理410转化为氮化硅。硅氮化物形成防止或减少鳍64的氧化的保护性薄膜。
由于鳍64的尺寸(例如,图4中的W1和W2)在改进的工艺技术中持续缩小,因此鳍64在随后的处理期间具有较高的塌陷的风险。覆盖层83为鳍64提供结构支撑,以防止随后的工艺中鳍64的塌陷。此外,通过氮化处理410形成的氮化物膜与本发明的下文公开的其它部件一起防止或减少鳍64的氧化,从而有助于减少由于氧化引起的鳍损失并且保持鳍64的尺寸。
下一步,参照图6,在覆盖层83上方共形地形成介电层86。介电层86可以包括合适的介电材料,其减少或防止鳍64的氧化。例如,介电层86可以是通过CVD、PVD、ALD等或它们的组合形成的氮化硅(例如,SiNx)、氮氧化硅(例如,SiON)或氧化硅(例如,SiO2)层。
在示例性实施例中,介电层86是氮化硅层,并且通过使用二氯硅烷(例如,SiH2Cl2)和氨(例如NH3)作为前体的ALD来形成。在一些实施例中,SiH2Cl2的流率在约1slm和约4slm之间,NH3的流率在约5slm和约8slm之间。用于介电层86的沉积工艺的温度可以在约400℃和约600℃之间,并且沉积工艺的压力可以在约2托和约4托之间。在一些实施例中,在完成沉积工艺之后,形成的介电层86的厚度T3在约2nm至约4nm的范围内。
下一步,如图7示出的,形成绝缘材料62以填充沟槽61(见图6)。在一些实施例中,在沉积绝缘材料62之后,实施退火工艺420以固化沉积的绝缘材料62。绝缘材料62可以是诸如氧化硅的氧化物、氮化物等或它们的组合,并且可以通过高密度等离子体化学汽相沉积(HDP-CVD)、可流动CVD(FCVD)等或它们的组合形成。可以使用其它绝缘材料和/或其它形成工艺。
在示例性实施例中,绝缘材料62包括氧化硅(例如,SiO2)并且通过FVCD工艺形成。如图7示出的,沉积的绝缘材料62填充沟槽61(见图6)并且延伸至鳍64的顶面之上。例如,绝缘材料62在鳍64的顶面上方的高度H2在从约250nm至约350nm的范围内。
一旦沉积绝缘材料62,实施退火工艺420以固化沉积的绝缘材料62。在一些实施例中,退火工艺420包括第一退火工艺和随后的第二退火工艺。在一些实施例中,第一退火工艺是湿退火,例如湿蒸气退火,并且第二退火工艺是干退火。根据实施例,第一退火是在从约500℃至约700℃的范围内的温度下实施约两小时至约三小时的持续时间的湿蒸汽退火(例如,在包括水蒸汽的环境中实施的热退火工艺)。根据实施例,第二退火工艺是在包含氮气(例如,N2气体)的环境中,在从约600℃至约800℃范围内的温度下实施约一小时至约两小时的持续时间的干退火。
由于绝缘材料62的厚度,退火工艺420可以固化绝缘材料62的顶部(例如,在鳍64的顶面之上或接近顶面的部分),并且可能没有充分固化绝缘材料62的底部(例如,虚线69下面的部分)。随后的退火工艺430(见图9)将进一步固化绝缘材料62。
下一步,参照图8,诸如CMP的平坦化工艺可以去除过量的绝缘材料62并且形成绝缘材料62的平坦的顶面。如图8示出的,平坦化工艺也暴露了介电层86的顶面。
参照图9,在平坦化工艺之后,实施退火工艺430以进一步固化绝缘材料62的剩余部分。在一些实施例中,介电层86(例如,氮化硅)的顶层87(例如,外部)在退火工艺430之后被氧化并且转化为介电层86的氧化物(例如,氮氧化硅)。如图9示出的,介电层86的剩余部分表示为介电层85。在下文中讨论更多细节。
在一些实施例中,退火工艺430包括第一退火工艺和随后的第二退火工艺。在一些实施例中,第一退火工艺是湿退火,例如湿蒸气退火,并且第二退火工艺是干退火。根据实施例,第一退火是在从约500℃至约700℃的范围内的温度下实施约两小时至约三小时的持续时间的湿蒸汽退火。根据实施例,第二退火工艺是在包含氮气(例如,N2气体)的环境中,在从约600℃至约800℃范围内的温度下实施约一小时至约两小时的持续时间的干退火。在一些实施例中,可以在与图7中的退火工艺420相同的条件下实施退火工艺430。
在一些实施例中,介电层86的顶层87(例如,外部)被例如扩散至绝缘材料62中湿蒸汽中的氧氧化,并且被转化为介电层86的材料的氧化物。在示例性实施例中,介电层86(见图8)包括氮化硅,氧化的顶层87(例如,介电层)包括氮氧化硅,并且介电层85包括氮化硅。在下面的讨论中,氧化的顶层87和介电层85可以统称为介电衬层堆叠件88。
在一些实施例中,氧化的顶层87的厚度T5约为介电层86的原始厚度T3(见图6)的三分之一。换句话说,氧化顶层87的厚度与介电层85的厚度T4之间的比率约为1:2。
在一些实施例中,引起介电层86的(部分)氧化的氧来自退火工艺期间使用的湿蒸汽,因此,介电层86的更靠近氧源的顶部的氧化多于介电层86的远离氧源的底部。例如,在一些实施例中,参照图9,在退火工艺430之后,接近鳍64的顶面的介电衬层堆叠件88的第一部分中的元素硅(例如,Si)、氮(例如,N)和氧(例如,O)之间的比率(例如,原子百分比)(即,Si:N:O之间的比率)为约5:2.5:2.5。在一些实施例中,接近鳍64的中点(即,鳍64的顶面和衬底50的上表面50U之间的中点)的介电衬层堆叠件88的第二部分中的Si:N:O的比率为约5:3:2。在一些实施例中,接近衬底50的上表面50U的介电衬层堆叠件88的第三部分中的Si:N:O的比率为约5:4:1。
虽然在图9中示出了在退火工艺430期间和/或之后形成的氧化的顶层87,但是氧化的顶层87也可以在退火工艺420期间和/或之后形成。例如,当绝缘材料62的厚度H2(见图7)较小(例如,350nm或更小)时,来自退火工艺420的蒸汽湿退火的氧可以氧化介电层86,并且形成氧化的顶层87。这些和其它变化均旨在完全地包括在本发明的范围内。
由于通过例如介电衬层堆叠件88和通过氮化处理410形成在覆盖层83上方的薄氮化物膜提供的保护,因此在退火工艺期间(例如,420和430),保护鳍64免受氧气的影响,并且几乎没有发生鳍64的氧化。因此,目前公开的方法避免了由于鳍64的氧化导致的鳍临界尺寸损失。
下一步,如图10示出的,使用例如干蚀刻去除图案化掩模56(见图9),但是也可以使用其它合适的去除工艺。例如,可以实施使用磷酸(例如,H3PO4)的干蚀刻去除图案化掩模56,并且因此绝缘材料62中形成暴露图案化掩模52的顶面的开口67。如图10示出的,去除工艺也去除了设置在鳍64的顶面上方的介电层85的部分、氧化的顶层87的部分以及覆盖层83的部分。
下一步,在图11中,使绝缘材料62凹进,从而使得鳍64的上部突出在凹进的绝缘材料62的上表面62U之上。如图11示出的,绝缘材料62的凹进也去除了位于凹进的绝缘材料62的上表面62U之上的图案化掩膜52、介电层85的部分、氧化的顶层87的部分以及覆盖层83的部分。在一些实施例中,凹进的绝缘材料62形成诸如浅沟槽隔离(STI)区域的隔离区域62。可以使用干蚀刻使绝缘材料62凹进,并且干蚀刻可以使用包含氨(例如,NH3)和氟化氢(HF)的蚀刻气体。其它合适的蚀刻工艺也可以用于使绝缘材料62凹进。
绝缘材料62的顶面62U可具有平坦表面(如图所示)、凸表面、凹表面(诸如凹陷)或它们的组合。绝缘材料62的顶面62U可以通过适当的蚀刻形成为平坦的,凸的和/或凹的。可以使用可接受的蚀刻工艺(诸如对绝缘材料62的材料有选择性的蚀刻工艺)使绝缘材料62凹进。例如,可以使用采用蚀刻或应用材料公司的SICONI工具或稀释的氢氟酸(dHF)的化学氧化物去除。
如图11示出的,在鳍64的顶面和接近鳍64的顶面62U之间测量的鳍高度H3可以在约52.5nm和约55.5nm之间的范围内。在一些实施例中,用于鳍64A(例如,包括SiGe的鳍)的鳍宽度W3在约7.5nm至约11nm的范围内,并且用于鳍64B(例如,包括硅的鳍)的鳍宽度W4在约7nm至约13.7nm的范围内。在绝缘材料62凹进之后测量的鳍64A和鳍64B之间的鳍间距P2在约24.5nm至约27.5nm之间。在一些实施例中,鳍间距P2与鳍间距P1(见图4)相同。
图12示出了半导体鳍64(例如,64A/64B)上方的伪栅极结构75(例如,75A和75B)的形成。在一些实施例中,伪栅极结构75包括栅极电介质66和栅极68。可以在伪栅极结构75上方形成掩模70。为了形成伪栅极结构75,在半导体鳍64和隔离区域62上形成介电层。介电层可以是例如氧化硅、硅氮化物、它们的多层等,并且可以根据可接受的技术沉积或热生长。在一些实施例中,介电层可以是高k介电材料,并且在这些实施例中,介电层可以具有大于约7.0的k值,并且可以包括Hf、Al、Zr、La、Mg、Ba、Ti、Pb的金属氧化物或硅酸盐、它们的多层以及它们的组合。介电层的形成方法可以包括分子束沉积(MBD)、原子层沉积(ALD)、等离子体增强CVD(PECVD)等。
在介电层上方形成栅极层,在栅极层上方形成掩模层。可以在介电层上方沉积栅极层,并且之后诸如通过CMP平坦化栅极层。可以在栅极层上方沉积掩模层。栅极层可以由例如多晶硅形成,但是也可以使用其它材料。在一些实施例中,栅极层可以包括诸如TiN、TaN、TaC、Co、Ru、Al、它们的组合或它们的多层的含金属材料。掩模层可以由例如氮化硅等形成。
在形成层(例如,介电层、栅极层和掩模层)之后,可以使用可接受的光刻和蚀刻技术图案化掩模层以形成掩模70。之后,可以通过可接受的蚀刻技术将掩模70的图案转印至栅极层和介电层以分别形成栅极68和栅极电介质66。栅极68和栅极电介质66覆盖半导体鳍64的相应的沟道区域。栅极68也可以具有基本垂直于相应的半导体鳍64的纵向方向的纵向方向。
图13、图14A、图14B、图14C、图15至图20、图21A和图21B示出了FinFET器件100的进一步处理的各个截面图。在一些实施例中,对PMOS区域200和NMOS区域300实施如图13、图14A、图14B、图14C、图15至图20、图21A和图21B示出的工艺,其中,调整一些材料(例如,用于源极/漏极区域的掺杂剂或金属栅极的功函层)以适应形成在相应的区域中的器件类型(例如,P型器件或N型器件)。为了简单起见,在图13、图14A、图15至图20和图21A的每个中示出沿着鳍64A或鳍64B的截面A-A的一个截面图(而不是沿着鳍64A的截面A-A和沿着鳍64B的截面A-A的两个截面图)。
如图13示出的,在鳍64中形成轻掺杂漏极(LDD)区域65。可以通过等离子体掺杂工艺形成LDD区域65。等离子体掺杂工艺可以在鳍64中注入N型杂质(用于N型器件)或者P型杂质(用于P型器件)以形成LDD区域65。例如,可以形成图案化掩模层以在将N型杂质注入至NMOS区域300的LDD区域65时屏蔽PMOS区域200。类似地,可以形成另一图案化掩模层以在将P型杂质注入至PMOS区域200的LDD区域65时屏蔽NMOS区域300。图13也示出了半导体材料50A和衬底50之间的界面63,其在示出的实施例中存在于鳍64A中并且不存在于鳍64B中。为了简单起见,可以不在所有附图中示出界面63。
在一些实施例中,LDD区域65邻接FinFET器件100的沟道区域。LDD区域65的部分可以在栅极68下方延伸至FinFET器件100的沟道区域。图13示出了LDD区域65的非限制性实例。LDD区域65的其它配置、形状和形成方法也是可能的并且均旨在完全地包括在本发明的范围内。例如,可以在形成第一栅极间隔件72之后形成LDD区域65。
仍然参照图13,在形成LDD区域65之后,在栅极结构上形成栅极间隔件74。栅极间隔件74可以包括第一栅极间隔件72和第二栅极间隔件73。在图13的实例中,在栅极68的相对侧壁上并且在栅极电介质66的相对侧壁上形成第一栅极间隔件72。第一栅极间隔件72也可以在半导体鳍64的上表面(其中,在鳍64内形成LDD区域65)和隔离区域62的上表面上方延伸。如图13示出的,在第一栅极间隔件72上形成第二栅极间隔件73。第一栅极间隔件72可以由诸如氮化硅的氮化物、氮氧化硅、碳化硅、碳氮化硅等或它们的组合形成,并且可以使用例如,热氧化、CVD或其它合适的沉积工艺形成。第二栅极间隔件73可以由使用适当的沉积方法的氮化硅、碳氮化硅、它们的组合等形成。
在示例性实施例中,通过在FinFET器件100上方首先共形地沉积第一栅极间隔件层,之后在沉积的第一栅极间隔件层上方共形地沉积第二栅极间隔件层来形成栅极间隔件74。下一步,实施诸如干蚀刻工艺的各向异性刻蚀工艺,以去除第二栅极间隔件层的设置在FinFET器件100的上表面(例如,伪栅极结构75的上表面)上的第一部分,同时保留第二栅极间隔件层的沿着伪栅极结构75的侧壁设置的第二部分。在各向异性蚀刻工艺之后保留的第二栅极间隔件层的第二部分形成第二栅极间隔件73。各向异性蚀刻工艺也去除了第一栅极间隔件层的设置在第二栅极间隔件73的侧壁的外部的部分,并且第一栅极间隔件层的剩余部分形成第一栅极间隔件72。如图13示出的第一栅极间隔件72和第二栅极间隔件73的形状和形成方法仅仅是非限制性实例,并且其它形状和形成方法也是可能的。
下一步,如图14A示出的,形成源极/漏极区域80。通过蚀刻鳍64内的LDD区域65以形成凹槽,并且使用诸如金属有机CVD(MOCVD)、分子束外延(MBE)、液相外延(LPE)、汽相外延(VPE)、选择性外延生长(SEG)等或它们的组合的合适的方法在凹槽中外延生长材料来形成源极/漏极区域80。
如图14A示出的,外延源极/漏极区域80可以具有从鳍64的相应的表面凸起的表面(例如,在鳍64的非凹进部分之上凸起)并且可以具有小平面。邻近的鳍64的源极/漏极区域80可合并以形成连续的外延源极/漏极区域80(见图14B)。在一些实施例中,用于邻近的鳍64的源极/漏极区域80没有合并在一起并且保持分隔开的源极/漏极区域80(见图14C)。在产生的FinFET是n型FinFET的一些示例性实施例中,源极/漏极区域80包括碳化硅(SiC)、硅磷(SiP)、磷掺杂硅碳(SiCP)等。在产生的FinFET是p型FinFET的可选示例性实施例中,源极/漏极区域80包括硅锗(SiGe)以及诸如硼或铟的p型杂质。在一些实施例中,源极/漏极区域80中的硅锗形成为比FinFET器件的沟道区域中的硅锗具有更高的锗原子百分比,从而使得在FinFET器件的沟道区域中诱导压缩应变。
图14B示出了实施例中的图14A所示的FinFET器件100的但是沿着截面C-C的截面图。在图14B的实例中,外延源极/漏极区域80A和80B合并以形成连续的外延源极/漏极区域80。图14C示出了另一实施例中的图14A所示的FinFET器件100的但是沿着截面C-C的截面图。在图14C的实例中,外延源极/漏极区域80A和80B没有合并并且保持分隔开的源极/漏极区域80。
外延源极/漏极区域80可以注入有掺杂剂以形成源极/漏极区域80,随后是退火。注入工艺可以包括形成和图案化诸如光刻胶的掩模以覆盖FinFET的将被保护免受注入工艺的影响的区域。源极/漏极区域80可以具有在从约1E19cm-3至约1E21cm-3的范围内的杂质(例如,掺杂剂)浓度。在一些实施例中,可以在生长期间原位掺杂外延源极/漏极区域。
下一步,如图15至图17示出的,在图14A示出的结构上方形成第一层间电介质(ILD)90,并且实施后栅极工艺(有时称为替换栅极工艺)。在后栅极工艺中,栅极68和栅极电介质66(见图14A)认为是伪结构并且被去除并且用有源栅极和有源栅极电介质替换。
参照图15,在一些实施例中,第一ILD 90由诸如磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、未掺杂的硅酸盐玻璃(USG)等的介电材料形成,并且可以通过诸如CVD、PECVD或FCVD的任何合适的方法沉积。可以实施诸如CMP工艺的平坦化工艺以去除掩模70并且平坦化第一ILD 90的顶面,从而使得第一ILD 90的顶面与栅极68的顶面齐平。因此,在一些实施例中,在CMP工艺之后,暴露栅极68的顶面。
根据一些实施例,在蚀刻步骤中去除栅极68和位于栅极68正下方的栅极电介质66,使得在相应的间隔件74之间形成凹槽89。每个凹槽89暴露相应的鳍64的沟道区域。每个沟道区域均设置在邻近的一对外延源极/漏极区域80之间。在伪栅极去除期间,当蚀刻伪栅极68时,伪栅极介电层66可以用作蚀刻停止层。之后,可以在伪栅极68的去除之后去除伪栅极介电层66。
下一步,在图16中,形成用于替换栅极97(见图17)的栅极介电层96、阻挡层94、晶种层92和栅电极98。栅极介电层96共形地沉积在凹槽89中,诸如在鳍64的顶面和侧壁上和第一栅极间隔件72的侧壁上以及第一ILD 90的顶面上。根据在一些实施例,栅极介电层96包括氧化硅、氮化硅或它们的多层。在其它实施例中,栅极介电层96包括高k介电材料,并且在这些实施例中,栅极介电层96可以具有大于约7.0的k值,并且可以包括Hf、Al、Zr、La、Mg、Ba、Ti、Pb的金属氧化物或硅酸盐以及它们的组合。栅极介电层96的形成方法可以包括MBD、ALD、PECVD等。
下一步,在栅极介电层96上方共形地形成阻挡层94。阻挡层94可以包括诸如氮化钛的导电材料,但是可以可选地利用诸如氮化钽、钛、钽等的其它材料。可以使用诸如等离子体增强CVD(PECVD)的CVD工艺形成阻挡层94。然而,可以可选地使用诸如溅射或金属有机化学汽相沉积(MOCVD)、原子层沉积(ALD)的其它可选工艺。
虽然在图16中未示出,但是可以在替换栅极97中(例如在阻挡层94上方)形成功函层。例如,可以在区域200中形成P型功函层,并且可以在区域300中形成N型功函层。可以包括在栅极结构(例如,97)中的示例性P型功函金属包括TiN、TaN、Ru、Mo、Al、WN、ZrSi2、MoSi2、TaSi2、NiSi2、WN、其它合适的P型功函材料或它们的组合。可以包括在栅极结构中的示例性N型功函金属包括Ti、Ag、TaAl、TaAlC、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、其它合适的N型功函材料或它们的组合。功函值与功函层的材料组成相关,并且因此,选择功函层的材料以调整其功函值,从而使得将要在相应的区域中形成的器件实现目标阈值电压Vt。可以通过CVD、物理汽相沉积(PVD)和/或其它合适的工艺沉积功函层。
下一步,在阻挡层94(或者功函层,如果形成的话)上方形成晶种层92。晶种层92可以包括铜(Cu)、钛(Ti)、钽(Ta)、氮化钛(TiN)、氮化钽(TaN)等或它们的组合,并且可以通过原子层沉积(ALD)、溅射、物理汽相沉积(PVD)等沉积。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同的材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和位于钛层上方的铜层。
下一步,在晶种层92上方沉积栅电极98,并且填充凹槽89的剩余部分。栅电极98可以由诸如TiN、TaN、TaC、Co、Ru、Al等含金属材料、它们的组合或它们的多层制成,并且可以通过例如电镀、化学镀或其它合适的方法形成。
下一步,如图17示出的,在栅电极98的形成之后,可以实施诸如CMP的平坦化工艺,以去除栅极介电层96、阻挡层94、功函层(如果形成的话)、晶种层92以及栅电极98的材料的过量部分,其过量部分位于第一ILD 90的顶面上方。因此,栅电极98的材料、晶种层92、功函层(如果形成的话)、阻挡层94和栅极介电层96的最终的剩余部分形成产生的FinFET器件100的替换栅极97。
下一步,在图18中,在第一ILD 90上方沉积第二ILD 95。在实施例中,第二ILD 95是通过可流动CVD方法形成的可流动膜。在一些实施例中,第二ILD 95由诸如PSG、BSG、BPSG、USG等的介电材料形成,并且可以通过诸如CVD和PECVD的任何合适的方法沉积。穿过第一ILD 90和/或第二ILD 95形成用于接触件102(见图21A和图21B)的接触开口91和93。例如,接触开口91形成为穿过第二ILD 95并且暴露替换栅极97,而接触开口93形成为穿过第一ILD 90和第二ILD 95并且暴露源极/漏极区域80。
下一步,在图19中,在源极/漏极区域80上方形成硅化物区域82,并且在硅化物区域82和第二ILD 95上方形成阻挡层104。在一些实施例中,通过在源极/漏极区域80上方沉积能够与半导体材料(例如,硅、锗)反应的金属以形成硅化物或锗化物区域来形成硅化物区域82。该金属可以是镍、钴、钛、钽、铂、钨、其它贵金属、其它难熔金属、稀土金属或它们的合金。之后实施热退火工艺,使得沉积的金属与源极/漏极区域80反应以形成硅化物区域82。在热退火工艺之后,去除未反应的金属。
阻挡层104共形地形成在硅化物区域82和第二ILD 95上方,并且内衬接触开口91/93的侧壁和底部。阻挡层104可以包括诸如钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等的导电材料,并且可以使用诸如等离子体增强CVD(PECVD)的CVD工艺形成。然而,也可以使用诸如溅射或金属有机化学汽相沉积(MOCVD)、物理汽相沉积(PVD)、原子层沉积(ALD)等其它可选工艺。
下一步,在图20中,在阻挡层104上方形成晶种层109,并且在晶种层109上方形成导电材料110。晶种层109可以通过PVD、ALD或CVD沉积,并且可以由钨、铜或铜合金形成,但是也可以可选地使用其它合适的方法和材料。
一旦已经形成晶种层109,则可以在晶种层109上形成导电材料110以填充接触开口91/93。导电材料110可以包括钨,但是可以可选地利用诸如铝、铜、氮化钨、钌、银、金、铑、钼、镍、钴、镉、锌、这些的合金、它们的组合等的其它合适的材料。可以使用诸如PVD、CVD、ALD、镀(例如,电镀)和回流的任何合适的沉积方法形成导电材料110。
下一步参照图21A,一旦已经填充了接触开口91/93,则可以通过诸如CMP的平坦化工艺去除接触开口91/93的外部的过量的阻挡层104、晶种层109和导电材料110,但是可以使用任何合适的去除工艺。因此,在接触开口91/93中形成接触插塞102。虽然在图21A中的相同截面中示出了位于源极/漏极区域80上方和替换栅极97上方的接触插塞102,但是接触插塞102可以在FinFET器件100中处于不同的截面。
图21B示出了一些实施例中的图21A中所示的FinFET器件100的但沿着截面B-B的截面图。在图21B中,在鳍64A上方形成第一替换栅极99A(例如,包括栅极电介质96/阻挡层94/晶种层92/栅电极98A),并且在鳍64B上方形成第二替换栅极99B(例如,包括栅极电介质96/阻挡层94/晶种层92/栅电极98B)。第一替换栅极99A例如通过第一ILD 90与第二替换栅极99B分隔开。第一接触插塞102电连接至栅电极98A,第二接触插塞102电连接至栅电极98B。
虽然在图21B的截面图中未示出,但是可以在替换栅极(例如,99A和99B)和第一ILD 90之间(例如,沿着替换栅极99A和99B的侧壁)之间形成栅极间隔件74(见图13)。例如,在图21B的截面图中,可以沿着第一替换栅极99A的两个侧壁并且沿着第二替换栅极99B的两个侧壁形成栅极间隔件74。例如,在这种实施例中,在第一替换栅极99A和第二替换栅极99B之间形成栅极间隔件74。在一些实施例中,栅极间隔件74没有形成在第一替换栅极99A和第二替换栅极99B之间,但是形成在替换栅极99A和99B的外部侧壁(例如,第一替换栅极99A的最左侧壁和第二替换栅极99B的最右侧壁)上。在又其它实施例中,在图21B的截面图中没有形成栅极间隔件74。栅极间隔件74的这些和其它变化均旨在完全地包括在本发明的范围内。
本发明的变化和修改是可能的并且均旨在完全地包括在本发明的范围内。例如,可以在区域200和300中的每个中形成多于一个鳍,并且可以在鳍64上方形成多于一个栅极。鳍64的形成可以包括其它处理步骤,并且鳍64A和64B的材料可以相同或可以不相同。此外,在以上讨论的替换栅极工艺中,伪栅极结构75A和75B在由替换栅极97替换之前彼此分隔开。在其它实施例中,可以形成从鳍64A连续延伸至鳍64B的伪栅极结构,之后用从鳍64A连续延伸至鳍64B的替换栅极来替换伪栅极结构,并且随后,切割替换栅极(例如,通过蚀刻鳍64A和64B之间的开口,并且用介电材料填充开口)以形成两个分隔开的替换栅极(每个鳍64A和64B上一个)。这些和其它变化均旨在完全地包括在本发明的范围内。
图22示出了根据一些实施例的形成半导体器件的方法的流程图。应该理解,图22所示的实施例方法仅仅是许多可能的实施例方法的实例。本领域普通技术人员将意识到许多变化、替换和修改。例如,可以添加、去除、替换、重新排列和重复图22中所示的各个步骤。
参照图22,在步骤1010中,在衬底的第一区域中的第一鳍上方形成半导体覆盖层。在步骤1020中,在半导体覆盖层上方形成介电层。在步骤1030中,在第一鳍的顶面上方和第一鳍的相对侧上形成绝缘材料。在步骤1040中,固化绝缘材料。在步骤1050中,在固化之后,使绝缘材料凹进以暴露第一鳍的顶部。在步骤1060中,在第一鳍的顶部上方形成栅极结构。
实施例可以实现优势。覆盖层83和介电衬层堆叠件88为鳍64提供结构支撑,以减少或防止随后的工艺中的鳍的塌陷。此外,介电衬层堆叠件88在随后的退火工艺中将鳍64与氧隔离,从而减少或避免了鳍的氧化。保留了设计的鳍尺寸(例如鳍宽度、鳍间距),这有利地改进了形成的器件的电性能。覆盖层83的氮化处理提供了氮化物的额外的薄膜以减少或防止氧气渗透至鳍内,进一步减小了鳍的氧化的可能性。
在实施例中,方法包括:在衬底的第一区域中的第一鳍上方形成半导体覆盖层;在半导体覆盖层上方形成介电层;在介电层上方形成绝缘材料,该绝缘材料的上表面比第一鳍的上表面更远离衬底延伸;使绝缘材料凹进以暴露第一鳍的顶部;以及在第一鳍的顶部上方形成栅极结构。在实施例中,该方法还包括在形成半导体覆盖层之前:用外延半导体材料替换衬底的第一区域中的第一部分;以及图案化外延半导体材料以形成第一鳍。在实施例中,形成半导体覆盖层包括在第一鳍上方形成硅覆盖层。在实施例中,该方法还包括在半导体覆盖层上方形成介电层之前,用含氮化物气体处理半导体覆盖层。在实施例中,形成介电层包括形成包括半导体覆盖层的材料的氮化物的介电层。在实施例中,该方法还包括在使绝缘材料凹进之前固化绝缘材料。在实施例中,半导体覆盖层是硅覆盖层,并且介电层是氮化硅层,其中,固化绝缘材料将介电层的顶层转化为氮氧化硅。在实施例中,固化包括实施第一退火工艺;在第一退火工艺之后实施平坦化工艺;以及实施第二退火工艺。在实施例中,平坦化工艺去除绝缘材料的顶部并且暴露第一鳍的上表面上方的掩模层。在实施例中,实施第一退火工艺包括实施第一湿蒸气退火;以及在第一湿蒸气退火之后,实施第一干退火。在实施例中,在包含氮气的环境中实施第一干退火。在实施例中,实施第二退火工艺包括实施第二湿蒸汽退火;以及在第二湿蒸气退火之后实施第二干退火。在实施例中,第一区域是PMOS区域,其中,该方法还包括在衬底的邻近于PMOS区域的NMOS区域中形成第二鳍,其中,在第一鳍上方和第二鳍上方形成半导体覆盖层和介电层。
在实施例中,形成鳍式场效应晶体管(FinFET)器件的方法包括:在衬底的PMOS区域中形成第一鳍;在衬底的邻近于PMOS区域的NMOS区域中形成第二鳍;以及在第一鳍和第二鳍上方形成硅覆盖层。该方法也包括对硅覆盖层实施氮化处理;在硅覆盖层上方形成第一介电材料;在第一鳍和第二鳍之间以及第一鳍和第二鳍上方沉积第二介电材料,其中,第一介电材料位于硅覆盖层和第二介电材料之间;并且实施热工艺以固化第二介电材料。该方法还包括在热工艺之后使第二介电材料凹进以暴露第一鳍的顶部和第二鳍的顶部;以及在第一鳍上方形成第一栅极结构并且在第二鳍上方形成第二栅极结构。在实施例中,形成硅覆盖层包括在第一鳍和第二鳍上方共形地形成硅覆盖层。在实施例中,实施氮化处理包括用包含氨的气体处理硅覆盖层。在实施例中,形成第一介电材料包括在硅覆盖层上方共形地形成氮化硅层,其中,实施热工艺将第一介电材料的顶层转化为氮氧化硅。
在实施例中,鳍式场效应晶体管(FinFET)器件包括突出在隔离区域(位于鳍的相对侧上)的上表面之上的鳍;位于鳍和隔离区域之间的硅覆盖层;位于硅覆盖层和隔离区域之间的第一介电材料;以及位于第一介电材料和隔离区域之间的与第一介电材料不同的第二介电材料,第二介电材料包括第一介电材料的氧化物。在实施例中,第一鳍包括硅锗,第一介电材料包括氮化硅,并且第二介电材料包括氮氧化硅。在实施例中,FinFET器件还包括位于硅覆盖层和第一介电材料之间的氧化硅膜。
在实施例中,鳍式场效应晶体管(FinFET)器件包括第一鳍;邻近于第一鳍的第二鳍,第二鳍具有与第一鳍不同的材料;位于第一鳍和第二鳍之间的隔离区域,其中,第一鳍的上部和第二鳍的上部突出在隔离区域之上;以及位于第一鳍的下部与隔离区之间并且位于第二鳍的下部与隔离区之间的半导体覆盖层。FinFET器件还包括位于半导体覆盖层和隔离区域之间的第一介电层;以及位于第一介电层与隔离区域之间的与第一介电层不同的第二介电层。在实施例中,第一鳍包括硅锗,并且第二鳍包括硅。在实施例中,第一鳍具有P型源极/漏极区域,并且第二鳍具有N型源极/漏极区域。在实施例中,第一介电层包括氮化硅,并且第二介电层包括氮氧化硅。在实施例中,FinFET器件还包括位于半导体覆盖层和第一介电层之间的氧化物膜,其中,氧化物膜包括半导体覆盖层的材料的氧化物。
在实施例中,形成半导体器件的方法包括:在从衬底突出的鳍上方形成半导体衬垫;在半导体衬垫上方共形地形成氮化硅层;以及在鳍上方和周围沉积隔离材料。该方法也包括使用热工艺固化隔离材料,其中,固化隔离材料将远离衬底的氮化硅层的上层转化为氮氧化硅;去除隔离材料的部分以形成浅沟槽隔离(STI)区域,其中,鳍突出在STI区域之上;以及在鳍上方形成栅极。在实施例中,该方法还包括用氮气处理半导体衬垫以在半导体衬垫上方形成介电膜,介电膜包括半导体衬垫的氮化物。在实施例中,固化包括实施第一热退火工艺以固化隔离材料的至少顶部;在第一热退火工艺之后使隔离材料凹进;以及在使隔离材料凹进之后实施第二热退火工艺。在实施例中,实施第一热退火工艺包括实施湿退火工艺;并且在湿退火工艺之后实施干退火工艺。
在实施例中,方法包括:在衬底的PMOS区域中形成具有硅锗的第一鳍;在衬底的NMOS区域中形成具有硅的第二鳍;在第一鳍和第二鳍上方形成硅覆盖层;以及在硅覆盖层上方形成包括氮化硅的介电层。该方法也包括在第一鳍和第二鳍之间形成隔离材料;固化隔离材料,其中,固化隔离材料将介电层的上层转化为氮氧化硅;使隔离材料凹进以暴露第一鳍的顶部和第二鳍的顶部;以及分别在第一鳍和第二鳍上方形成第一栅极结构和第二栅极结构。
上面概述了若干实施例的特征,使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解,它们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中它们可以做出多种变化、替换以及改变。
Claims (20)
1.一种形成鳍式场效应晶体管器件的方法,包括:
在衬底的第一区域中的第一鳍上方形成半导体覆盖层;
在所述半导体覆盖层上方形成介电层;
在所述介电层上方形成绝缘材料,所述绝缘材料的上表面比所述第一鳍的上表面更远离所述衬底延伸;
使所述绝缘材料凹进以暴露所述第一鳍的顶部;以及
在所述第一鳍的顶部上方形成栅极结构。
2.根据权利要求1所述的方法,还包括,在形成所述半导体覆盖层之前:
用外延半导体材料替换所述衬底的所述第一区域中的第一部分;以及
图案化所述外延半导体材料以形成所述第一鳍。
3.根据权利要求1所述的方法,其中,形成所述半导体覆盖层包括在所述第一鳍上方形成硅覆盖层。
4.根据权利要求1所述的方法,还包括在所述半导体覆盖层上方形成所述介电层之前,用含氮化物气体处理所述半导体覆盖层。
5.根据权利要求1所述的方法,其中,所述第一鳍和所述衬底包括相同的材料。
6.根据权利要求1所述的方法,还包括:在使所述绝缘材料凹进之前,固化所述绝缘材料。
7.根据权利要求6所述的方法,其中,其中,所述半导体覆盖层是硅覆盖层,并且所述介电层是氮化硅层,其中,固化所述绝缘材料将所述介电层的顶层转化为氮氧化硅。
8.根据权利要求6所述的方法,其中,所述固化包括:
实施第一退火工艺;
在所述第一退火工艺之后实施平坦化工艺;以及
实施第二退火工艺。
9.根据权利要求8所述的方法,其中,所述平坦化工艺去除所述绝缘材料的顶部并且暴露所述第一鳍的所述上表面上方的掩模层。
10.根据权利要求8所述的方法,其中,实施所述第一退火工艺包括:
实施第一湿蒸气退火;以及
在所述第一湿蒸气退火之后,实施第一干退火。
11.根据权利要求10所述的方法,其中,在包含氮气的环境中实施所述第一干退火。
12.根据权利要求10所述的方法,其中,实施所述第二退火工艺包括:
实施第二湿蒸汽退火;以及
在所述第二湿蒸气退火之后实施第二干退火。
13.根据权利要求1所述的方法,其中,所述第一区域是PMOS区域,其中,所述方法还包括在衬底的邻近于所述PMOS区域的NMOS区域中形成第二鳍,其中,在所述第一鳍上方和所述第二鳍上方形成所述半导体覆盖层和所述介电层。
14.一种形成鳍式场效应晶体管(FinFET)器件的方法,所述方法包括:
在衬底的PMOS区域中形成第一鳍;
在所述衬底的邻近于所述PMOS区域的NMOS区域中形成第二鳍;
在所述第一鳍和所述第二鳍上方形成硅覆盖层;
对所述硅覆盖层实施氮化处理;
在所述硅覆盖层上方形成第一介电材料;
在所述第一鳍和所述第二鳍之间以及所述第一鳍和所述第二鳍上方沉积第二介电材料,其中,所述第一介电材料位于所述硅覆盖层和所述第二介电材料之间;
实施热工艺以固化所述第二介电材料;
在所述热工艺之后,使所述第二介电材料凹进以暴露所述第一鳍的顶部和所述第二鳍的顶部;以及
在所述第一鳍上方形成第一栅极结构并且在所述第二鳍上方形成第二栅极结构。
15.根据权利要求14所述的方法,其中,形成所述硅覆盖层包括在所述第一鳍和所述第二鳍上方共形地形成所述硅覆盖层。
16.根据权利要求14所述的方法,其中,实施所述氮化处理包括用包含氨的气体处理所述硅覆盖层。
17.根据权利要求14所述的方法,其中,形成所述第一介电材料包括在所述硅覆盖层上方共形地形成氮化硅层,其中,实施所述热工艺将所述第一介电材料的顶层转化为氮氧化硅。
18.一种鳍式场效应晶体管(FinFET)器件,包括:
鳍,突出在隔离区域的上表面之上,所述隔离区域位于所述鳍的相对侧上;
硅覆盖层,位于所述鳍和所述隔离区域之间;
第一介电材料,位于所述硅覆盖层和所述隔离区域之间;以及
第二介电材料,位于所述第一介电材料和所述隔离区域之间并且与所述第一介电材料不同,所述第二介电材料包括所述第一介电材料的氧化物。
19.根据权利要求18所述的鳍式场效应晶体管器件,其中,所述鳍包括硅锗,其中,所述第一介电材料包括氮化硅,并且所述第二介电材料包括氮氧化硅。
20.根据权利要求18所述的鳍式场效应晶体管器件,还包括位于所述硅覆盖层和所述第一介电材料之间的氧化硅膜。
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