CN1094253C - 半导体装置之金属布线制造方法 - Google Patents

半导体装置之金属布线制造方法 Download PDF

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CN1094253C
CN1094253C CN971119074A CN97111907A CN1094253C CN 1094253 C CN1094253 C CN 1094253C CN 971119074 A CN971119074 A CN 971119074A CN 97111907 A CN97111907 A CN 97111907A CN 1094253 C CN1094253 C CN 1094253C
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barrier metal
metal level
metal layer
plasma treatment
sulphur hexafluoride
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CN1177203A (zh
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郑镇基
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

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Abstract

半导体装置之金属布线的制造方法被提供而且包括步骤：沉积一层障碍物金属层于绝缘薄膜之上，而且经过SF6等离子体处理；依序形成一层铝金属层、一层防止反射层以及光致抗蚀剂薄膜图案于该障碍物金属层的表面之上，以该图案当作蚀刻掩模蚀刻该防止反射层、该铝金属层以及该障碍物金属层而形成金属布线；并且去除该光致抗蚀剂薄膜图案，当硅球状体在铝金属层被沉积于其上时只生长一点点于该障碍物金属层之上的时候，该SF6等离子体处理在蚀刻期间不会留下任何残馀物于该绝缘薄膜之上。

Description

半导体装置之金属布线制造方法
一般而言，本发明系有关半导体装置之金属布线的制造方法，尤指在制造半导体装置之金属布线中使用六氟化硫(SF6)等离子体处理，藉以不会在绝缘层上留下任何导电物质的残馀物。
随着大的电阻，为半导体装置所使用之多晶硅层成为减小半导体装置之操作速度的动机，当作一个导电的通道，金属布线被使用来降低电阻。
为了对本发明之背景有较佳的了解，将配合图1及图2来说明用以制造半导体装置之金属布线的传统制程。
在图1及图2中显示用以制造半导体装置之金属布线而留下残馀物的传统制程步骤。
对于制造金属布线，如在图1中所示，首先以一层绝缘薄膜2覆盖于基板1之上，在该绝缘薄膜2之上依序沉积一层障碍物金属层3、一层铝金属层5以及一层防止反射薄膜6，其后，形成光致抗蚀剂图案7于该防止反射薄膜6之上。
通常，该障碍物金属层3系用例如钛或氮化钛薄膜来做的，该铝金属层5系用例如铝-硅-(Al-Si-Cu)来做的，而该防止反射薄膜6系用例如氮化钛薄膜来做的。
随着该光致抗蚀剂薄膜图案7当作掩模用，该防止反射薄膜6、铝金属层5以及障碍物金属层3依序被蚀刻而形成金属布线8，随之而后为该光致抗蚀剂薄膜图案的去除，如在图2中所显示，此时，该障碍物金属层3在该绝缘薄膜2的表面上留下残馀物3′，该残馀物3′致使成为介于邻近的金属布线8之间的桥梁而形成短路。
当由铝-硅-铜所做之铝金属层被沉积于该障碍物金属层3的表面之上时，硅球状体4生长于该障碍物金属层3之上，并且在该铝金属层5的蚀刻之后继续存在，当该下层的障碍物金属层3被蚀刻完毕时，该硅球状体也一起被去除，但部分的氨化钛继续存在。
因此，本发明之目的在于克服在公知技术中所遭遇的上述问题并且提供半导体装置之金属布线的制造方法，该方法藉减少在经由六氟化硫(SF6)等离子体处理之铝金属层的沉积时于障碍物金属层上之硅球状体的生长来防止残馀物的形成。
根据本发明，藉半导体装置之金属布线制造方法的提供可以达成上述之目的，包括步骤：沉积一层障碍物金属层于绝缘薄膜之上并且使该障碍物金属层经过六氟化硫(SF6)等离子体处理；依序形成一层铝金属层、一层防止反射层以及光致抗蚀剂薄膜图案于该障碍物金属层的表面之上；以该光致抗蚀剂薄膜图案当作蚀刻掩模用来蚀刻该防止反射层～铝金属层以及障碍物金属层而形成金属布线；以及去除该光致抗蚀剂薄膜图案。
本发明之其他的目的及观点将从下列之实施例的说明并参考伴随的图形而变得明显，其中：
图1及图2系显示用以制造由一层障碍物金属层、一层铝金属层以及一层防止反射层所构成之金属布线的传统方法之横断面示意图；及
图3到图6系显示根据本发明之用以制造由一层障碍物金属层、一层铝金属层以及一层防止反射层所构成之金属层线的方法之横断面示意图。
参考伴随的图形最有助于了解本发明之较佳实施例的应用，其中相同的参考数字个别被用于相同及相当的部分。
根据本发明图3到图6，显示用以制造半导体装置之金属布线的制程步骤。
首先，如在图3中所显示，以一层绝缘薄膜2，例如一层氧化物薄膜覆盖于基板1之上，而后，以一层障碍物金属层3，例如一层钛或氮化钛薄膜于该绝缘薄膜2之上。
图4系取自在经过以六氟化硫(SF6)等离子体处理该障碍物金属层3的横断面图，对于该六氟化硫(SF6)等离子体处理法而言，在压力为2.0-20.0毫乇(mtorr)的情形下，在电源电力为500-2000瓦及偏压电力为0-100瓦时使用20-100SCCM的六氟化硫(SF6)。
图5系取自在依序沉积一层铝金属层5及一层防止反射层6，随之而后形成光致抗蚀剂图案7之后的横断面图，该铝金属层5系用铝-硅-铜(Al-Si-Cu)来做的，而该防止反射薄膜系用氮化钛来做的。
其次，使用该光致抗蚀剂薄膜图案7当作掩模，该防止反射薄膜6、铝金属层5以及障碍物金属层3依序被蚀刻而形成金属布线8，随之而后为该光致抗蚀剂图案7的去除，如在图6中所显示。
如在上文中所述，本发明之特色在于，随着钛或氮化钛层之障碍物金属层的沉积之后，实施六氟化硫(SF6)等离子体处理，当硅球状体3在铝-硅-铜(Al-Si-Cu)的铝金属层5被沉积于其上时只生长一点点于该障碍物金属层3之上的时候，此处理在蚀刻期间不会留下任何残馀物于该绝缘薄膜2之上。
本发明已经以图示说明的方式来叙述，而且将可了解，所使用的专用术语系意欲说明其本质而非限制性。
本发明之许多修改及变型可能系监于上述之教旨，因此将可了解到，在附加之权利要求的范围之内，本发明可以用除了那些被特别说明之方式的方式来实施。

Claims (6)

1.一种半导体装置之金属布线的制造方法，包括步骤：
沉积一层障碍物金属层于绝缘薄膜之上，而且使该障碍物金属层经过六氟化硫(SF6)等离子体处理；
依序形成一层铝金属层、一层防止反射层以及光致抗蚀剂薄膜图案于该障碍物金属层的表面之上；
以该光致抗蚀剂薄膜图案当作蚀刻掩模，蚀刻该防止反射层、该铝金属层以及该障碍物金属层而形成金属布线，并且去除该光致抗蚀剂薄膜图案。
2.如权利要求1的方法，其中该障碍物金属层系以钛或氮化钛来做的。
3.如权利要求1的方法，其中该铝金属层系以铝-硅-铜(Al-Si-Cu)来做的。
4.如权利要求1的方法，其中该使用六氟化硫(SF6)以20-100SCCM的速率来实施该六氟化硫(SF6)等离子体处理。
5.如权利要求1或4的方法，其中在电源电力为500-2000瓦以及偏压电力为0-100瓦时实施该六氟化硫(SF6)等离子体处理。
6.如权利要求1或4的方法，其中在压力为2.0-20.0毫乇(mTorr)时实施该六氟化硫(SF6)等离子体处理。
CN971119074A 1996-06-27 1997-06-25 半导体装置之金属布线制造方法 Expired - Fee Related CN1094253C (zh)

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Publication number Priority date Publication date Assignee Title
CN101192567B (zh) * 2006-11-27 2010-06-16 东部高科股份有限公司 在半导体器件中形成金属布线的方法和装置

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US5950107A (en) * 1996-12-17 1999-09-07 Intel Corporation In-situ pre-ILD deposition treatment to improve ILD to metal adhesion
KR100278652B1 (ko) * 1998-01-13 2001-02-01 윤종용 반도체장치의텅스텐패턴형성방법
CN100541720C (zh) * 2002-06-27 2009-09-16 东京毅力科创株式会社 等离子体处理方法
TWI292933B (en) * 2004-03-17 2008-01-21 Imec Inter Uni Micro Electr Method of manufacturing a semiconductor device having damascene structures with air gaps
CN103887230B (zh) * 2014-03-28 2016-08-31 中国电子科技集团公司第二十四研究所 等离子体刻蚀AlSi的方法

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KR960001601B1 (ko) * 1992-01-23 1996-02-02 삼성전자주식회사 반도체 장치의 접촉구 매몰방법 및 구조
JP2751820B2 (ja) * 1994-02-28 1998-05-18 日本電気株式会社 半導体装置の製造方法
US5430328A (en) * 1994-05-31 1995-07-04 United Microelectronics Corporation Process for self-align contact
US5554254A (en) * 1995-03-16 1996-09-10 Taiwan Semiconductor Manufacturing Company Post contact layer etch back process which prevents precipitate formation
US5554563A (en) * 1995-04-04 1996-09-10 Taiwan Semiconductor Manufacturing Company In situ hot bake treatment that prevents precipitate formation after a contact layer etch back step

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101192567B (zh) * 2006-11-27 2010-06-16 东部高科股份有限公司 在半导体器件中形成金属布线的方法和装置

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US5856238A (en) 1999-01-05
CN1177203A (zh) 1998-03-25
TW324110B (en) 1998-01-01

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