CN109413836B - Circuit board and preparation method thereof - Google Patents
Circuit board and preparation method thereof Download PDFInfo
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- CN109413836B CN109413836B CN201710696697.4A CN201710696697A CN109413836B CN 109413836 B CN109413836 B CN 109413836B CN 201710696697 A CN201710696697 A CN 201710696697A CN 109413836 B CN109413836 B CN 109413836B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
- H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
Abstract
A circuit board comprises a first substrate, a heat-conducting base material and a second substrate stacked in sequence, wherein a through cavity is formed on the first substrate, the cavity is provided with electronic elements, the first substrate and the second substrate are respectively provided with a first conductive circuit layer and a second conductive circuit layer, the first conductive circuit layer and the second conductive circuit layer are respectively covered with a first dielectric layer and a second dielectric layer, a third conductive circuit layer and a fourth conductive circuit layer are respectively formed on the first dielectric layer and the second dielectric layer, a first solder mask layer and a second solder mask layer are respectively formed on the third conductive circuit layer and the fourth conductive circuit layer, a heat conduction hole is formed at least from one of the first solder mask layer and the second solder mask layer, the heat conduction hole exposes the heat conduction substrate, and the heat conduction hole is filled with heat conduction materials, so that at least one heat conduction part is formed.
Description
Technical Field
The invention relates to a circuit board and a preparation method thereof.
Background
In recent years, electronic products are widely used in daily work and life, and light, thin and small electronic products are increasingly popular. The circuit board is used as a main component of the electronic product, and occupies a large space of the electronic product, so that the volume of the circuit board influences the volume of the electronic product to a great extent, and the large-volume circuit board is difficult to conform to the trend of lightness, thinness, shortness and smallness of the electronic product.
The passive elements (such as resistors, capacitors and the like) of the circuit board are embedded in the circuit substrate, so that the overall thickness of the circuit board is reduced, and the thickness of the electronic product is reduced. However, heat generated during the operation of the embedded passive components is difficult to dissipate, which may cause thermal expansion of the core layer of the circuit board, thereby damaging the circuit board.
Disclosure of Invention
In view of the above, it is desirable to provide a circuit board capable of solving the above problems.
In addition, a preparation method of the circuit board is also needed to be provided.
The invention provides a preparation method of a circuit board, which comprises the following steps: providing a circuit substrate, wherein the circuit substrate comprises a first single-sided board, a heat-conducting base material and a second single-sided board which are sequentially pressed, a cavity penetrates through the first single-sided board, the first single-sided board comprises a first copper foil which is far away from the heat-conducting base material, and the second single-sided board comprises a second copper foil which is far away from the heat-conducting base material; electroplating the first copper foil and the second copper foil to form a first electroplated copper layer; etching the first electroplated copper layers and the first copper foil and the second copper foil positioned between the first electroplated copper layers to obtain a first conductive circuit layer and a second conductive circuit layer; placing an electronic element in the cavity, and pressing a first dielectric layer and a second dielectric layer on the first conductive circuit layer and the second conductive circuit layer respectively; forming a third conductive circuit layer and a fourth conductive circuit layer on the first dielectric layer and the second dielectric layer respectively, wherein the third conductive circuit layer is electrically connected with the first conductive circuit layer and the electronic element, and the fourth conductive circuit layer is electrically connected with the second conductive circuit layer; forming a first solder mask layer and a second solder mask layer on the third conductive circuit layer and the fourth conductive circuit layer respectively; and at least one heat conduction hole is formed in one of the first solder mask layer and the second solder mask layer and penetrates through the first solder mask layer and the first dielectric layer or the second solder mask layer and the second dielectric layer, so that the heat conduction base material is exposed, and then each heat conduction hole is filled with a heat conduction material, so that at least one heat conduction part in heat conduction connection with the heat conduction base material is formed, and the circuit board is obtained.
The invention also provides a circuit board, which comprises a first substrate, a heat-conducting base material and a second substrate which are sequentially overlapped, wherein a through cavity is formed on the first substrate, an electronic element is arranged in the cavity, a first conducting circuit layer and a second conducting circuit layer are respectively formed on the first substrate and the second substrate, a first dielectric layer and a second dielectric layer are respectively covered on the first conducting circuit layer and the second conducting circuit layer, a third conducting circuit layer and a fourth conducting circuit layer are respectively formed on the first dielectric layer and the second dielectric layer, the third conducting circuit layer is electrically connected with the first conducting circuit layer and the electronic element, the fourth conducting circuit layer is electrically connected with the second conducting circuit layer, a first solder mask layer and a second solder mask layer are respectively formed on the third conducting circuit layer and the fourth conducting circuit layer, at least one of the first welding-proof layer and the second welding-proof layer is provided with a heat conduction hole, the heat conduction hole penetrates through the first welding-proof layer and the first dielectric layer or the second welding-proof layer and the second dielectric layer so as to expose the heat conduction substrate, and the heat conduction hole is filled with heat conduction materials so as to form at least one heat conduction part.
In the above circuit board, heat generated by the electronic component may be dissipated to an external environment through the heat conductive base material and the heat conductive portion, and the heat may be buffered when reaching the heat conductive base material, thereby preventing thermal expansion of the core layer.
Drawings
Fig. 1 is a schematic structural diagram of a first single-sided board, a second single-sided board and a heat-conducting substrate used in a method for manufacturing a circuit board according to a preferred embodiment of the invention.
Fig. 2 is a schematic structural diagram of the circuit substrate obtained after laminating the first single-sided board, the second single-sided board and the heat-conducting base material shown in fig. 1.
Fig. 3 is a schematic structural view of the circuit substrate shown in fig. 2 after an opening is formed therein and a first conductive seed layer is formed thereon.
FIG. 4 is a schematic diagram of the circuit substrate shown in FIG. 3 after both sides are covered with a patterned photoresist layer.
FIG. 5 is a schematic view of the structure of FIG. 4 after copper is electroplated in the openings of the patterned photoresist layer to form a first electroplated copper layer.
Fig. 6 is a schematic structural diagram illustrating the first electroplated copper layer shown in fig. 5 after etching to obtain a first conductive circuit layer and a second conductive circuit layer.
Fig. 7 is a schematic structural view of the first single-sided board shown in fig. 6 after an electronic device is placed in the cavity and the first dielectric layer and the second dielectric layer are laminated.
Fig. 8 is a schematic structural diagram of the first dielectric layer and the second dielectric layer shown in fig. 7 after a via hole is formed therein.
Fig. 9 is a schematic diagram of the structure after forming a second conductive seed layer in the via shown in fig. 8 and electroplating copper on the first dielectric layer and the second dielectric layer to form a second electroplated copper layer.
Fig. 10 is a schematic structural diagram illustrating the second electroplated copper layer shown in fig. 9 after etching to obtain a third conductive circuit layer and a fourth conductive circuit layer.
Fig. 11 is a schematic structural diagram illustrating a first solder mask layer and a second solder mask layer formed on the third conductive trace layer and the fourth conductive trace layer shown in fig. 10.
Fig. 12 is a schematic structural view of the first solder mask shown in fig. 11 after thermal vias are formed in the first solder mask and thermal conductive materials are filled in the first solder mask to form thermal conductive portions.
Fig. 13 is a schematic structural diagram of the first solder mask layer and the second solder mask layer shown in fig. 11 after forming heat conduction holes and filling heat conduction materials to form heat conduction portions.
Fig. 14 is a schematic structural view of a circuit board obtained by covering the end of the heat-conducting portion shown in fig. 12 with a heat sink.
Fig. 15 is a schematic diagram illustrating a structure of the circuit substrate shown in fig. 2 after forming an opening therein, forming a first conductive seed layer, and covering a photoresist on the cavity of the first single panel in another preferred embodiment.
Fig. 16 is a schematic view of the structure of another circuit board obtained on the circuit substrate shown in fig. 15.
Description of the main elements
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
Referring to fig. 1 to 14, a first embodiment of the invention provides a method for manufacturing a circuit board 100, including the following steps:
referring to fig. 1, a first single-sided board 11, a second single-sided board 12 and a heat-conducting substrate 13 are provided. The first single-sided board 11 includes a first substrate 110 and a first copper foil 111 bonded to the first substrate 110, and a cavity 112 penetrates through the first substrate 110 and the first copper foil 111. The second single-sided board 12 includes a second substrate 120 and a second copper foil 121 bonded to the second substrate 120. The first copper foil 111 and the second copper foil 121 both have a thickness d 1.
In the present embodiment, the material of the heat conductive base material 13 is a heat conductive resin composition having good electrical insulation, and more specifically, the material of the heat conductive base material 13 may be at least one selected from a heat conductive resin composition filled with a nanocarbon material, an epoxy resin heat conductive resin composition, a polycarbonate-based heat conductive resin composition, an acrylic heat conductive resin composition, and the like. The thermal conductivity coefficient of the material of the thermal conductive substrate 13 is K1.
Referring to fig. 2, the first single-sided board 11 and the second single-sided board 12 are respectively pressed on two opposite surfaces of the heat-conducting substrate 13, so that the first copper foil 111 and the second copper foil 121 are respectively disposed away from the heat-conducting substrate 13, thereby forming a circuit board 20.
Referring to fig. 3, at least one opening 21 is formed in the circuit substrate 20 except the cavity 112 to penetrate through the first single-sided board 11, the second single-sided board 12 and the heat-conducting substrate 13, and a first conductive seed layer 22 is formed on an inner wall of each opening 21 and an inner wall of the cavity 112.
In the present embodiment, the opening 21 may be formed by laser drilling. In the present embodiment, the first conductive seed layer 22 may be formed by electroless plating or sputtering.
Referring to fig. 4, a patterned photoresist layer 30 is respectively covered on the first copper foil 111 and the second copper foil 121, and an opening (not shown) defined by the patterned photoresist layer 30 is used for exposing a partial region of the first copper foil 111 and the second copper foil 121, the opening 21 formed with the first conductive seed layer 22, and the cavity 112 formed with the first conductive seed layer 22.
In the present embodiment, the patterned photoresist layer 30 is formed by an exposure and development process to form a desired pattern. More specifically, the pattern photoresist layer 30 is a dry film.
Referring to fig. 5, copper is electroplated on the exposed areas of the first copper foil 111 and the second copper foil 121, so as to form a first electroplated copper layer 40 on the first copper foil 111 and the second copper foil 121, respectively. A portion of the first copper electroplated layer 40 is filled in the opening 21 formed with the first conductive seed layer 22 to form a first conductive via 23 for electrically connecting the two first copper electroplated layers 40, and a portion of the first copper electroplated layer 40 is further formed in the cavity 112.
The thickness of the first electroplated copper layer 40 is d2, and d2 is more than or equal to d 1.
Referring to fig. 6, the patterned photoresist layer 30 is removed, and the first electroplated copper layer 40, the first copper foil 111 and the second copper foil 121 between the first electroplated copper layer 40 are etched by exposure and development techniques to obtain a first conductive trace layer 51 and a second conductive trace layer 52.
The thicknesses of the first conductive trace layer 51 and the second conductive trace layer 52 are d 2. The first electroplated copper layer 40, which is located in the cavity 112 after etching, has a thickness d2-d 1.
Step seven, referring to fig. 7, an electronic component 63 is disposed on the first copper electroplating layer 40 in the cavity 112, wherein the electronic component 63 has two contact pads 630 away from the first copper electroplating layer 40 in the cavity 112. Then, a first dielectric layer 61 and a second dielectric layer 62 are respectively pressed on the first conductive trace layer 51 and the second conductive trace layer 52, and the first dielectric layer 61 is made to flow and fill the gap between the first conductive trace layer 51 and the electronic component 63, and the second dielectric layer 62 is made to flow and fill the gap between the second conductive trace layers 52. The electronic component 63 may be a resistor or a capacitor, etc.
In the present embodiment, the material of the first dielectric layer 61 and the second dielectric layer 62 is a resin, and the resin may be at least one selected from polypropylene, epoxy resin, polyurethane, phenol resin, urea resin, melamine-formaldehyde resin, unsaturated resin, polyimide, and the like.
In step eight, referring to fig. 8, a through hole 610 is opened in the first dielectric layer 61 to expose the first conductive trace layer 51 and the contact pad 630 of the electronic component 63, and a through hole 620 is opened in the second dielectric layer 62 to expose the second conductive trace layer 52.
Step nine, referring to fig. 9, a second conductive seed layer 64 is formed on the inner wall of each of the through holes 610, 620, and then copper is electroplated on the first dielectric layer 61 and the second dielectric layer 62, so as to form a second copper electroplating layer 65 on the first dielectric layer 61 and the second dielectric layer 62, respectively, and a portion of the second copper electroplating layer 65 is filled in each of the through holes 610, 620 formed with the second conductive seed layer 64 to form a second conductive hole 66.
Referring to fig. 10, a desired conductive trace is etched in the second electroplated copper layer 65 by an exposure and development technique, so as to form a third conductive trace layer 71 and a fourth conductive trace layer 72 on the first dielectric layer 61 and the second dielectric layer 62, respectively. The third conductive trace layer 71 is electrically connected to the first conductive trace layer 51 and the contact pad 630 of the electronic component 63 through the second conductive via 66. The fourth conductive trace layer 72 is electrically connected to the second conductive trace layer 52 through the second conductive via 66.
In this embodiment, the through holes 610 and 620 may be formed by laser drilling.
Referring to fig. 11, a first solder mask 81 and a second solder mask 82 are formed on the third conductive trace layer 71 and the fourth conductive trace layer 72, respectively.
In this embodiment, the first solder mask layer 81 and the second solder mask layer 82 are ink layers or dry films.
Step twelve, referring to fig. 12 and 13, a heat conduction hole 91 is formed at least from one of the first solder mask layer 81 and the second solder mask layer 82, and the heat conduction hole 91 penetrates through the first solder mask layer 81, the first dielectric layer 61 and the first substrate 110, or penetrates through the second solder mask layer 82, the second dielectric layer 62 and the second substrate 120, thereby exposing the heat conduction base material 13. Then, each heat conduction hole 91 is filled with a heat conductive material, thereby forming at least one heat conduction portion 90 in heat conductive connection with the heat conductive base material 13.
In the present embodiment, two heat conduction holes 91 are opened from the first solder resist layer 81 (i.e., the heat conduction holes 91 are located on the same side, as shown in fig. 12). The heat conducting material filled in the heat conducting part 90 is similar to the heat conducting base material in material, and the heat conducting coefficient is K2, and K2 is not less than K1.
In another embodiment, one heat conduction hole 91 is formed from each of the first solder mask layer 81 and the second solder mask layer 82 (i.e., the heat conduction holes 91 are located on different sides, as shown in fig. 13), and the heat conduction holes 91 formed from the first solder mask layer 81 and the heat conduction holes 91 formed from the second solder mask layer 82 are alternately arranged.
The projection area of the electronic component 63 on the heat-conducting substrate 13 is a1, the contact area between the two heat-conducting portions 90 and the heat-conducting substrate 13 is a2, and a2 is equal to or greater than a 1.
Step thirteen, referring to fig. 14, a heat sink 92 covers an end of each heat conducting portion 90 away from the heat conducting substrate 13, so that the heat sink 92 is thermally connected to the heat conducting substrate 13 through the heat conducting portion 90, thereby obtaining the circuit board 100. When the heat conduction holes 91 are opened from the first solder mask layer 81, the end of each heat conduction hole 91 can be covered by a single heat sink 92.
In the present embodiment, the heat dissipation sheet 92 has a thermal conductivity of K3, K3 ≧ K2. The heat sink 92 is made of metal, and more specifically, the heat sink 92 is made of at least one material selected from gold, silver, copper, lead, nickel, tin, and the like.
Referring to fig. 14, the first embodiment of the invention further provides a circuit board 100, wherein the circuit board 100 includes a first substrate 110, a heat conductive substrate 13 and a second substrate 120 stacked in sequence. A cavity 112 is formed through the first substrate 110. At least one first conductive via 23 penetrates the first substrate 110, the second substrate 120 and the heat conductive base material 13. The inner wall of each of the first conductive vias 23 and the inner wall of the cavity 112 include a first conductive seed layer 22.
A first conductive trace layer 51 and a second conductive trace layer 52 are formed on the first substrate 110 and the second substrate 120, respectively. The first conductive trace layer 51 and the second conductive trace layer 52 are electrically connected through the first conductive via 23. The first conductive trace layer 51 includes a first copper foil 111 formed on the first substrate 110 and a first copper electroplated layer 40 formed on the first copper foil 111, the first copper electroplated layer 40 further formed on the first conductive seed layer 22 of the cavity 112. The second conductive trace layer 52 includes a second copper foil 121 formed on the second substrate 120 and a first copper electroplating layer 40 formed on the second copper foil 121. The thicknesses of the first conductive trace layer 51 and the second conductive trace layer 52 are d 2. The first electroplated copper layer 40 located in the cavity 112 has a thickness d2-d 1.
An electronic component 63 is disposed on the first electroplated copper layer 40 in the cavity 112, and the electronic component 63 has two contact pads 630 located away from the first electroplated copper layer 40 in the cavity 112.
The first conductive trace layer 51 and the second conductive trace layer 52 are covered with a first dielectric layer 61 and a second dielectric layer 62, respectively, the first dielectric layer 61 fills the gap between the first conductive trace layer 51 and the electronic component 63, and the second dielectric layer 62 fills the gap between the second conductive trace layer 52.
A second conductive via 66 is formed in the first dielectric layer 61 for exposing the first conductive trace layer 51 and a contact pad 630 of the electronic component 63. A second conductive via 66 is formed in the second dielectric layer 62 to expose the second conductive trace layer 52. The inner wall of each second conductive via 66 includes a second conductive seed layer 630.
A third conductive trace layer 71 and a fourth conductive trace layer 72 are formed on the first dielectric layer 61 and the second dielectric layer 62, respectively. The third conductive trace layer 71 is electrically connected to the first conductive trace layer 51 and the contact pad 630 of the electronic component 63 through the second conductive via 66. The fourth conductive trace layer 72 is electrically connected to the second conductive trace layer 52 through the second conductive via 66.
A first solder mask 81 and a second solder mask 82 are formed on the third conductive trace layer 71 and the fourth conductive trace layer 72, respectively. At least one of the first solder mask layer 81 and the second solder mask layer 82 is provided with a heat conduction hole 91, the heat conduction hole 91 penetrates through the first solder mask layer 81, the first dielectric layer 61 and the first substrate 110, or penetrates through the second solder mask layer 82, the second dielectric layer 62 and the second substrate 120, so as to expose the heat conduction substrate 13, and the heat conduction hole 91 is filled with a heat conduction material, so as to form at least one heat conduction part 90.
The end of each heat conducting portion 90 away from the heat conducting substrate 13 is covered with a heat sink 92, and the heat sink 92 is connected to the heat conducting substrate 13 through the heat conducting portion 90 in a heat conducting manner.
A second embodiment of the present invention provides a method for manufacturing a circuit board 100', which is different from the method for manufacturing the circuit board 100 of the first embodiment, in that the first conductive seed layer 22 and the first electroplated copper layer 40 are not formed in the cavity 112, specifically, in the third step: referring to fig. 15, after at least one opening 21 is formed in the circuit substrate 20 except the cavity 112 to penetrate the single-sided board 11, the second single-sided board 12 and the heat conductive substrate 13, a photoresist 113 is covered on the cavity 112, and a first conductive seed layer 22 is formed on an inner wall of each opening 21. The photoresist 113 may be used to prevent copper deposition on the inner walls of the cavity 112 during the copper electroplating process.
Referring to fig. 16, a circuit board 100' according to a second embodiment of the present invention is different from the circuit board 100 in that the first conductive seed layer 22 and the first electroplated copper layer 40 are not formed in the cavity 112, i.e., the electronic component 63 directly contacts the bottom of the cavity 112.
Since the electronic component 63 is embedded in the cavity 112, the thickness of the whole product can be reduced. The heat generated by the electronic component 63 can be dissipated to the external environment through the heat conductive substrate 13, the heat conductive portion 90 and the heat sink 92 in sequence. Since the heat can be buffered when it reaches the heat conductive base material 13, thermal expansion of the core layer is prevented.
It is understood that various other changes and modifications may be made by those skilled in the art based on the technical idea of the present invention, and all such changes and modifications should fall within the protective scope of the claims of the present invention.
Claims (14)
1. A method of making a circuit board, comprising:
providing a circuit substrate, wherein the circuit substrate comprises a first single-sided board, a heat-conducting base material and a second single-sided board which are sequentially pressed, a cavity penetrates through the first single-sided board, the first single-sided board comprises a first copper foil which is far away from the heat-conducting base material, and the second single-sided board comprises a second copper foil which is far away from the heat-conducting base material;
electroplating the first copper foil and the second copper foil to form a first electroplated copper layer;
etching the first electroplated copper layers and the first copper foil and the second copper foil positioned between the first electroplated copper layers to obtain a first conductive circuit layer and a second conductive circuit layer;
placing an electronic element in the cavity, and pressing a first dielectric layer and a second dielectric layer on the first conductive circuit layer and the second conductive circuit layer respectively;
forming a third conductive circuit layer and a fourth conductive circuit layer on the first dielectric layer and the second dielectric layer respectively, wherein the third conductive circuit layer is electrically connected with the first conductive circuit layer and the electronic element, and the fourth conductive circuit layer is electrically connected with the second conductive circuit layer;
forming a first solder mask layer and a second solder mask layer on the third conductive circuit layer and the fourth conductive circuit layer respectively; and
and at least one heat conduction hole is formed in one of the first solder mask layer and the second solder mask layer and penetrates through the first solder mask layer and the first dielectric layer or the second solder mask layer and the second dielectric layer, so that the heat conduction substrate is exposed, and then heat conduction materials are filled in each heat conduction hole, so that at least one heat conduction part in heat conduction connection with the heat conduction substrate is formed, and the circuit board is obtained.
2. The method for manufacturing a circuit board according to claim 1, further comprising:
and covering a radiating fin at the end part of each heat conduction part far away from the heat conduction base material, so that the radiating fin is in heat conduction connection with the heat conduction base material through the heat conduction part.
3. The method of claim 1, wherein the thermal conductive material of the thermal conductive portion and the thermal conductive substrate are at least one selected from a group consisting of a nanocarbon material filled thermal conductive resin composition, an epoxy resin thermal conductive resin composition, a polycarbonate resin thermal conductive resin composition and an acrylic resin thermal conductive resin composition, the thermal conductive substrate has a thermal conductivity of K1, the thermal conductive material of the thermal conductive portion has a thermal conductivity of K2, and K2 is equal to or greater than K1.
4. The method of claim 1, wherein the step of "forming a first electroplated copper layer on the first copper foil and the second copper foil by electroplating" further comprises:
at least one hole penetrating through the first single-sided board, the second single-sided board and the heat-conducting base material is formed in the area of the circuit substrate except the cavity; and
a first conductive seed layer is formed on the inner wall of each opening and the inner wall of the cavity.
5. The method of claim 4, wherein the step of "forming a first electroplated copper layer on the first copper foil and the second copper foil by electroplating" further comprises:
covering a pattern photoresist layer on the first copper foil and the second copper foil respectively, wherein an opening defined by the pattern photoresist layer is used for exposing partial areas of the first copper foil and the second copper foil, the opening formed with the first conductive seed crystal layer and the cavity formed with the first conductive seed crystal layer;
electroplating copper on the exposed areas of the first copper foil and the second copper foil so as to form the first copper electroplating layers on the first copper foil and the second copper foil respectively, wherein part of the first copper electroplating layers are filled in the opening formed with the first conductive seed layer so as to form a first conductive hole for electrically connecting the two first copper electroplating layers, and part of the first copper electroplating layers are further formed in the cavity;
and removing the pattern photoresist layer.
6. The method of claim 4, wherein the step of "forming a first electroplated copper layer on the first copper foil and the second copper foil by electroplating" further comprises:
covering a photoresist on the cavity;
covering a pattern photoresist layer on the first copper foil and the second copper foil respectively, wherein an opening defined by the pattern photoresist layer is used for exposing partial areas of the first copper foil and the second copper foil and the opening formed with the first conductive seed crystal layer;
electroplating copper on the exposed areas of the first copper foil and the second copper foil so as to form the first copper electroplating layers on the first copper foil and the second copper foil respectively, wherein part of the first copper electroplating layers are filled in the opening formed with the first conductive seed layer so as to form a first conductive hole for electrically connecting the two first copper electroplating layers;
and removing the photoresist and the pattern photoresist layer.
7. The method for manufacturing a circuit board according to claim 5 or 6, wherein the step of forming a third conductive trace layer and a fourth conductive trace layer on the first dielectric layer and the second dielectric layer, respectively, further comprises:
forming a through hole in the first dielectric layer to expose the first conductive trace layer and the electronic element, and forming a through hole in the second dielectric layer to expose the second conductive trace layer;
forming a second conductive seed layer on the inner wall of each through hole, and electroplating copper on the first dielectric layer and the second dielectric layer, so as to form a second copper electroplating layer on the first dielectric layer and the second dielectric layer respectively, wherein part of the second copper electroplating layer is filled in each through hole formed with the second conductive seed layer to form a second conductive hole;
and etching a required conductive circuit in the second electroplated copper layer by adopting an exposure and development technology, so as to form a third conductive circuit layer and a fourth conductive circuit layer on the first dielectric layer and the second dielectric layer respectively, wherein the third conductive circuit layer is electrically connected with the first conductive circuit layer and the electronic element through the second conductive hole, and the fourth conductive circuit layer is electrically connected with the second conductive circuit layer through the second conductive hole.
8. The method of claim 1, wherein the projected area of the electronic component on the heat-conducting substrate is A1, the contact area between any two heat-conducting parts and the heat-conducting substrate is A2, and A2 is equal to or greater than A1.
9. A circuit board comprises a first substrate, a heat-conducting base material and a second substrate which are sequentially stacked, wherein a through cavity is formed on the first substrate, an electronic element is arranged in the cavity, a first conducting circuit layer and a second conducting circuit layer are respectively formed on the first substrate and the second substrate, a first dielectric layer and a second dielectric layer are respectively covered on the first conducting circuit layer and the second conducting circuit layer, a third conducting circuit layer and a fourth conducting circuit layer are respectively formed on the first dielectric layer and the second dielectric layer, the third conducting circuit layer is electrically connected with the first conducting circuit layer and the electronic element, the fourth conducting circuit layer is electrically connected with the second conducting circuit layer, a first solder mask layer and a second solder mask layer are respectively formed on the third conducting circuit layer and the fourth conducting circuit layer, at least one of the first welding-proof layer and the second welding-proof layer is provided with a heat conduction hole, the heat conduction hole penetrates through the first welding-proof layer and the first dielectric layer or the second welding-proof layer and the second dielectric layer so as to expose the heat conduction substrate, and the heat conduction hole is filled with heat conduction materials so as to form at least one heat conduction part.
10. The circuit board of claim 9, wherein an end of each thermal conductive portion remote from the thermal conductive substrate is covered with a heat sink, the heat sink being thermally conductively connected to the thermal conductive substrate through the thermal conductive portion.
11. The circuit board of claim 9, wherein at least one first conductive via extends through the first substrate, the second substrate and the thermally conductive substrate, an inner wall of each first conductive via includes a first conductive seed layer, and the first conductive trace layer and the second conductive trace layer are electrically connected through the first conductive via.
12. The circuit board of claim 11, wherein the first conductive trace layer comprises a first copper foil formed on the first substrate and a first electroplated copper layer formed on the first copper foil, and the second conductive trace layer comprises a second copper foil formed on the second substrate and a first electroplated copper layer formed on the second copper foil.
13. The circuit board of claim 12, wherein the inner wall of the cavity is also formed with the first conductive seed layer, and the first electroplated copper layer is further formed on the first conductive seed layer of the cavity such that the electronic component is located on the first electroplated copper layer in the cavity.
14. The circuit board of claim 11, wherein the first dielectric layer has second conductive vias formed therein for exposing the first conductive trace layer and the electronic component, the second dielectric layer has second conductive vias formed therein for exposing the second conductive trace layer, each of the second conductive vias has a second conductive seed layer on an inner wall thereof, the third conductive trace layer is electrically connected to the first conductive trace layer and the electronic component through the second conductive vias, and the fourth conductive trace layer is electrically connected to the second conductive trace layer through the second conductive vias.
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| CN201710696697.4A CN109413836B (en) | 2017-08-15 | 2017-08-15 | Circuit board and preparation method thereof |
| TW106128451A TWI658761B (en) | 2017-08-15 | 2017-08-22 | Circuit board and method for making the same |
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| CN201710696697.4A CN109413836B (en) | 2017-08-15 | 2017-08-15 | Circuit board and preparation method thereof |
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|---|---|---|---|---|
| US11545412B2 (en) | 2018-03-20 | 2023-01-03 | Unimicron Technology Corp. | Package structure and manufacturing method thereof |
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Also Published As
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| TW201911984A (en) | 2019-03-16 |
| CN109413836A (en) | 2019-03-01 |
| TWI658761B (en) | 2019-05-01 |
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