CN109411422A - 具有散热结构的晶圆封装 - Google Patents

具有散热结构的晶圆封装 Download PDF

Info

Publication number
CN109411422A
CN109411422A CN201811034100.0A CN201811034100A CN109411422A CN 109411422 A CN109411422 A CN 109411422A CN 201811034100 A CN201811034100 A CN 201811034100A CN 109411422 A CN109411422 A CN 109411422A
Authority
CN
China
Prior art keywords
solder mask
heat
conducting layer
metal heat
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
CN201811034100.0A
Other languages
English (en)
Inventor
不公告发明人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lu Weizheng
Original Assignee
Lu Weizheng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lu Weizheng filed Critical Lu Weizheng
Priority to CN201811034100.0A priority Critical patent/CN109411422A/zh
Publication of CN109411422A publication Critical patent/CN109411422A/zh
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明提供了一种具有散热结构的晶圆封装，包括：半导体衬底，具有相对的上表面和下表面；位于所述上表面的多个焊盘；位于所述多个焊盘上的多个焊球；覆盖所述上表面的阻焊层，所述阻焊层漏出所述多个焊球并且为覆盖所述上表面的边缘位置；环绕所述阻焊层的金属导热层，所述金属导热层仅位于所述上表面的边缘位置；位于所述下表面的散热层；以及连接所述金属导热层和所述散热层的多个导热通孔；所述金属导热层的厚度小于所述阻焊层的厚度。

Description

具有散热结构的晶圆封装
技术领域
本发明涉及一种半导体封装件，尤指一种具有散热结构的晶圆封装结构。
背景技术
利用封装技术将电子元件的体积减至最小并提高产品的集成度(Integration)，是制造电子产品的趋势。同时，基于现今电子产品的功能需求，在产品内的有限空间必须设置最多的电子元件，因此使电子产品内供设置电子元件的位置的大小相当于电子元件的尺寸。因此，电子元件之外观公差大小亦成为需要控管的项目。
以目前35mm×35mm尺寸的半导体封装件为例，该半导体封装件的平面单边公差不得大于0.2mm，亦即，该半导体封装的外距介于37.98mm至35.02mm之间；而若为更小的半导体封装件，甚至会到正负0.1mm左右。所以，如果要用人力检查半导体封装件的基板的边缘位置实在困难，所以现在普遍导入自动检查机进行检查。
然而，在应用自动检查机进行前述半导体封装件时，会发生误判的情况，而其原因在于一般托盘多为黑色或深色，而半导体封装件表面的拒焊层也是深色，使得影像传感器常无法分辨出半导体封装件的基板的边缘界限，因此导致误判。
同时，由于静电放电(Electrostatic Discharge，ESD)会产生烧毁、劣化半导体金属层或发生潜在性失效等，所以，就电子元件而言必须相当注重静电防护功能。
最后，由于集成度的不断提升，高密度器件的晶圆衬底上将产生大量的热，当热量过大，温度过高，就会导致器件的失效，因而，封装的散热性能也是必须考虑的问题。
发明内容
基于解决上述封装中的问题，本发明提供了一种具有散热结构的晶圆封装，包括：半导体衬底，具有相对的上表面和下表面；位于所述上表面的多个焊盘；位于所述多个焊盘上的多个焊球；覆盖所述上表面的阻焊层，所述阻焊层露出所述多个焊球并且未覆盖所述上表面的边缘位置；环绕所述阻焊层的金属导热层，所述金属导热层仅位于所述上表面的边缘位置；位于所述下表面的散热层；以及连接所述金属导热层和所述散热层的多个导热通孔；所述金属导热层的厚度小于所述阻焊层的厚度。
根据本发明的实施例，所述阻焊层的边缘具有一阶梯，所述金属导热层的厚度不大于所述阶梯的厚度。
根据本发明的实施例，所述金属导热层紧贴于所述阶梯的边缘。
根据本发明的实施例，所述阶梯的厚度为所述阻焊层厚度的一半。
根据本发明的实施例，所述阻焊层厚度为100-200微米。
根据本发明的实施例，所述金属导热层的材料选自Cu和Ni中的至少一种。
根据本发明的实施例，所述导热通孔可以填充导电材料，优选为Cu或Au。
根据本发明的实施例，所述导热通孔可以填充非导电材料，优选为Al2O3。
根据本发明的实施例，所述散热层的材料为金属。
根据本发明的实施例，所述散热层为散热鳍片结构。
本发明的技术方案，利用上表面周边的金属导热层进行第一步散热，然后通过导热通孔将一部分热量传导至下表面的散热层上，散热层面积大，散热效率高，且不易对上表面的器件造成影响，极大的提高了散热效率，保证了封装的可靠性；并且周边的金属导热层和导热通孔具有电磁屏蔽作用，保证其他电子部件对封装件的干扰；边缘的金属导热层与阻焊层颜色不同，可以轻易的分辨出边缘位置；最后，所述阻焊层高于所述金属导热层，可以防止金属导热层与焊球间的相互影响（短路等）。
附图说明
图1为本发明晶圆封装结构的剖面图；
图2为本发明晶圆封装结构的俯视图。
具体实施方式
参见图1，本发明提供了一种具有散热结构的晶圆封装，包括：半导体衬底10，具有相对的上表面和下表面；位于所述上表面的多个焊盘11；位于所述多个焊盘上的多个焊球13；覆盖所述上表面的阻焊层12，所述阻焊层12露出所述多个焊球13并且未覆盖所述上表面的边缘位置；环绕所述阻焊层12的金属导热层14，所述金属导热层14仅位于所述上表面的边缘位置；位于所述下表面的散热层15；以及连接所述金属导热层14和所述散热层15的多个导热通孔16；在本实施例中，所述金属导热层14的厚度小于所述阻焊层12的厚度，这样可以更加突出焊球的高度，在外连接其他电子部件或基板时，可以避免金属导热层14与焊球的短路或者与其他电子部件或基板的短路。
优选的，参见图1和图2，所述阻焊层12的边缘具有一阶梯17，所述金属导热层14紧贴于所述阶梯17的边缘，所述阶梯17环绕所述焊球阵列，所述金属导热层14的厚度不大于所述阶梯17的厚度，更优的，金属导热层14的厚度等于所述阶梯17的厚度。所述阶梯的厚度为所述阻焊层厚度的一半，例如，所述阻焊层厚度为100-200微米，所述阶梯厚度为50-100微米，所述金属导热层14的厚度也为50-100微米。该阶梯的设置可以防止在沉积或电镀金属导热层14时，过量的金属材料溢出到阻焊层的上表面导致焊球的短路。
此外，根据本发明的实施例，所述金属导热层14的材料选自Cu和Ni中的至少一种。所述导热通孔16可以填充导电材料，优选为Cu或Au；所述导热通孔16也可以填充非导电材料，优选为Al2O3。所述散热层15的材料为金属或散热键合片等。所述散热层也可以为散热鳍片结构（未示出）。
最后应说明的是：显然，上述实施例仅仅是为清楚地说明本发明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引申出的显而易见的变化或变动仍处于本发明的保护范围之中。

Claims (3)

1.一种具有散热结构的晶圆封装，包括：半导体衬底，具有相对的上表面和下表面；位于所述上表面的多个焊盘；位于所述多个焊盘上的多个焊球；覆盖所述上表面的阻焊层，所述阻焊层露出所述多个焊球并且未覆盖所述上表面的边缘位置；环绕所述阻焊层的金属导热层，所述金属导热层仅位于所述上表面的边缘位置；位于所述下表面的散热层；以及连接所述金属导热层和所述散热层的多个导热通孔；
其特征在于，所述金属导热层的厚度小于所述阻焊层的厚度，所述金属导热层的材料选自Cu和Ni中的至少一种；所述导热通孔填充导电材料，所述导电材料为Cu或Au；所述导热通孔填充非导电材料，所述非导电材料为Al2O3。
2.根据权利要求1所述的具有散热结构的晶圆封装，其特征在于，所述散热层的材料为金属。
3.根据权利要求1所述的具有散热结构的晶圆封装，其特征在于，所述散热层为散热鳍片结构。
CN201811034100.0A 2016-11-27 2016-11-27 具有散热结构的晶圆封装 Withdrawn CN109411422A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811034100.0A CN109411422A (zh) 2016-11-27 2016-11-27 具有散热结构的晶圆封装

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811034100.0A CN109411422A (zh) 2016-11-27 2016-11-27 具有散热结构的晶圆封装
CN201611058184.2A CN106449561B (zh) 2016-11-27 2016-11-27 一种具有散热结构的晶圆封装

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN201611058184.2A Division CN106449561B (zh) 2016-11-27 2016-11-27 一种具有散热结构的晶圆封装

Publications (1)

Publication Number Publication Date
CN109411422A true CN109411422A (zh) 2019-03-01

Family

ID=58218892

Family Applications (3)

Application Number Title Priority Date Filing Date
CN201811034100.0A Withdrawn CN109411422A (zh) 2016-11-27 2016-11-27 具有散热结构的晶圆封装
CN201611058184.2A Active CN106449561B (zh) 2016-11-27 2016-11-27 一种具有散热结构的晶圆封装
CN201811034300.6A Active CN109411424B (zh) 2016-11-27 2016-11-27 一种具有散热结构的晶圆封装

Family Applications After (2)

Application Number Title Priority Date Filing Date
CN201611058184.2A Active CN106449561B (zh) 2016-11-27 2016-11-27 一种具有散热结构的晶圆封装
CN201811034300.6A Active CN109411424B (zh) 2016-11-27 2016-11-27 一种具有散热结构的晶圆封装

Country Status (1)

Country Link
CN (3) CN109411422A (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112449477B (zh) * 2019-08-27 2022-04-15 宏启胜精密电子(秦皇岛)有限公司 电路板的制造方法及电路板
CN115132679A (zh) * 2022-08-30 2022-09-30 之江实验室 一种具有热电制冷系统的晶圆级封装结构

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6028367A (en) * 1999-05-07 2000-02-22 Taiwan Semiconductor Manufacturing Company, Ltd. Bonds pads equipped with heat dissipating rings and method for forming
US6577013B1 (en) * 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
TW466723B (en) * 2000-12-01 2001-12-01 Siliconware Precision Industries Co Ltd Super thin package having high heat-dissipation property
WO2002101829A1 (en) * 2001-06-13 2002-12-19 Advanpack Solutions Pte Ltd Method for forming a wafer level chip scale package, and package formed thereby
JP3893301B2 (ja) * 2002-03-25 2007-03-14 沖電気工業株式会社 半導体装置の製造方法および半導体モジュールの製造方法
US8198716B2 (en) * 2007-03-26 2012-06-12 Intel Corporation Die backside wire bond technology for single or stacked die package
US7473586B1 (en) * 2007-09-03 2009-01-06 Freescale Semiconductor, Inc. Method of forming flip-chip bump carrier type package
US8642385B2 (en) * 2011-08-09 2014-02-04 Alpha & Omega Semiconductor, Inc. Wafer level package structure and the fabrication method thereof
US9236322B2 (en) * 2012-04-11 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for heat spreader on silicon
CN104795372A (zh) * 2015-03-27 2015-07-22 江阴长电先进封装有限公司 一种指纹识别传感器芯片的封装结构
CN104900768A (zh) * 2015-04-14 2015-09-09 芜湖九瓷电子科技有限公司 一种led用氧化铝陶瓷基板制造方法

Also Published As

Publication number Publication date
CN106449561A (zh) 2017-02-22
CN109411424A (zh) 2019-03-01
CN106449561B (zh) 2018-09-28
CN109411424B (zh) 2020-11-27

Similar Documents

Publication Publication Date Title
US10204848B2 (en) Semiconductor chip package having heat dissipating structure
EP3567628B1 (en) Semiconductor package system
US8648461B2 (en) Semiconductor device
TW201839931A (zh) 半導體封裝結構
JP2008166440A (ja) 半導体装置
US9343437B2 (en) Semiconductor package devices
US7388286B2 (en) Semiconductor package having enhanced heat dissipation and method of fabricating the same
CN106548993B (zh) 一种晶圆封装结构
JP6473778B2 (ja) 光学的封止構造体
CN106449561B (zh) 一种具有散热结构的晶圆封装
CN106449563B (zh) 一种具有鳍形结构的晶圆封装
CN106449562B (zh) 一种具有散热结构的晶圆封装方法
CN106449432B (zh) 一种晶圆封装结构的制造方法
TWI778249B (zh) 半導體封裝系統
CN106449443B (zh) 一种具有鳍形结构的晶圆封装方法
KR20180023488A (ko) 반도체 패키지 및 반도체 패키지 제조방법
KR102654893B1 (ko) 반도체 패키지 시스템
KR102607109B1 (ko) 반도체 패키지 시스템
US9870977B2 (en) Semiconductor device with heat information mark
KR20100025436A (ko) 플립칩 패키지 및 그 제조방법
CN110098158B (zh) 半导体封装件
CN117855163A (zh) 封装结构及其形成方法
WO2014049965A1 (ja) 実装基板を用いた回路モジュール

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WW01 Invention patent application withdrawn after publication
WW01 Invention patent application withdrawn after publication

Application publication date: 20190301