CN109411409A - 金属化层及其制造方法 - Google Patents

金属化层及其制造方法 Download PDF

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CN109411409A
CN109411409A CN201810926968.5A CN201810926968A CN109411409A CN 109411409 A CN109411409 A CN 109411409A CN 201810926968 A CN201810926968 A CN 201810926968A CN 109411409 A CN109411409 A CN 109411409A
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conductive
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metallized thread
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尼古拉斯·V·利考西
埃罗尔·特德·莱恩
林萱
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GlobalFoundries US Inc
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Abstract

本发明涉及金属化层及其制造方法，揭示集成电路的金属化层的结构及其相关制造方法。具有形成一金属线的一第一金属化层。一第二金属化层形成于该第一金属化层的上方，具有二金属化线以及从该二金属化线延伸至该第一金属化层的该金属化线的二导电通孔。该第一金属化线被分割为一第一区段以及与该第一部分断开的一第二区段，使得该第一区段通过一导电通孔连接至该第二金属化层中的一金属线，该第二区段通过另一导电通孔连接至该第二层中的另一金属化线。

Description

金属化层及其制造方法
技术领域
本发明涉及半导体设备制造以及集成电路，更具体而言，涉及集成电路的金属化层及制造金属化层的方法。
背景技术
一集成电路的金属化层用于提供设备以及该集成电路的组件之间的连接。任何一个金属化层通常包括多个导电金属化线，且一个层的金属化线可通过导电通孔连接到一较高或较低层的金属化线。当集成电路设备继续缩小时，各种制造技术的限制可能会限制导电通孔的设置位置以及导电通孔如何紧密地设置在一起，并限制了特定金属化层以及整个集成电路的设计。
发明内容
在本发明的一实施例中，一种方法包括形成一第一金属化层以及位于该第一金属化层上方的第二金属化层。该第一金属化层具有一金属化线，该第二金属化层具有一介电层以及两条金属化线，该两条金属化线通过延伸通过该介电层的导电通孔而连接至该第一金属化层中的该金属化线。在形成该第二金属化层之后，该第一层中的该金属化线被分割为相互断开的两个区段，导致一个区段通过一个导电通孔连接到该第二层中的一金属化线，以及另一区段通过该另一导电通孔连接至该第二层中的该另一金属化线。
在本发明的一实施例中，一种结构具有一第一金属化层，该第一金属化层具有一金属化线，该金属化线被分割为相互断开的两个区段。该结构具有位于该第一金属化层上方的一第二金属化层，该第二层具有一介电层、通过延伸通过该介电层的一个导电通孔连接至该第一层中的一个区段的一个金属线、以及通过延伸通过该介电层的另一个导电通孔连接至该第一层中的另一区段的另一金属化线。第一金属化层中的该金属化线的该一区段具有与该一个导电通孔的一侧壁对齐并接触的一末端，第一金属化层中的该金属化线的该另一区段具有与该另一个导电通孔的一侧壁对齐并接触的一末端。
附图说明
纳入并构成本说明书的一部分的附图说明了本发明的各种实施例，连同上述给出的本发明的一般描述以及下面给出的实施例的详细描述，用于解释本发明的实施例。
图1A以及图2至图9为根据本发明的实施例所述的一处理方法的连续制造阶段中的横截面图。
图1B为图1A所示结构的一等距视图。
具体实施方式
参考图1A和图1B，根据本发明的实施例，描述在形成一第一金属化层110以及位于第一金属化层110上方的一第二金属化层120之后的一结构100。在图1B中，为了清晰和易于理解，结构100的一部分，包括介电层121以及金属化线125的一部分，已被移除。第一金属化层110具有一金属化线115，且可具有额外的金属化线117和设置在金属化线115,117之间的介电材料116，如图1B中的结构100的等距视图所示。第一金属化层110可设置在一层间介电层101的上方，其可将该金属化层与下层电路结构组件或其他金属化层电性隔离(未在图1A至图9中示出)。结构100还具有一第二金属化层120，其包括一介电层121、一金属化线125a、以及另一金属化线125b，并且可以包括额外的金属化线125。第二金属化层120还具有从金属化线125a延伸通过介电层121至金属化线115的一导电通孔130a，以及从金属化线125b延伸通过介电层121至金属化线115的另一导电通孔130b。结构100还可以包括设置在第一金属化层110上方以及介电层121下方的一介质帽(dielectric cap)122。介质帽122可以是与介电层121的该介电材料不同的一介电材料，并可以具有与介电层121不同的蚀刻选择性。例如，介电层121可以是一氧化物介电材料，且介质帽122可以是一氮化物介电材料。在本文中，术语“第一”以及“第二”用于不同的金属化层，以表示结构100内的金属化层的相对位置以便于参考，而非用于限制。“第一金属化层”，如图1A至图1B中的金属化层110，可以对应于一集成电路结构中的第一金属化层或最低的金属化层，或者可以对应于所述结构中的更高的金属化层；同样的，“第二金属化层”，例如金属化层120，可以对应于形成于该第一金属化层上方的第二金属化层，或可以对应于该集成电路结构中的更高的金属化层。
集成电路结构中的金属化层，无论是第一金属化层110或第二金属化层120或另一金属化层，可大致通过任何适合的工艺形成，例如，通过光刻蚀刻工艺，其中，根据一图案化硬掩膜，在一介电层(例如介电层121)中蚀刻出沟槽。这样的工艺可以是单曝光图案化工艺、自对准双图案化(SADP)工艺等。通孔也可以使用类似的蚀刻工艺蚀刻通过介电层121，从而形成与金属化沟槽自对准的通孔。然后，沟槽以及通孔可以填充导电材料以形成金属化线125,125a,125b及导电通孔130a，130b。在示例性实施例中，如图1A及图1B所示，导电通孔130a及130b可以是相邻的导电通孔，两者的中心分离一跨度D，如图1A所示，基本上等于为该集成电路结构所定义的一最小临界尺寸，例如一层中的金属化线之间的最小间距。由于电路和电路特征的继续缩小，金属化层的设计规则经常需要将导电通孔隔离为一金属化层所定义的最小间距的至少两倍，这是由于在较低的金属化层的制造工艺的限制下，例如在一金属化层内形成以及切割金属化线的工艺，不能将导电通孔连接到一较低的金属化层中的单独的金属线上。本文公开和描述的工艺可允许两个导电通孔彼此相邻地形成，使得其中心以该最小临界尺寸或最小间距分开，并使得各导电通孔将一上层金属化层(例如第二金属化层120)的一条金属化线连接至一较低金属化层(例如第一金属化层110)的一独立金属化线上。
如图1A所示的结构100的实施例所描述，第一金属化层110可包括设置在金属化线115下方的一阻障衬垫111。阻障衬垫111也可以设置在金属化线115的侧壁上。第二金属化层120可具有设置在金属化线125,125a,125b，以及导电通孔130a,130b的下方及/或其侧壁上的一阻障衬垫126。例如阻障衬垫111和/或阻障衬垫126的一阻障衬垫可以是钛、氮化钛、钽、氮化钽，或其他阻障衬垫材料，并通过例如化学气相沉积(CVD)或原子层沉积(ALD)予以形成。可包括一阻障衬垫以防止金属化线的金属材料与底层介电层(例如层间介电层101)的材料相互作用或结合。金属化线115还可以包括金属化线115上方的一导电帽112。金属化线125,125a,125b以及导电通孔130a,130b也可以包括一导电帽127。导电帽112,127可例如为钴或钌或其他导电材料，并且可以通过例如化学气相沉积或原子层沉积予以形成。
请参考图2，其中相同的附图标记指代图1A及图1B中的相似特征。于处理方法的一后续制造阶段，一帽体140选择性地生长在金属化线125,125a,125b上以及导电通孔130a,130b的上表面上，一图案化光刻堆栈150形成在第二金属化层120的上方。如本文所进一步详述的，在第一金属化层110中的金属化线115的一部分被移除期间，帽体140用于保护金属化线125a及125b，以及导电通孔130a及130b的上表面。如本文所进一步详述的，帽体140包括一材料，其抵抗蚀刻介电材料(例如介电层121或介质帽122)的蚀刻工艺，抵抗蚀刻工艺以移除或“切割”金属化线115的一部分，并可在不影响结构100的其他部分的情况下随后被选择性的移除。帽体140可例如为钨、镍、钼、或铝的导电体，或例如为硅的半导体，或它们的组合。或者，帽体140可以是绝缘体，例如氧化铪、氧化铝、或其组合。帽体140可以是导电体与绝缘体的组合，或者半导体与绝缘体的组合，或者导电体、半导体与绝缘体材料的组合。图案化光刻堆栈150可以包括，例如，一有机平坦化层(OPL)151，一抗反射涂层152，以及一光阻层153。光阻层153经图案化而具有对准于待蚀刻的介电层121的一部分上方的开口154，如后进一步详述。
请参考图3，其中，相同的附图标记指代图2中的相似特征，在处理方法的一后续制造阶段，图案化光刻堆栈150被选择性的蚀刻以形成通过图案化光刻堆栈150的一开口154，例如，通过有机平坦化层151，以暴露导电通孔130a与导电通孔130b之间的介电层121a。图案化光刻堆栈150的一个或多个层，例如光阻层153以及抗反射涂层152可在选择性蚀刻图案化光刻堆栈150之后被移除。
请参考图4，其中，相同的附图标记指代图3中的相似特征，在处理方法的一后续制造阶段，一沟槽155形成在导电通孔130a以及130b之间的介电层121中，移除由开口154曝光的介电层121a的部分，以暴露金属化线115的一部分。沟槽155可通过对介电层121具有选择性的任何蚀刻工艺进行蚀刻。导电通孔130a以及130b的作用在于使沟槽155的蚀刻自对准，使得金属化线115的暴露部分与导电通孔130a以及导电通孔130b的侧壁对准。在结构100包括一介质帽122的实施例中，位于导电通孔130a以及130b之间的介质帽122可在蚀刻出介电层121中的沟槽155之后被移除以暴露金属化线115的部分。图案化光刻堆栈150可以保留在第二金属化层120的上方以保护介电层121的其他部分以及介质帽122不受蚀刻工艺或蚀刻处理的影响。
请参考图5，其中，相同的附图标记指代图4中的相似特征，在处理方法的一后续制造阶段，金属化线115的一部分被移除或“切割”，将金属化线115分割为相互分离的两个区段115a,115b。金属化线115的部分的移除可通过例如使用蚀刻剂的一蚀刻工艺来完成，该蚀刻剂选择性移除金属化线115的暴露部分，以及阻障衬垫111与导电帽112的部分，而不影响介电层121、层间介电层101或帽体140。如上所述，帽体140包括抵抗用于蚀刻介电材料的蚀刻工艺的一个或多个材料，并抵抗用于移除金属化线115的一部分的蚀刻工艺，使得金属化线125及125a，125b以及导电通孔130a，130b的上表面在蚀刻处理期间保持完整。在移除金属化线115之后，金属化线115的区段115a及115b可具有暴露的端面115c以及115d，根据所选择的蚀刻剂以及该蚀刻剂的曝光时间长度而定，导电通孔130a以及130b的侧壁可以部分被暴露以及回蚀刻，如图5所示。
请参考图6，其中，相同的附图标记指代图5中的相似特征，在处理方法的一后续制造阶段，一导电阻障材料160选择性地生长在金属化线115的区段115a的暴露的端面115c以及部分115b的暴露的端面115d的上方，一间隙填充介电材料165沉积在金属化线115的区段115a,115b之间以及导电通孔130a,130b之间。导电阻障材料160也可以选择性地生长于导电通孔130a以及导电通孔130b的暴露侧壁上方。导电阻障材料160可以通过CVD或ALD工艺或其他替代工艺生长，且可以是例如钴、钌或其他导电阻障材料。导电阻障材料不会生长在帽体140的材料上方或粘附在帽体140的材料上。生长导电阻障材料160可以促进部分地“重建”导电通孔130a及130b的部分，这些部分可能在移除金属化线115的部分期间被移除，如上所述。如本文所述，导电阻障材料160还可以防止区段115a及115b的金属材料以及导电通孔130a及130b的金属材料与间隙填充介电材料165相互作用或结合。
间隙填充介电材料165可以是一介电材料，被选择用于减小或最小化区段115a及115b之间或导电通孔130a及130b之间的电容。如上所述，导电通孔130a及130b可具有以一跨度隔离的中心，此跨度基本上等于为结构100所定义的一最小临界尺寸，且导电通孔的之间的电容与导电通孔之间的间隔成反比，导电通孔130a及130b之间的电容可能相对较高。因此，可以使用具有相对较高的的介电常数k的间隙填充介电材料165来降低此电容。例如，间隙填充介电材料165可以是氮掺杂碳化硅。在另一实施例中，间隙填充介电材料165可以是一高k氧化物材料。在一实施例中，间隙填充介电材料165可以是高度共形的，使得间隙填充介电材料165是实心的而没有空隙或气隙，因此不会发生夹断(pinch-off)。在另一替换性实施例中，间隙填充可以是部分的，其可通过在一深度处的夹断而引入一间隙或气隙129，使得当间隙填充介电材料165在一后续制造阶段中被凹陷时，气隙129不会被打开。
请参考图7，其中，相同的附图标记指代图6中的相似特征，在处理方法的一后续制造阶段，间隙填充介电材料165被凹陷，且帽体140从金属化线125,125a,125b以及导电通孔130a,130b的上方被移除。虽然在可替换实施例中允许在不移除帽体140的情况下继续制造，但是例如，如果帽体140为一导电材料，例如钨，则通常移除帽体140是有利的，使得帽体140不干扰后续的制造工艺。类似的，虽然在替换性实施例中，间隙填充介电材料165可能不被凹陷，但是通常，凹陷间隙填充介电材料165是有利的，使得第二金属化层120上方不会有高介电常数材料干扰后续制造工艺。
请参考图8，其中，相同的附图标记指代图7中的相似特征，在处理方法的一后续制造阶段，一共形介质帽层170沉积在第二金属化层120的上方。共形介质帽层170可以是与介质帽122类似的材料，例如一氮化物基介电材料。
请参考图9，其中，相同的附图标记指代图8中的相似特征，在处理方法的一后续制造阶段，一第三金属化层200形成在共形介质帽层170以及第二金属化层120的上方。与第一金属化层110或第二金属化层120类似，第三金属化层200可以包括形成在一介电层201中的一条或多条金属化线205，且金属化线205可以包括一阻障层202以及导电帽层206。第三金属化层200的制造可以包括本文所述的工艺或其他通常用于制造集成电路结构的金属化层的工艺。
上述方法用于制造集成电路芯片。所得到的集成电路芯片可以由制造商以原始晶片形式(例如，作为具有多个未封装芯片的一单晶片)，一裸片，或一封装形式予以分布。在后一种情况下，芯片安装在一单芯片封装中(例如，一塑料载体，具有附接到一母板或其他更高级别的载体的引线)或一多芯片封装中(例如，具有表面互连或埋置互连中的一个或两个的一陶瓷载体)。在任何情况下，芯片可以与其他芯片、分立电路元件和/或其他信号处理设备集成为一中间产品或一最终产品的一部分。
本文引用的术语，如“垂直”、“水平”等是通过示例而不是通过限制来建立参考框架的。本文使用的术语“水平”被定义为与一半导体基板的一传统平面平行的一平面，而不管其实际三维空间取向。术语“垂直”和“正常”指的是垂直于水平的方向，正如刚才所定义的。“横向”一词是指水平面内的一个方向。诸如“上方”和“下方”这样的术语用于表示元件或结构相对于彼此的定位，而不是相对高度。
“连接”或“耦合”到另一个元件的一个特征可以直接连接或耦合到另一个元件，或者，可以存在一个或多个介入元件。如果缺少介入元件，则一个特征可以是“直接连接”或“直接耦合”到另一个元件。如果存在至少一个介入元件，则一个特征可以是“间接连接”或“间接耦合”到另一个元件。
为了说明的目的，已经提出了本发明的各种实施例的描述，但不打算穷尽或局限于所公开的实施例。在不脱离所描述的实施例的范围和精神的情况下，许多修改和变化对本领域的普通技术人员而言是显而易见的。本文所使用的术语被选择来最好地解释实施例的原理、实际应用或技术改进，而不是市场上所发现的技术，或者使本领域的普通技术人员能够理解本文所公开的实施例。

Claims (20)

1.一种方法，包括：
形成具有第一金属化线的第一金属化层；
形成第二金属化层于该第一金属化层的上方，该第二金属化层具有介电层、第二金属化线、第三金属化线、从该第二金属化线延伸通过该介电层至该第一金属化线的第一导电通孔、以及从该第三金属化线通过该介电层至该第一金属化线的第二导电通孔；以及
在形成该第二金属化层之后，将该第一金属化线分割为第一区段以及与该第一区段断开的第二区段，
其中，该第一金属化线的该第一区段通过该第一导电通孔连接至该第二金属化线，该第一金属化线的该第二区段由该第二导电通孔连接至该第三金属化线。
2.根据权利要求1所述的方法，其中，在分离该第一金属化线之后，该第一区段具有与该第一导电通孔的第一侧壁对齐并接触的第一端，该第二部分具有与该第二导电通孔的第二侧壁对齐并接触的第二端。
3.根据权利要求1所述的方法，其中，分离该第一金属化线包括：
蚀刻位于该第一导电通孔与该第二导电通孔之间的该介电层中的沟槽，该蚀刻暴露该第一金属化线的一部分；以及
移除该第一金属化线的该暴露部分。
4.根据权利要求3所述的方法，其中，蚀刻该介电层中的该沟槽包括：
形成图案化光刻堆栈于该第二金属化层的上方；
选择性蚀刻该图案化光刻堆栈以暴露该第一导电通孔与该第二导电通孔之间的该介电层；以及
蚀刻该暴露的介电层以暴露该第一金属化线的该部分。
5.根据权利要求4所述的方法，其中，蚀刻该暴露的介电层是通过该第一导电通孔与该第二导电通孔以自对准该第一金属化线的该部分。
6.根据权利要求4所述的方法，还包括：
选择性地生长帽体于该第二金属化线以及该第三金属化线上，在移除该第一金属化线的该暴露部分期间，该帽体保护该第二金属化线以及该第三金属化线以及该第一导电通孔与该第二导电通孔的上表面。
7.根据权利要求6所述的方法，其中，该帽体为钨、镍、钼、硅、铝、氧化铪，或其组合。
8.根据权利要求6所述的方法，其中，该第一金属化层具有位于该第一金属化线的上方以及该第二金属化层的该介电层的下方的介质帽，该介质帽具有与该介电层以及该帽体不同的蚀刻选择性，且还包括：
移除该第一导电通孔与该第二导电通孔之间的该介质帽。
9.根据权利要求6所述的方法，还包括：
选择性生长导电阻障材料于该第一金属化线的该第一区段与该第二区段的暴露的端面上。
10.根据权利要求9所述的方法，其中，该导电阻障材料还进一步选择性生长于该第一导电通孔的第一暴露侧壁的上方以及该第二导电通孔的第二暴露侧壁的上方。
11.根据权利要求9所述的方法，其中，该导电阻障材料为钴或钌。
12.根据权利要求6所述的方法，还包括：
沉积间隙填充介电材料于该第一金属化线的的该第一区段与该第二区段之间、以及该第一导电通孔与该第二导电通孔之间；
移除该帽体；
沉积共形介质帽于该第二金属化层的上方；以及
形成第三金属化层于该共形介质帽层的上方。
13.根据权利要求12所述的方法，其中，该间隙填充介电材料包括氮掺杂碳化硅或高k氧化物材料。
14.根据权利要求12所述的方法，其中，该间隙填充介电材料包括气隙。
15.一种结构，包括：
集成电路结构的第一金属化层，该第一金属化层具有被分割为第一区段以及与该第一区段断开的第二区段的第一金属化线；以及
第二金属化层，位于该第一金属化层的上方，该第二金属化层具有介电层、第二金属化线、第三金属化线、从该第二金属化线延伸通过该介电层至该第一金属化线的该第一区段的第一导电通孔、以及从该第三金属化线延伸通过该介电层至该第一金属化线的该第二区段的第二导电通孔，
其中，该第一区段具有与该第一导电通孔的第一侧壁对齐并接触的第一端面，该第二区段具有与该第二导电通孔的第二侧壁对齐并接触的第二端面。
16.根据权利要求15所述的结构，其中，该第一导电通孔的第一中心与该第二导电通孔的第二中心相隔一跨度，该跨度基本上等于该集成电路结构的最小临界尺寸。
17.根据权利要求15所述的结构，还包括：
间隙填充介电材料，位于该第一金属化线的该第一区段与该第二区段之间，以及该第一导电通孔与该第二导电通孔之间。
18.根据权利要求17所述的结构，其中，该间隙填充介电材料为氮掺杂碳化硅或高k氧化物材料。
19.根据权利要求17所述的结构，其中，该间隙填充介电材料包括气隙。
20.根据权利要求15所述的结构，还包括：
导电阻障材料，设置于该第一金属化线的该第一区段的该第一端面、该第一金属化线的该第二区段的该第二端面、该第一导电通孔的该第一侧壁、以及该第二导电通孔的该第二侧壁的上方，
其中，该导电阻障材料包括钴或钌。
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