CN109390360B - 用于限制封装高度并减少边缘闪光的图像传感器封装 - Google Patents
用于限制封装高度并减少边缘闪光的图像传感器封装 Download PDFInfo
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- CN109390360B CN109390360B CN201810520561.2A CN201810520561A CN109390360B CN 109390360 B CN109390360 B CN 109390360B CN 201810520561 A CN201810520561 A CN 201810520561A CN 109390360 B CN109390360 B CN 109390360B
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- 239000000758 substrate Substances 0.000 claims abstract description 93
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 53
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 53
- 239000010703 silicon Substances 0.000 claims abstract description 53
- 229910000679 solder Inorganic materials 0.000 claims abstract description 44
- 239000000463 material Substances 0.000 claims abstract description 30
- 239000006059 cover glass Substances 0.000 claims abstract description 26
- 230000002093 peripheral effect Effects 0.000 claims abstract description 25
- 239000011810 insulating material Substances 0.000 claims description 12
- 230000001070 adhesive effect Effects 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 238000002310 reflectometry Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims 22
- 239000012790 adhesive layer Substances 0.000 claims 6
- 239000011521 glass Substances 0.000 claims 5
- 239000000853 adhesive Substances 0.000 claims 3
- 239000002861 polymer material Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 13
- 239000010931 gold Substances 0.000 description 13
- 229910052737 gold Inorganic materials 0.000 description 13
- 239000003292 glue Substances 0.000 description 11
- 230000008878 coupling Effects 0.000 description 7
- 238000010168 coupling process Methods 0.000 description 7
- 238000005859 coupling reaction Methods 0.000 description 7
- 238000013461 design Methods 0.000 description 7
- 230000004048 modification Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 230000004313 glare Effects 0.000 description 5
- 239000002800 charge carrier Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 239000007921 spray Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000002059 diagnostic imaging Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000004922 lacquer Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H01L27/146—Imager structures
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- H01L27/14636—Interconnect structures
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- H01L2224/0554—External layer
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- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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Abstract
本申请案涉及一种用于限制封装高度并减少边缘闪光的图像传感器封装。在一个实施例中,所述图像传感器封装包括硅衬底;图像传感器像素阵列,其形成在所述硅衬底上;外围电路区,其形成在所述硅衬底上的所述图像传感器像素阵列周围;再分布层RDL,其电耦合到所述外围电路区;至少一个焊球,其电耦合到所述RDL;及护罩玻璃,其耦合到所述RDL。所述RDL的任何部分都不定位在所述图像传感器像素阵列的正上方或正下方。所述至少一个焊球的任何部分都不定位在所述硅衬底的正上方或正下方。实施暗材料层以防止所述图像传感器像素阵列的边缘闪光效应。
Description
技术领域
本发明大体上涉及图像传感器封装。特定来说,图像传感器经封装以使其再分布层(RDL)及焊球定位到其像素阵列的侧,以便降低图像传感器封装的总体高度。另外,实施暗材料侧壁以减少不希望的边缘闪光。
背景技术
图像传感器使用例如光电二极管的光电子组件来检测入射光并作为响应产生电子信号。图像传感器的主要组件是其传感器像素阵列,其中每一像素包含将光子转换为电荷载流子的光电二极管,暂时存储电荷载流子的浮动节点,以及数个晶体管门(转移栅极,源极跟随器、复位晶体管等),其将电荷载流子传送出像素以由外围电路进一步处理。通常将图像传感器与其支持元件一起封装到图像传感器封装中,然后将图像传感器封装并入成像产品中,例如移动电话照相机、消费型电子照相机、监控摄像机、汽车驾驶员辅助装置、医学成像内窥镜等。
发明内容
一方面,本申请案涉及一种图像传感器封装。所述图像传感器封装包括:(a)硅衬底,其包含第一衬底表面,及与所述第一衬底表面相对的第二衬底表面;(b)图像传感器像素阵列,其形成在所述硅衬底上并位于所述第一衬底表面处;(c)外围电路区,其形成在所述硅衬底上的所述图像传感器像素阵列周围,并位于所述第一衬底表面处;(d)再分布层(RDL),其电耦合到所述外围电路区;(e)至少一个焊球,其电耦合到所述RDL;及(f)护罩玻璃,其耦合到所述RDL;其中所述RDL包含第一RDL表面及与所述第一RDL表面相对的第二RDL表面;其中所述第一RDL表面面对与所述第一衬底表面相同的方向;且其中所述第二RDL表面面对与所述第二衬底表面相同的方向。
另一方面,本申请案涉及一种图像传感器系统。所述图像传感器包括图像传感器封装,其中所述图像传感器封装包含:(a)硅衬底,其包含第一衬底表面,及与所述第一衬底表面相对的第二衬底表面;(b)图像传感器像素阵列,其形成在所述硅衬底上并位于所述第一衬底表面处;(c)外围电路区,其形成在所述硅衬底上的所述图像传感器像素阵列周围,并位于所述第一衬底表面处;(d)再分布层(RDL),其电耦合到所述外围电路区;(e)至少一个焊球,其电耦合到所述RDL;及(f)护罩玻璃,其耦合到所述RDL;其中所述RDL包含第一RDL表面及第二RDL表面;其中所述第一RDL表面面对与所述第一衬底表面相同的方向;且其中所述第二RDL表面面对与所述第二衬底表面相同的方向。
附图说明
参考以下诸图描述本发明的非限制性及非穷尽实例,其中相似参考数字贯穿各种视图指代相似部件,除非另有规定。
图1A是展示在传感器像素阵列下方具有再分布层及焊球的图像传感器封装的第一实施例的横截面侧视图。
图1B是展示具有护罩玻璃遮光罩来减少边缘闪光的图像传感器封装的第二实施例的横截面图。
图2A是展示其中再分布层及焊球定位到传感器像素阵列的侧的图像传感器封装的第三实施例的横截面图。
图2B是展示其中再分布层及焊球定位到传感器像素阵列的侧的降低高度图像传感器封装的第四实施例的横截面图。
图3A及3B分别是展示图像传感器封装的第三实施例及第四实施例的边缘闪光效应的横截面图。
图4A是展示具有减少边缘闪光效应的暗材料侧壁的图像传感器封装的第五实施例的横截面侧视图。
图4B是展示具有减少边缘闪光效应的暗材料侧壁的图像传感器封装的第六实施例的横截面侧视图。
对应参考字符贯穿附图的若干视图指示对应组件。所属领域的技术人员应了解,图式中的元件出于简单及清楚的目的而说明,且未必是按比例绘制。举例来说,图式中一些元件的尺寸相对于其它元件可被夸大以帮助提高对本发明的各种实施例的理解。此外,为了促进对本发明的这些各种实施例的更容易的观察,通常不描绘在商业上可行的实施例中有用的或必需的常见但众所周知的元件。
具体实施方式
在以下描述中,阐述众多特定细节以提供对所述实例的透彻理解。然而,所属领域的技术人员将认识到,能够在不具有一或多个特定细节的情况下或配合其它方法、组件、材料等等实践本文所描述的技术。在其它情况下,未展示或详细地描述众所周知的结构、材料或操作以避免混淆某些方面。
贯穿本说明书的对“实例”或“实施例”的参考意指结合实例所描述的特定特征、结构或特性包含于本发明的至少一个实例中。因此,贯穿本说明书的各种地方的“实例”或“实施例”的出现未必都是指同一实例。此外,特定特征、结构或特性可以任何合适方式组合于一或多个实例中。
贯穿本说明书,使用若干所属领域的术语。这些术语具有其出自的所属领域的一般意义,除非本文具体定义或其使用背景另有明确指示。
第一图像传感器封装实施例
图1A是展示图像传感器封装100A的第一实施例的横截面侧视图。传感器封装100A的第一实施例包含硅衬底130,其中图像传感器像素阵列140形成在其顶部或前侧表面上。图像传感器像素阵列140包含数个图像传感器像素;每一像素经配置以检测传入光子并作为响应产生光电信号。这些像素可示范性地基于互补金属氧化物半导体(CMOS)或电荷耦合装置(CCD)设计。环绕像素阵列140的是外围电路区145,其在图1A中用虚线矩形标记。由像素阵列140产生的电信号被传送到此外围电路区145中以被进一步处理。在硅衬底130的底部或后侧表面处的是含有金属布线的再分布层(RDL)120。穿硅通孔(TSV)180连接以提供硅衬底的前侧表面处的外围电路区145与硅衬底的后侧表面处的RDL 120之间的电耦合。焊球150连接(例如,电耦合)到RDL 120。当焊球150安装在印刷电路板(PCB,图1A中未展示)上时,将在RDL 120与PCB之间建立电耦合。坝状物170位于硅衬底130的前侧表面上。护罩玻璃110位于坝状物170的顶部上。
应了解,在图像传感器封装100A的此第一实施例中,RDL 120及焊球150位于图像传感器像素阵列140的正下方。此配置可致使传感器封装100A的总高度为相对较高。这是图像传感器封装100A的此第一实施例的缺点。另一缺点是边缘闪光问题。如图1A中所示,以倾斜角度进入传感器封装100A的入射光线160可从护罩玻璃110的侧反射掉,并且落到像素阵列140的边缘上。这将导致围绕由像素阵列140产生的图像的边缘的闪光(过度曝光),因此为术语边缘闪光。这是需要消除的不良效应。
第二图像传感器封装实施例
为处置边缘闪光问题,本文揭示一种改进的图像传感器封装。图1B是展示图像传感器封装100B的第二实施例的横截面图,其具有与图像传感器封装100A的第一实施例相同的组件,除在护罩玻璃110的顶表面上的组件之外,传感器封装100B的第二实施例具有遮光罩115以阻挡入射光线160。遮光罩115可由例如金属的反射材料或例如黑色光致抗蚀剂的吸收材料制成。由于此遮光罩阻挡,入射光线160将不能够如图1A中先前所示那样从护罩玻璃110的侧反射,借此消除边缘闪光。
由于RDL 120及焊球150仍位于图像传感器像素阵列140的正下方,所以传感器封装100B的第二实施例的总高度仍与传感器封装100A的第一实施例相同。因此,先前揭示的传感器封装高度过高的缺点仍未得到解决。
第三图像传感器封装实施例
为处置图像传感器封装过度高度问题,先前揭示的将像素阵列与RDL及焊球堆叠的设计通过将RDL及焊球放置到像素阵列的侧的设计得以改进。与先前揭示的堆叠封装设计相比,此类型的图像传感器封装设计可被称为扇出封装。
图2A是展示其中RDL及焊球定位到传感器像素阵列的侧的改进的图像传感器封装设计的横截面图。图像传感器封装200A的第三实施例包含具有第一表面(即,顶部或前侧表面;未标注)及第二表面(即,底部或后侧表面;未标注)的硅衬底230,其中图像传感器像素阵列240形成在硅衬底230的前侧表面上。图像传感器像素阵列240包含数个图像传感器像素;每一像素经配置以检测传入光子并相应地产生光电信号。这些像素可示范性地基于CMOS或CCD设计。环绕像素阵列240的是外围电路区245,其位于硅衬底230的前侧表面处。外围电路区245在图2A中用虚线矩形标记。由像素阵列240产生的电信号被传送到此外围电路区245中以被进一步处理。
一或若干RDL 220及焊球250位于像素阵列240的侧。焊球250也可被称为球栅阵列(BGA)250,并完全位于硅衬底230的侧,如图2A中所示。RDL 220含有金属布线,并且机械地及电耦合到焊球250。更具体来说,RDL 220包含第一表面(即,顶部或前侧表面;未标注)及第二表面(即,底部或后侧表面;未标注),其中RDL 220在RDL 220的后侧表面处耦合到焊球250。护罩玻璃210耦合到RDL 220的前侧表面,并且位于像素阵列240的正上方,如图2A中所示。
当焊球250安装在印刷电路板(PCB;未展示)上时,将通过焊球250在RDL 220与PCB之间建立电耦合。至关重要的是,一或若干金凸块280及金凸块触点285建立RDL 220与外围电路区245之间的电耦合。因此,通过焊球250、RDL 220、金凸块280及金凸块触点285在PCB与外围电路区245之间建立电连接。金凸块280及其相关联的金凸块触点285如此命名是因为凸块通常由金制成,金是良导体。然而,也可使用具有类似良好导电性的其它材料来建立RDL 220与外围电路区245之间的电耦合。
一或数个焊接掩模助焊剂(SMF)270、盖(CV)层265及喷射胶260提供图像传感器封装200A的各个部件之间的机械结合及电绝缘。SMF 270由绝缘材料(例如,漆或某些聚合物)制成。如图2A中所示,其环绕金凸块280、RDL 220及焊球250的部分,以便提供这些部件的电绝缘。此外,喷射胶260可由绝缘材料制成。其环绕金凸块280的部分以提供电绝缘,并且还结合到SMF 270以提供机械耦合以将硅衬底230连接到RDL 220及焊球250。最后,CV层265可由绝缘材料制成。其结合到护罩玻璃210及RDL 220两者上以提供这两个部件之间的机械耦合。
护罩玻璃210位于像素阵列240的正上方,其间具有间隙。归因于CV层265、SMF 270及喷射胶260的定位,如图2A中所示,这三个部件一起充当坝状物,以便将护罩玻璃210固持在像素阵列240之上及上方。
重要的是,RDL 220及焊球250位于硅衬底230的侧。应了解,焊球250完全在硅衬底230的侧。焊球250的任何部分都不叠覆在硅衬底230或像素阵列204的上方或下方。还应了解,RDL 220的任何部分都不叠覆在像素阵列240的上方或下方。与先前如图1A及1B中所示的图像传感器封装100A及100B相对照,此位置关系有助于减小图像传感器封装200A的整体高度。
第四图像传感器封装实施例
图2B是展示图像传感器封装200B的第四实施例的横截面图,其具有与图像传感器封装200A的第三实施例相同的组件,除护罩玻璃210直接结合到RDL 220及SMF 270,而不像图像传感器封装200A中那样使用CV层265。RDL 220内存在非金属部件,并且SMF 270可完全是非金属的。这些部件可经设计以具有粘合性质以将其直接耦合到护罩玻璃210。与图2A相比较,应了解,现在只有SMF 270及喷射胶260充当坝状物以将护罩玻璃210固持在像素阵列240之上及上方。不再使用图2A中的CV层265。与图2A中的图像传感器封装200A相比,这有助于进一步减小图像传感器封装200B的整体高度。
扇出图像传感器封装中的边缘闪光问题
扇出图像传感器封装(例如,先前在图2A及2B中揭示的图像传感器封装200A及200B的第三及第四实施例)遭受潜在的边缘闪光问题。图3A及3B分别是展示图像传感器封装200A及200B的第三实施例及第四实施例的边缘闪光效应的横截面图。
如图3A中所示,以倾斜角进入图像传感器封装200A的第三实施例的入射光线300可在由CV层265、SMF 270及喷射胶260组成的堆叠结构的侧壁310反射。光线300被反射并落在像素阵列240的边缘上,如由图3A中的带箭头线所示。这将导致由像素阵列240产生的图像的边缘周围的闪光。需要消除所述不期望的边缘闪光效应。应了解,侧壁310与像素阵列240的边缘之间的距离是此边缘闪光现象的一个因素。窄的距离(例如75微米或更小)将增加边缘闪光效应的可能性。使此窄的距离更宽(例如,达到140微米或以上)将有助于减小或消除边缘闪光效应。然而,加宽距离也将增加图像传感器封装200A的横向大小,并且可能被认为是不合需要的。
类似地,在图3B中,以倾斜角进入图像传感器封装200B的第四实施例的入射光线300可在由SMF 270及喷射胶260组成的堆叠结构的侧壁320反射。光线300被反射并落在像素阵列240的边缘上,如由图3B中的带箭头线所示。这也将导致由像素阵列240产生的图像的边缘周围的闪光。类似于图像传感器封装200A的情形,当侧壁320与像素阵列240的边缘之间的距离为75微米或更小时,此边缘闪光更有可能发生。将此距离增加到140微米或以上将减小或消除边缘闪光,但也将不期望地增加图像传感器封装200B的横向大小。
第五图像传感器封装实施例
为处置边缘闪光问题,对扇出图像传感器封装进行改进。图4A是展示图像传感器封装400A的第五实施例的横截面侧视图,图像传感器封装400A具有减少边缘闪光效应的暗材料侧壁490。图像传感器封装400A的第五实施例是如先前在图2A中揭示的图像传感器200A的第三实施例的改进。图4A中许多部件的编号类似于图2A。举例来说,图4A中的护罩玻璃编号为410,类似于图2A中编号为210。类似地,图4A展示RDL 420,硅衬底430、像素阵列440、外围电路区445、焊球450、喷射胶460、CV层465、SMF 470、金凸块480及金凸块触点485。这些部件中的每一者分别与图2A中的对应等同部件相关,即,RDL 220、硅衬底230、像素阵列240、外围电路区245、焊球250、喷射胶260、CV层265、SMF 270、金凸块280及金凸块触点285。图4A中的上述各个部件彼此具有大体上相同的关系,并且执行与图2A中的对应等同部件大体上相同的功能。
重要的是,RDL 420及焊球450位于硅衬底430的侧。应了解,焊球450完全在硅衬底430的侧。焊球450的任何部分都不叠覆在硅衬底430或像素阵列440的上方或下方。还应了解,RDL 420的任何部分都不叠覆在像素阵列440的上方或下方。与先前如图1A及1B中所示的图像传感器封装100A及100B相对照,此位置关系有助于减小图像传感器封装400A的整体高度。
护罩玻璃410位于像素阵列440的正上方,其间具有间隙。归因于CV层465、SMF 470及喷射胶460的定位,这三个部件一起充当坝状物以将护罩玻璃410固持在像素阵列440之上及上方。此空间功能关系与先前在图2A及3A中揭示的空间功能关系相同。重要的是,CV层465、SMF 470及喷射胶460形成侧壁,如果保留原样并且没有某种类型的覆盖或修改,将倾向于将入射光线反射到像素阵列440的边缘上。此侧壁未在图4A中标记,但是可看作是图3A中的部件310。
如图4A中所示,施加暗材料层490以覆盖此侧壁的一部分或全部。此暗材料层490部分用于减少或防止入射光线300(参见图3A)从此暗材料层490反射以落到像素阵列440的边缘。因此,将减少或消除边缘闪光。
黑色材料层490可由有机黑色材料制成,例如黑色光致抗蚀剂(一种类型的聚合物或树脂)。其也可为具有低反射表面的金属物质。在实施例中,暗材料层具有1%或更小的反射率。在另一实施例中,暗材料层490具有足够的厚度以便具有此低反射率值。
第六图像传感器封装实施例
图4B是展示图像传感器封装400B的第六实施例的横截面侧视图,图像传感器封装400B具有减小边缘闪光效应的暗材料侧壁490。图像传感器封装400B的第六实施例是如先前在图2B中揭示的图像传感器200B的第四实施例的改进。图像传感器封装400B的第六实施例具有与图像传感器封装400A的第五实施例相同的组件,除护罩玻璃410直接结合到RDL420及SMF 470,而不像在图像传感器封装400A中那样使用CV层465。在RDL 420内存在非金属组件。SMF 470可完全是非金属的。这两个部件可被设计为具有足够的粘合性质以便将其直接耦合到护罩玻璃410。与图4A中的图像传感器封装400A相比,应了解,在图像传感器封装400B中,仅SMF 470及喷射胶460现在一起充当坝状物以将护罩玻璃410固持在像素阵列440之上及上方。不再使用如图4A中所示的CV层465。与图4A中的图像传感器封装400A相比,这有助于进一步减小图像传感器封装400B的整体高度。
如先前提及,归因于SMF 470及喷射胶460的定位,这两个部件充当坝状物以将护罩玻璃410固持在像素阵列440之上及上方。此空间功能关系与先前在图2B及3B中揭示的空间功能关系相同。重要的是,SMF 470及喷射胶460形成侧壁,如果保留原样并且没有某种类型的覆盖或修改,将倾向于将入射光线反射到像素阵列440的边缘上。此侧壁未在图4B中标记,但是可看作是图3B中的部件320。
如图4B中所示,施加暗材料层490以覆盖此侧壁的一部分或全部。此暗材料层490部分用于减少或防止入射光线300(参见图3B)从暗材料层490反射且落到像素阵列440的边缘。因此,将减少或消除边缘闪光。
暗材料层490可由有机黑色材料制成,例如黑色光致抗蚀剂。其也可为具有低反射表面的金属物质。在实施例中,暗材料层具有1%或更小的反射率。在另一实施例中,暗材料层490具有足够的厚度以便具有此低反射率值。
不希望本发明的所说明的实例的以上描述(包含摘要中所描述的内容)为穷尽性或将本发明限于所揭示的精确形式。尽管本文描述本发明的特定实例是出于说明性目的,但相关领域的技术人员将认识到,在本发明范围内各种修改是可能的。
依据以上详细描述可对本发明做出这些修改。所附权利要求书中使用的术语不应解释为将本发明限于本说明书中所揭示的特定实例。而是,本发明的范围全部由所附权利要求书确定,所附权利要求书应根据权利要求解释的既定原则来解释。
Claims (11)
1.一种图像传感器封装,其包括:
(a)硅衬底,其包含第一衬底表面,及与所述第一衬底表面相对的第二衬底表面;
(b)图像传感器像素阵列,其形成在所述硅衬底上并位于所述第一衬底表面处;
(c)外围电路区,其形成在所述硅衬底上的所述图像传感器像素阵列周围,并位于所述第一衬底表面处;
(d)再分布层RDL,其电耦合到所述外围电路区,其中所述RDL包含第一RDL表面和与所述第一RDL表面相对的第二RDL表面;
(e)至少一个焊球,其电耦合到所述第二RDL表面,其中所述焊球位于所述硅衬底的侧边,所述焊球的任何部分都不叠覆在所述硅衬底的上方且所述焊球的任何部分都不叠覆在所述硅衬底的下方;及
(f)护罩玻璃,其直接结合到所述第一RDL表面,其中所述护罩玻璃定位在所述图像传感器像素阵列的正上方且其中所述RDL安置于所述图像传感器像素阵列的侧边;
(g)绝缘材料层,其结合到所述第二RDL表面;
(h)粘合剂层,其致使所述RDL粘附到所述硅衬底;其中所述粘合剂层结合到所述绝缘材料层且结合到所述硅衬底的所述第一衬底表面;
其中所述第一RDL表面面对的方向与所述第一衬底表面面对的方向相同;且其中所述第二RDL表面面对的方向与所述第二衬底表面面对的方向相同;以及
其中所述绝缘材料层及所述粘合剂层形成位于所述第一衬底表面上的坝状物以将所述护罩玻璃固持在所述图像传感器像素阵列之上及上方,且所述坝状物具有面向所述图像传感器像素阵列的侧壁;及
所述图像传感器封装进一步包含覆盖所述坝状物的所述侧壁的至少一部分的暗材料层。
2.根据权利要求1所述的图像传感器封装,其中所述RDL通过金属构件电耦合到所述外围电路区。
3.根据权利要求1所述的图像传感器封装,其中所述RDL的任何部分都不定位在所述图像传感器像素阵列的正上方,且其中所述RDL的任何部分都不定位在所述图像传感器像素阵列的正下方。
4.根据权利要求1所述的图像传感器封装,其中所述坝状物定位到所述图像传感器像素阵列的所有侧。
5.根据权利要求1所述的图像传感器封装,其中所述暗材料层包括黑色聚合物材料。
6.根据权利要求1所述的图像传感器封装,其中所述暗材料层具有至多百分之一的反射率。
7.一种图像传感器封装,其包含:
(a)硅衬底,其包含第一衬底表面,及与所述第一衬底表面相对的第二衬底表面;
(b)图像传感器像素阵列,其形成在所述硅衬底上并位于所述第一衬底表面处;
(c)外围电路区,其形成在所述硅衬底上的所述图像传感器像素阵列周围,并位于所述第一衬底表面处;
(d)再分布层RDL,其电耦合到所述外围电路区,其中所述RDL包含第一RDL表面和与所述第一RDL表面相对的第二RDL表面;
(e)至少一个焊球,其电耦合到所述第二RDL表面,其中所述焊球位于所述硅衬底的侧边,所述焊球的任何部分都不叠覆在所述硅衬底的上方且所述焊球的任何部分都不叠覆在所述硅衬底的下方;及
(f)护罩玻璃,其耦合到所述第一RDL表面且其中所述RDL定位在所述图像传感器像素阵列的侧边;
(g)绝缘材料层,其结合到所述第二RDL表面;
(h)粘合剂层,其致使所述RDL粘附到所述硅衬底;其中所述粘合剂层结合到所述绝缘材料层且结合到所述硅衬底的所述第一衬底表面;
其中所述第一RDL表面面对的方向与所述第一衬底表面面对的方向相同;且其中所述第二RDL表面面对的方向与所述第二衬底表面面对的方向相同;
进一步包括覆盖层,其结合到所述RDL的所述第一RDL表面和所述护罩玻璃,其中所述覆盖层、所述绝缘材料层及所述粘合剂层形成位于所述第一衬底表面上的坝状物以将所述护罩玻璃固持在所述图像传感器像素阵列之上及上方,且所述坝状物具有面向所述图像传感器像素阵列的侧壁;及
所述图像传感器封装进一步包含覆盖所述坝状物的所述侧壁的至少一部分的暗材料层。
8.根据权利要求7所述的图像传感器封装,其中所述坝状物定位到所述图像传感器像素阵列的所有侧。
9.一种包括图像传感器封装的图像传感器系统,其中所述图像传感器封装包括:
(a)硅衬底,其包含第一衬底表面,及与所述第一衬底表面相对的第二衬底表面;
(b)图像传感器像素阵列,其形成在所述硅衬底上并位于所述第一衬底表面处;
(c)外围电路区,其形成在所述硅衬底上的所述图像传感器像素阵列周围,并位于所述第一衬底表面处;
(d)再分布层RDL,其电耦合到所述外围电路区,其中所述RDL包含第一RDL表面和第二RDL表面;
(e)至少一个焊球,其电耦合到所述第二RDL表面,其中所述焊球位于所述硅衬底的侧边,所述焊球的任何部分都不叠覆在所述硅衬底的上方且所述焊球的任何部分都不叠覆在所述硅衬底的下方;及
(f)护罩玻璃,其直接结合到所述第一RDL表面,其中所述护罩玻璃定位在所述图像传感器像素阵列的正上方且其中所述RDL安置于所述图像传感器像素阵列的侧边;
(g)绝缘材料层,其结合到所述第二RDL表面;
(h)粘合剂层,其致使所述RDL粘附到所述硅衬底;其中所述粘合剂层结合到所述绝缘材料层且结合到所述硅衬底的所述第一衬底表面;
其中所述第一RDL表面面对的方向与所述第一衬底表面面对的方向相同;且其中所述第二RDL表面面对的方向与所述第二衬底表面面对的方向相同;以及
其中所述绝缘材料层及所述粘合剂层形成位于所述第一衬底表面上的坝状物以将所述护罩玻璃固持在所述图像传感器像素阵列之上及上方,且所述坝状物具有面向所述图像传感器像素阵列的侧壁;及
所述图像传感器系统进一步包含覆盖所述坝状物的所述侧壁的至少一部分的暗材料层。
10.根据权利要求9所述的图像传感器系统,其中
所述RDL的任何部分都不定位在所述图像传感器像素阵列的正上方;且
所述RDL的任何部分都不定位在所述图像传感器像素阵列的正下方。
11.根据权利要求10所述的图像传感器系统,
其中所述坝状物定位到所述图像传感器像素阵列的所有侧。
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