TW201911555A - 限制封裝高度及減少邊緣光之影像感測器封裝 - Google Patents

限制封裝高度及減少邊緣光之影像感測器封裝 Download PDF

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TW201911555A
TW201911555A TW107120640A TW107120640A TW201911555A TW 201911555 A TW201911555 A TW 201911555A TW 107120640 A TW107120640 A TW 107120640A TW 107120640 A TW107120640 A TW 107120640A TW 201911555 A TW201911555 A TW 201911555A
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image sensor
rdl
pixel array
sensor package
substrate
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TWI691064B (zh
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簡維志
林蔚峰
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美商豪威科技股份有限公司
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Abstract

本發明揭示一種影像感測器封裝，其包括：一矽基板；一影像感測器像素陣列，其形成於該矽基板上；一週邊電路區域，其形成於該矽基板上之該影像感測器像素陣列周圍；一再分佈層(RDL)，其電耦合至該週邊電路區域；至少一焊球，其電耦合至該RDL；及一護罩玻璃，其耦合至該RDL。該RDL之任何部分不直接定位於該影像感測器像素陣列上方或該影像感測器像素陣列下方。該至少一焊球之任何部分不直接定位於該矽基板上方或該矽基板下方。一暗材料層經實施以防止該影像感測器像素陣列之一邊緣光效應。

Description

限制封裝高度及減少邊緣光之影像感測器封裝
本發明大體上係關於影像感測器封裝。特定言之，一影像感測器經封裝以使其再分佈層(RDL)及焊球定位至其像素陣列之側以應減小影像感測器封裝之總高度。另外，一暗材料側壁經實施以減少非所要邊緣光。
一影像感測器使用諸如光電二極體之光電組件來偵測入射光且回應性地產生電子信號。影像感測器之一主要組件係其感測器像素陣列，其中各像素包含將光子轉換為電荷載子之一光電二極體、暫時儲存電荷載子之一浮動節點及自像素傳送出電荷載子以由一週邊電路進一步處理之數個電晶體閘(轉移閘、源極隨耦器、重設電晶體等等)。一影像感測器通常與其支援元件一起封裝成一影像感測器封裝，接著，影像感測器封裝併入至諸如一行動電話相機、一消費型電子相機、一監控攝影機、一汽車駕駛員輔助裝置、一醫學成像內窺鏡等等之一成像產品中。
在以下描述中，闡述諸多特定細節以提供實例之一透徹理解。然而，熟習相關技術者將認識到，可在無一或多個特定細節之情況下或使用其他方法、組件、材料等等實踐本文所描述之技術。在其他例項下，未展示或詳細描述熟知結構、材料或操作以免使特定態樣不清楚。
參考本說明書之「實例」或「實施例」意指接合實例所描述之一特定特徵、結構或特性包含於本發明之至少一實例中。因此，出現於本說明書之各種位置中之「實例」或「實施例」未必係指相同實例。此外，特定特徵、結構或特性可依任何適合方式組合於一或多個實例中。
在本說明書中，使用若干技術術語。除非本文明確界定或其使用背景另有明確指示，否則此等術語採用其所屬技術領域之一般含義。
第一影像感測器封裝實施例
圖1A係展示一影像感測器封裝100A之一第一實施例的一橫截面側視圖。感測器封裝100A之第一實施例包含一矽基板130，其中一影像感測器像素陣列140形成於矽基板130之頂面或前側表面上。影像感測器像素陣列140包含數個影像感測器像素；各像素經組態以偵測入射光子且回應性地產生光電信號。此等像素可例示性地基於互補金屬氧化物半導體(CMOS)或電荷耦合裝置(CCD)設計。一週邊電路區域145環繞像素陣列140，週邊電路區域145在圖1A中由虛線矩形標記。將由像素陣列140產生之電信號傳送至此週邊電路區域145中以被進一步處理。含有金屬佈線之一再分佈層(RDL)120位於矽基板130之底面或後側表面處。一貫穿矽通路(TSV) 180連接以提供矽基板之前側表面處之週邊電路區域145與矽基板之後側表面處之RDL 120之間之一電耦合。焊球150連接(例如，電耦合)至RDL 120。當焊球150安裝於一印刷電路板(PCB，圖1A中未展示)上時，將在RDL 120與PCB之間建立電耦合。壩狀物170位於矽基板130之前側表面上。一護罩玻璃110位於壩狀物170之頂部上。
應瞭解，在影像感測器封裝100A之此第一實施例中，RDL 120及焊球150直接位於影像感測器像素陣列140下方。此組態可導致感測器封裝100A之總高度相對較高。此係影像感測器封裝100A之此第一實施例之一缺點。另一缺點係一邊緣光問題。如圖1A中所展示，依一傾斜角進入感測器封裝100A之一入射光線160可自護罩玻璃110之側反射且落至像素陣列140之邊緣上。此將導致由像素陣列140產生之一影像之邊緣周圍之光斑(曝光過度)，因此為術語「邊緣光」。此係需要消除之一非所要效應。
第二影像感測器封裝實施例
為應對邊緣光問題，本文揭示一種改良之影像感測器封裝。圖1B係展示影像感測器封裝100B之一第二實施例的一橫截面圖，除在護罩玻璃110之頂面上，感測器封裝100B之第二實施例具有阻擋入射光線160之一遮光板115之外，影像感測器封裝100B具有相同於影像感測器封裝100A之第一實施例之組件。遮光板115可由諸如一金屬之一反射材料或諸如一黑色光阻劑之一吸收材料製成。由於此遮光板阻擋，入射光線160將無法如先前圖1A中所展示般自護罩玻璃110之側反射，藉此消除邊緣光。
由於RDL 120及焊球150仍直接位於影像感測器像素陣列140下方，所以感測器封裝100B之第二實施例之總高度仍相同於感測器封裝100A之第一實施例。因此，先前所揭示之感測器封裝過高缺點仍未解決。
第三影像感測器封裝實施例
為應對影像感測器封裝過高問題，藉由將RDL及焊球放置至像素陣列之側之一設計來改良先前所揭示之將像素陣列與RDL及焊球堆疊之設計。與先前所揭示之堆疊封裝設計相比，此類型之影像感測器封裝設計可指稱一扇出封裝。
圖2A係展示具有定位至一感測器像素陣列之側之RDL及焊球之一改良影像感測器封裝設計的一橫截面圖。影像感測器封裝200A之一第三實施例包含具有一第一表面(即，頂面或前側表面；圖中未標記)及一第二表面(即，底面或後側表面；圖中未標記)之一矽基板230，其中一影像感測器像素陣列240形成於矽基板230之前側表面上。影像感測器像素陣列240包含數個影像感測器像素；各像素經組態以偵測入射光子且因此產生光電信號。此等像素可例示性地基於CMOS或CCD設計。一週邊電路區域245環繞像素陣列240，週邊電路區域245位於矽基板230之前側表面處。週邊電路區域245在圖2A中由虛線矩形標記。將由像素陣列240產生之電信號傳送至此週邊電路區域245中以被進一步處理。
一或若干RDL 220及焊球250位於像素陣列240之側。焊球250亦可指稱球柵陣列(BGA) 250且完全位於矽基板230之側，如圖2A中所展示。RDL 220含有金屬佈線且機械及電耦合至焊球250。更具體而言，RDL 220包含一第一表面(即，頂面或前側表面；圖中未標記)及一第二表面(即，底面或後側表面；圖中未標記)，其中RDL 220在RDL 220之後側表面處耦合至焊球250。一護罩玻璃210耦合至RDL 220之前側表面且直接位於像素陣列240上方，如圖2A中所展示。
當焊球250安裝於一印刷電路板(PCB；圖中未展示)上時，將透過焊球250在RDL 220與PCB之間建立電耦合。至關重要的是，一或若干金凸塊280及金凸塊接點285建立RDL 220與週邊電路區域245之間之電耦合。因此，透過焊球250、RDL 220、金凸塊280及金凸塊接點285在PCB與週邊電路區域245之間建立一電連接。金凸塊280及其相關聯之金凸塊接點285如此命名之原因係凸塊通常由為一良導體之金製成。然而，亦可使用具有類似良好導電性之其他材料來建立RDL 220與週邊電路區域245之間之電耦合。
一或數個焊罩助熔劑(SMF) 270、覆蓋(CV)層265及噴射膠260提供影像感測器封裝200A之各種部件之間之機械接合及電絕緣。SMF 270由一絕緣材料(例如漆或特定聚合物)製成。如圖2A中所展示，SMF 270環繞金凸塊280、RDL 220及焊球250之部分以提供此等部件之電絕緣。此外，噴射膠260可由一絕緣材料製成。噴射膠260環繞金凸塊280之部分以提供電絕緣，且亦接合至SMF 270以提供一機械耦合以將矽基板230連接至RDL 220及焊球250。最後，CV層265可由一絕緣材料製成。CV層265結合至護罩玻璃210及RDL 220兩者以提供此兩個部件之間之一機械耦合。
護罩玻璃210直接位於像素陣列240上方，其等之間具有一間隙。歸因於CV層265、SMF 270及噴射膠260之定位，如圖2A中所展示，此三個部件一起充當一壩狀物以使護罩玻璃210保持於高處及像素陣列240上方。
重要的是，RDL 220及焊球250位於矽基板230之側。應瞭解，焊球250完全在矽基板230之側。焊球250之任何部分不疊覆於矽基板230或像素陣列204上方或矽基板230或像素陣列204下方。亦應瞭解，RDL 220之任何部分不疊覆於像素陣列240上方或像素陣列240下方。與先前圖1A及圖1B中所展示之影像感測器封裝100A及100B相比，此位置關係有助於減小影像感測器封裝200A之總高度。
第四影像感測器封裝實施例
圖2B係展示影像感測器封裝200B之一第四實施例的一橫截面圖，除護罩玻璃210直接接合至RDL 220及SMF 270，無需如同影像感測器封裝200A般使用CV層265之外，影像感測器封裝200B具有相同於影像感測器封裝200A之第三實施例之組件。RDL 220內存在非金屬組件且SMF 270可完全為非金屬的。此等部件可經設計以具有黏合性來將其等直接耦合至護罩玻璃210。應瞭解，與圖2A相比，現僅有SMF 270及噴射膠260充當一壩狀物以使護罩玻璃210保持於高處及像素陣列240上方。不再使用圖2A中之CV層265。與圖2A中之影像感測器封裝200A相比，此有助於進一步減小影像感測器封裝200B之總高度。
扇出影像感測器封裝中之邊緣光問題
扇出影像感測器封裝(例如先前圖2A及圖2B中所揭示之影像感測器封裝200A及200B之第三實施例及第四實施例)面臨潛在邊緣光問題。圖3A及圖3B係分別展示影像感測器封裝200A及200B之第三實施例及第四實施例之一邊緣光效應的橫截面圖。
如圖3A中所展示，依一傾斜角進入影像感測器封裝200A之第三實施例之一入射光線300可自由CV層265、SMF 270及噴射膠260組成之一堆疊結構之一側壁310反射。光線300被反射且落至像素陣列240之邊緣上，如由圖3A中之箭頭線所展示。此將導致由像素陣列240產生之一影像之邊緣周圍之一光斑。需要消除此非所要邊緣光效應。應瞭解，側壁310與像素陣列240之邊緣之間之距離係此邊緣光現象之一成因。一窄距離(例如75微米或更小)將增加邊緣光效應之可能性。使此窄距離變寬(例如，達到140微米或更大)將有助於減少或消除邊緣光效應。然而，加寬距離亦會增大影像感測器封裝200A之橫向大小且會被視為不可取的。
類似地，在圖3B中，依一傾斜角進入影像感測器封裝200B之第四實施例之一入射光線300可自由SMF 270及噴射膠260組成之一堆疊結構之一側壁320反射。光線300被反射且落至像素陣列240之邊緣上，如由圖3B中之箭頭線所展示。此亦將導致由像素陣列240產生之一影像之邊緣周圍之一光斑。類似於影像感測器封裝200A之情形，此邊緣光更可能發生於側壁320與像素陣列240之邊緣之間之距離係75微米或更小時。將此距離增大至140微米或更大將減少或消除邊緣光，但亦會非所要地增大影像感測器封裝200B之橫向大小。
第五影像感測器封裝實施例
應改良扇出影像感測器封裝以應對邊緣光問題。圖4A係展示影像感測器封裝400A之一第五實施例的一橫截面側視圖，影像感測器封裝400A具有減少邊緣光效應之一暗材料側壁490。影像感測器封裝400A之第五實施例係相較於先前圖2A中所揭示之影像感測器200A之第三實施例之一改良方案。圖4A中諸多部件之編號類似於圖2A。舉例而言，圖4A中將一護罩玻璃編號為410，類似於圖2A之210。類似地，圖4A展示一RDL 420、一矽基板430、一像素陣列440、一週邊電路區域445、焊球450、噴射膠460、一CV層465、SMF 470、金凸塊480及金凸塊接點485。此等部件之各者分別相關於圖2A中之其對應部件，即，RDL 220、矽基板230、像素陣列240、週邊電路區域245、焊球250、噴射膠260、CV層265、SMF 270、金凸塊280及金凸塊接點285。圖4A中之上述各種部件彼此具有實質上相同關係且執行實質上相同於圖2A中之其對應部件之功能。
重要的是，RDL 420及焊球450位於矽基板430之側。應瞭解，焊球450完全在矽基板430之側。焊球450之任何部分不疊覆於矽基板430或像素陣列440上方或矽基板430或像素陣列440下方。亦應瞭解，RDL 420之任何部分不疊覆於像素陣列440上方或像素陣列440下方。與先前圖1A及圖1B中所展示之影像感測器封裝100A及100B相比，此位置關係有助於減小影像感測器封裝400A之總高度。
護罩玻璃410直接位於像素陣列440上方，其等之間具有一間隙。歸因於CV層465、SMF 470及噴射膠460之定位，此三個部件一起充當一壩狀物以使護罩玻璃410保持於高處及像素陣列440上方。此空間函數關係相同於先前圖2A及3A中所揭示之空間函數關係。重要的是，CV層465、SMF 470及噴射膠460形成一側壁，其若保持原樣且無某種類型之覆蓋或修改，則會易於將入射光線反射至像素陣列440之邊緣上。此側壁未在圖4A中被標記，但可被視為圖3A中之部件310。
如圖4A中所展示，施加一暗材料層490以覆蓋此側壁之部分或全部。此暗材料層490用於部分減少或防止入射光線300 (參閱圖3A)自其反射而落至像素陣列440之邊緣上。因此，將減少或消除邊緣光。
暗材料層490可由例如一黑色光阻劑(一類型之聚合物或樹脂)之一有機黑色材料製成。其亦可為具有一低反射表面之一金屬物質。在一實施例中，暗材料層具有1%或更小之一反射率。在另一實施例中，暗材料層490具有足以具有此一低反射率值之厚度。
第六影像感測器封裝實施例
圖4B係展示影像感測器封裝400B之一第六實施例的一橫截面側視圖，影像感測器封裝400B具有減少邊緣光效應之一暗材料側壁490。影像感測器封裝400B之第六實施例係相較於先前圖2B中所揭示之影像感測器200B之第四實施例之一改良方案。除護罩玻璃410直接接合至RDL 420及SMF 470，無需如同影像感測器封裝400A般使用CV層465之外，影像感測器封裝400B之第六實施例具有相同於影像感測器封裝400A之第五實施例之組件。RDL 420內存在非金屬組件。SMF 470可完全為非金屬的。此兩個部件可經設計以具有足以將其等直接耦合至護罩玻璃410之黏合性。應瞭解，與圖4A中之影像感測器封裝400A相比，在影像感測器封裝400B中，現僅有SMF 470及噴射膠460一起充當一壩狀物以使護罩玻璃410保持於高處及像素陣列440上方。不再使用圖4A中所展示之CV層465。與圖4A中之影像感測器封裝400A相比，此有助於進一步減小影像感測器封裝400B之總高度。
如先前所提及，歸因於SMF 470及噴射膠460之定位，此兩個部件充當一壩狀物以使護罩玻璃410保持於高處及像素陣列440上方。此空間函數關係相同於先前圖2B及圖3B中所揭示之空間函數關係。重要的是，SMF 470及噴射膠460形成一側壁，其若保持原樣且無某種類型之覆蓋或修改，則會易於將入射光線反射至像素陣列440之邊緣上。此側壁未在圖4B中被標記，但可被視為圖3B中之部件320。
如圖4B中所展示，施加一暗材料層490以覆蓋此側壁之部分或全部。此暗材料層490用於部分減少或防止入射光線300 (參閱圖3B)自其反射而落至像素陣列440之邊緣上。因此，將減少或消除邊緣光。
暗材料層490可由例如一黑色光阻劑之一有機黑色材料製成。其亦可為具有一低反射表面之一金屬物質。在一實施例中，暗材料層具有1%或更小之一反射率。在另一實施例中，暗材料層490具有足以具有此一低反射率值之厚度。
本發明之繪示實例之以上描述(其包含[中文]中所描述之內容)不意欲具窮舉性或使本發明受限於所揭示之精確形式。儘管本文出於繪示目的而描述本發明之特定實例，但熟習相關技術者將認識到，可在本發明之範疇內進行各種修改。
可鑑於以上詳細描述來對本發明作出此等修改。以下申請專利範圍中所使用之術語不應被解釋為使本發明受限於本說明書中所揭示之特定實例。確切而言，本發明之範疇完全取決於應根據申請專利範圍解釋之既定原則來解釋之以下申請專利範圍。
100A‧‧‧影像感測器封裝
100B‧‧‧影像感測器封裝
110‧‧‧護罩玻璃
115‧‧‧遮光板
120‧‧‧再分佈層(RDL)
130‧‧‧矽基板
140‧‧‧影像感測器像素陣列
145‧‧‧週邊電路區域
150‧‧‧焊球
160‧‧‧入射光線
170‧‧‧壩狀物
180‧‧‧貫穿矽通路(TSV)
200A‧‧‧影像感測器封裝
200B‧‧‧影像感測器封裝
210‧‧‧護罩玻璃
220‧‧‧RDL
230‧‧‧矽基板
240‧‧‧影像感測器像素陣列
245‧‧‧週邊電路區域
250‧‧‧焊球
260‧‧‧噴射膠
265‧‧‧覆蓋(CV)層
270‧‧‧焊罩助熔劑(SMF)
280‧‧‧金凸塊
285‧‧‧金凸塊接點
300‧‧‧入射光線
310‧‧‧側壁
320‧‧‧側壁
400A‧‧‧影像感測器封裝
400B‧‧‧影像感測器封裝
410‧‧‧護罩玻璃
420‧‧‧RDL
430‧‧‧矽基板
440‧‧‧像素陣列
445‧‧‧週邊電路區域
450‧‧‧焊球
460‧‧‧噴射膠
465‧‧‧CV層
470‧‧‧SMF
480‧‧‧金凸塊
485‧‧‧金凸塊接點
490‧‧‧暗材料層
參考以下諸圖來描述本發明之非限制性及非窮舉性實例，其中除非另有規定，否則相同元件符號係指所有各種視圖中之相同部件。
圖1A係展示在一感測器像素陣列下方具有一再分佈層及焊球之一影像感測器封裝之一第一實施例的一橫截面側視圖。
圖1B係展示具有減少邊緣光之一護罩玻璃遮光板之一影像感測器封裝之一第二實施例的一橫截面圖。
圖2A係展示具有定位至一感測器像素陣列之側之再分佈層及焊球之一影像感測器封裝之一第三實施例的一橫截面圖。
圖2B係展示具有定位至一感測器像素陣列之側之再分佈層及焊球之一應減小高度影像感測器封裝之一第四實施例的一橫截面圖。
圖3A及圖3B係分別展示一影像感測器封裝之第三實施例及第四實施例之一邊緣光效應的橫截面圖。
圖4A係展示具有減少邊緣光效應之一暗材料側壁之一影像感測器封裝之一第五實施例的一橫截面側視圖。
圖4B係展示具有減少邊緣光效應之一暗材料側壁之一影像感測器封裝之一第六實施例的一橫截面側視圖。
對應元件符號指示所有若干視圖中之對應組件。熟習技術者應瞭解，圖中之元件出於簡單及清楚之目的而繪示且未必按比例繪製。舉例而言，圖中一些元件之尺寸可相對於其他元件放大以有助於促進本發明之各種實施例之理解。此外，通常不描繪在一商業上可行實施例中有用或必需之常見但熟知之元件以促成本發明之此等各種實施例之無障礙觀看。

Claims (20)

  1. 一種影像感測器封裝，其包括： (a)一矽基板，其包含一第一基板表面及與該第一基板表面對置之一第二基板表面； (b)一影像感測器像素陣列，其形成於該矽基板上且定位於該第一基板表面處； (c)一週邊電路區域，其形成於該矽基板上之該影像感測器像素陣列周圍且定位於該第一基板表面處； (d)一再分佈層(RDL)，其電耦合至該週邊電路區域； (e)至少一焊球，其電耦合至該RDL；及 (f)一護罩玻璃，其耦合至該RDL； 其中該RDL包含一第一RDL表面及與該第一RDL表面對置之一第二RDL表面；其中該第一RDL表面面向相同於該第一基板表面之方向；且其中該第二RDL表面面向相同於該第二基板表面之方向。
  2. 如請求項1之影像感測器封裝，其中該至少一焊球電耦合至該第二RDL表面；且其中該護罩玻璃耦合至該第一RDL表面且直接定位於該影像感測器像素陣列上方。
  3. 如請求項2之影像感測器封裝，其中該RDL透過一金屬構件電耦合至該週邊電路區域。
  4. 如請求項2之影像感測器封裝，其中該RDL之任何部分不直接定位於該影像感測器像素陣列上方，且其中該RDL之任何部分不直接定位於該影像感測器像素陣列下方。
  5. 如請求項4之影像感測器封裝，其中該至少一焊球之任何部分不直接定位於該矽基板下方，且其中該至少一焊球之任何部分不直接定位於該矽基板上方。
  6. 如請求項5之影像感測器封裝，其進一步包含接合至該RDL之一絕緣材料層。
  7. 如請求項6之影像感測器封裝，其進一步包含導致該RDL黏合至該矽基板之一黏合層；其中該黏合層接合至該絕緣材料層及該矽基板之該第一基板表面。
  8. 如請求項7之影像感測器封裝，其中該絕緣材料層及該黏合層形成定位於該第一基板表面上且定位至該影像感測器像素陣列之所有側之一壩狀物；且其中該壩狀物具有面向該影像感測器像素陣列之一側壁。
  9. 如請求項8之影像感測器封裝，其進一步包含覆蓋該壩狀物之該側壁之至少一部分之一暗材料層。
  10. 如請求項9之影像感測器封裝，其中該暗材料層包括一黑色聚合物材料。
  11. 如請求項9之影像感測器封裝，其中該暗材料層具有至多1%之一反射率。
  12. 如請求項8之影像感測器封裝，其進一步包含接合至該RDL之該第一RDL表面之一覆蓋層。
  13. 如請求項12之影像感測器封裝，其中該覆蓋層、該絕緣材料層及該黏合層形成定位於該第一基板表面上且定位至該影像感測器像素陣列之所有側之一壩狀物；且其中該壩狀物具有面向該影像感測器像素陣列之一側壁。
  14. 如請求項13之影像感測器封裝，其進一步包含覆蓋該壩狀物之該側壁之至少一部分之一暗材料層。
  15. 一種影像感測器系統，其包括一影像感測器封裝，其中該影像感測器封裝包含： (a)一矽基板，其包含一第一基板表面及與該第一基板表面對置之一第二基板表面； (b)一影像感測器像素陣列，其形成於該矽基板上且定位於該第一基板表面處； (c)一週邊電路區域，其形成於該矽基板上之該影像感測器像素陣列周圍且定位於該第一基板表面處； (d)一再分佈層(RDL)，其電耦合至該週邊電路區域； (e)至少一焊球，其電耦合至該RDL；及 (f)一護罩玻璃，其耦合至該RDL； 其中該RDL包含一第一RDL表面及一第二RDL表面；其中該第一RDL表面面向相同於該第一基板表面之方向；且其中該第二RDL表面面向相同於該第二基板表面之方向。
  16. 如請求項15之影像感測器系統，其中該至少一焊球電耦合至該第二RDL表面；且其中該護罩玻璃耦合至該第一RDL表面且直接定位於該影像感測器像素陣列上方。
  17. 如請求項16之影像感測器系統，其中 該RDL之任何部分不直接定位於該影像感測器像素陣列上方； 該RDL之任何部分不直接定位於該影像感測器像素陣列下方； 該至少一焊球之任何部分不直接定位於該矽基板下方；且 該至少一焊球之任何部分不直接定位於該矽基板上方。
  18. 如請求項17之影像感測器系統，其進一步包含： (a)一絕緣材料層，其接合至該RDL； (b)一黏合層，其導致該RDL黏合至該矽基板； 其中該黏合層接合至該絕緣材料層及該矽基板之該第一基板表面； 其中該絕緣材料層及該黏合層形成定位於該第一基板表面上且定位至該影像感測器像素陣列之所有側之一壩狀物；且 其中該壩狀物具有面向該影像感測器像素陣列之一側壁。
  19. 如請求項18之影像感測器系統，其進一步包含覆蓋該壩狀物之該側壁之至少一部分之一暗材料層。
  20. 如請求項19之影像感測器系統，其進一步包含接合至該RDL之該第一RDL表面之一覆蓋層。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI786412B (zh) * 2019-06-24 2022-12-11 元太科技工業股份有限公司 顯示裝置及其製造方法
TWI796210B (zh) * 2022-04-27 2023-03-11 力成科技股份有限公司 影像感測器封裝之切單方法及影像感測器封裝

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11310402B2 (en) * 2015-08-25 2022-04-19 Gingy Technology Inc. Image capturing device and fingerprint image capturing device
CN110797362B (zh) * 2019-11-04 2022-05-24 重庆高开清芯科技产业发展有限公司 一种图像传感芯片的封装结构以及图像传感器
US11515347B2 (en) 2020-01-20 2022-11-29 Omnivision Technologies, Inc. Dam of image sensor module having sawtooth pattern and inclined surface on its inner wall and method of making same
CN111341796A (zh) * 2020-02-26 2020-06-26 南通智通达微电子物联网有限公司 一种图像传感器的扇出型封装方法
US11520197B2 (en) 2020-05-15 2022-12-06 Omnivision Technologies, Inc. Active-pixel device assemblies with rough coating for stray-light reduction, and methods for manufacture
US11942496B2 (en) 2020-06-04 2024-03-26 Stmicroelectronics Pte Ltd Slanted glass edge for image sensor package
KR20220060380A (ko) * 2020-11-04 2022-05-11 삼성전자주식회사 이미지 센서 패키지
KR20220070766A (ko) 2020-11-23 2022-05-31 삼성전자주식회사 글래스 기판을 포함하는 이미지 센서 패키지
US20230369274A1 (en) * 2022-05-10 2023-11-16 Taiwan Semiconduction Manufacturing Co., Ltd. Integrated circuit package and method of forming same

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6885107B2 (en) * 2002-08-29 2005-04-26 Micron Technology, Inc. Flip-chip image sensor packages and methods of fabrication
TWM246802U (en) * 2003-12-02 2004-10-11 Chipmos Technologies Inc Image sensor package with glass on chip configuration
TW200637017A (en) * 2005-04-14 2006-10-16 Chipmos Technologies Inc Image sensor module package
US20080197435A1 (en) * 2007-02-21 2008-08-21 Advanced Chip Engineering Technology Inc. Wafer level image sensor package with die receiving cavity and method of making the same
CN101582435B (zh) * 2008-05-16 2012-03-14 鸿富锦精密工业（深圳）有限公司 一种影像感测晶片封装结构及其应用的相机模组
CN101996898B (zh) * 2009-08-14 2012-10-31 中芯国际集成电路制造(上海)有限公司 Cmos图像传感器及其制造方法
US8791536B2 (en) * 2011-04-28 2014-07-29 Aptina Imaging Corporation Stacked sensor packaging structure and method
KR101963809B1 (ko) * 2012-04-25 2019-03-29 삼성전자주식회사 이미지 센서 패키지
CN103000649B (zh) * 2012-11-22 2015-08-05 北京工业大学 一种cmos图像传感器封装结构及其制造方法
US9503622B2 (en) * 2014-03-10 2016-11-22 Apple Inc. Preventing artifacts due to underfill in flip chip imager assembly
TWI546913B (zh) * 2014-04-02 2016-08-21 精材科技股份有限公司 晶片封裝體及其製造方法
US9898645B2 (en) * 2015-11-17 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor device and method
US10082651B2 (en) * 2016-04-11 2018-09-25 Omnivision Technologies, Inc. Slim imager, associated system-in-package, and associated method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI786412B (zh) * 2019-06-24 2022-12-11 元太科技工業股份有限公司 顯示裝置及其製造方法
US11555951B2 (en) 2019-06-24 2023-01-17 E Ink Holdings Inc. Display device and fabrication method of the same
TWI796210B (zh) * 2022-04-27 2023-03-11 力成科技股份有限公司 影像感測器封裝之切單方法及影像感測器封裝

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