CN109309090A - 半导体元件及其制造方法 - Google Patents

半导体元件及其制造方法 Download PDF

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CN109309090A
CN109309090A CN201810467925.5A CN201810467925A CN109309090A CN 109309090 A CN109309090 A CN 109309090A CN 201810467925 A CN201810467925 A CN 201810467925A CN 109309090 A CN109309090 A CN 109309090A
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stacked structure
gan channel
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semiconductor element
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CN109309090B (zh
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陈智伟
林恒光
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Nuvoton Technology Corp
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Abstract

本发明提供一种半导体元件及其制造方法。所述半导体元件包括第一堆叠结构、第二堆叠结构、隔离层以及栅极。所述第一堆叠结构配置于基底上，其包括第一GaN通道层，配置于所述基底上，且具有氮结晶相；以及第一阻挡层，配置于所述第一GaN通道层上。所述第二堆叠结构配置于所述基底上，其包括第二GaN通道层，配置于所述基底上，且具有镓结晶相；以及第二阻挡层，配置于所述第二GaN通道层上。所述隔离层配置于所述第一堆叠结构与所述第二堆叠结构之间。所述栅极配置于所述第一堆叠结构、所述隔离层与所述第二堆叠结构上。本发明能够使得工艺步骤较为简单，且可降低制成困难度以及降低生产成本。

Description

半导体元件及其制造方法
技术领域
本发明是有关于一种半导体元件，且特别是有关于一种具有N型通道与P型通道的半导体元件及其制造方法。
背景技术
对于GaN类的半导体元件来说，由于其具有高电子迁移率、耐高压、低通道电阻以及切换快速的优点，因此已逐渐被广泛应用。在具有N型通道与P型通道的GaN类的半导体元件(例如互补式金属氧化物半导体晶体管(CMOS))中，通常是通过离子植入的方式将N型掺质与P型掺质分别植入不同的通道层中，以形成N型通道与P型通道。
然而，在进行离子植入工艺时，需要精准地将掺质植入预定区域，因此工艺困难度较高，且工艺步骤较为繁杂。此外，在植入N型掺质与P型掺质之后，N型掺质与P型掺质往往会在后续的高温工艺中产生扩散现象，导致元件效能受到影响。
发明内容
本发明提供一种半导体元件，其具有N型通道与P型通道。
本发明提供一种半导体元件的制造方法，其用以制造具有N型通道与P型通道的半导体元件。
本发明的半导体元件包括第一堆叠结构、第二堆叠结构、隔离层以及栅极。所述第一堆叠结构配置于基底上，其包括第一GaN通道层，配置于所述基底上，且具有氮结晶相；以及第一阻挡层，配置于所述第一GaN通道层上。所述第二堆叠结构配置于所述基底上，其包括第二GaN通道层，配置于所述基底上，且具有镓结晶相；以及第二阻挡层，配置于所述第二GaN通道层上。所述隔离层配置于所述第一堆叠结构与所述第二堆叠结构之间，且所述隔离层将所述第一堆叠结构及所述第二堆叠结构完全隔开。所述栅极配置于所述第一堆叠结构、所述隔离层与所述第二堆叠结构上。
在本发明的半导体元件的一实施例中，上述第一GaN通道层的厚度与所述第二GaN通道层的厚度例如实质上相同，且所述第一阻挡层的厚度与所述第二阻挡层的厚度例如实质上相同。
在本发明的半导体元件的一实施例中，更包括第一保护层与第二保护层，其中所述第一保护层配置于所述第一阻挡层上，且所述第二保护层配置于所述第二阻挡层上。
在本发明的半导体元件的一实施例中，上述第一GaN通道层的厚度与所述第二GaN通道层的厚度例如实质上相同，所述第一阻挡层的厚度与所述第二阻挡层的厚度例如实质上相同，且所述第一保护层的厚度与所述第二保护层的厚度例如实质上相同。
在本发明的半导体元件的一实施例中，更包括第一缓冲层与第二缓冲层，其中所述第一缓冲层配置于所述第一GaN通道层与所述基底之间，且所述第二缓冲层配置于所述第二GaN通道层与所述基底之间。
在本发明的半导体元件的一实施例中，上述第一GaN通道层的厚度与所述第二GaN通道层的厚度例如实质上相同，所述第一阻挡层的厚度与所述第二阻挡层的厚度例如实质上相同，且所述第一缓冲层的厚度与所述第二缓冲层的厚度例如实质上相同。
本发明的半导体元件的制造方法包括：进行第一沉积工艺，于基底上形成第一GaN通道层，其中所述第一GaN通道层具有氮结晶相；于所述第一GaN通道层上形成第一阻挡层；移除部分所述第一阻挡层与所述第一GaN通道层，以形成第一堆叠结构；进行第二沉积工艺，于所述基底上形成第二GaN通道层，其中所述第二GaN通道层具有镓结晶相；于所述第二GaN通道层上形成第二阻挡层，以构成第二堆叠结构，其中所述第一堆叠结构与所述第二堆叠结构分隔开；于所述第一堆叠结构与所述第二堆叠结构之间形成隔离层，且所述隔离层将所述第一堆叠结构及所述第二堆叠结构完全隔开；以及于所述第一堆叠结构、所述隔离层与所述第二堆叠结构上形成栅极。
在本发明的半导体元件的制造方法的一实施例中，上述第一沉积工艺例如与所述第二沉积工艺不同。
在本发明的半导体元件的制造方法的一实施例中，上述第一GaN通道层的厚度与所述第二GaN通道层的厚度例如实质上相同，且所述第一阻挡层的厚度与所述第二阻挡层的厚度例如实质上相同。
在本发明的半导体元件的制造方法的一实施例中，上述在形成所述第一阻挡层之后以及在移除部分所述第一阻挡层与所述第一GaN通道层之前，更包括于所述第一阻挡层上形成第一保护层，且在形成所述第二阻挡层之后以及在形成所述隔离层之前，更包括于所述第二阻挡层上形成第二保护层。
在本发明的半导体元件的制造方法的一实施例中，上述第一GaN通道层的厚度与所述第二GaN通道层的厚度例如实质上相同，所述第一阻挡层的厚度与所述第二阻挡层的厚度例如实质上相同，且所述第一保护层的厚度与所述第二保护层的厚度例如实质上相同。
在本发明的半导体元件的制造方法的一实施例中，上述在进行所述第一沉积工艺之前，更包括于所述基底上形成第一缓冲层，且在形成所述第一堆叠结构之后以及在进行所述第二沉积工艺之前，更包括于所述基底上形成第二缓冲层。
在本发明的半导体元件的制造方法的一实施例中，上述第一GaN通道层的厚度与所述第二GaN通道层的厚度例如实质上相同，所述第一阻挡层的厚度与所述第二阻挡层的厚度例如实质上相同，且所述第一缓冲层的厚度与所述第二缓冲层的厚度例如实质上相同。
在本发明的半导体元件的制造方法的一实施例中，上述在形成所述第一堆叠结构之后以及在进行所述第二沉积工艺之前，更包括于所述基底上形成罩幕层以覆盖所述第一堆叠结构，且在形成所述第二堆叠结构之后以及形成所述隔离层之前，更包括移除所述罩幕层。
基于上述，在本发明中，利用沉积工艺而非利用离子植入的方式来形成P型通道层与N型通道层，因此能够使得工艺步骤较为简单，且可降低制成困难度以及降低生产成本。此外，在本发明中，可通过调整工艺参数而在基底上形成具有大致相同结构的P型金属氧化物半导体晶体管与N型金属氧化物半导体晶体管，因此在后续工艺中可避免因不均匀的图案平坦度所导致的工艺不稳定，且因此无须进行额外的平坦化工艺(例如化学机械研磨工艺)。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附图式作详细说明如下。
附图说明
图1A至图1D为依照本发明实施例所绘示的半导体元件的剖面示意图。
图2为依照本发明的半导体元件的上视示意图。
附图标号
10：半导体元件
100：基底
102、114：缓冲层
104、116：GaN通道层
106、118：阻挡层
108、120：保护层
110、122：堆叠结构
112：罩幕层
124：隔离层
126：栅极
具体实施方式
图1A至图1D为依照本发明实施例所绘示的半导体元件的剖面示意图。首先，请参照图1A，提供基底100。基底100例如为硅基底、SiC基底、蓝宝石基底或GaN基底。然后，选择性地于基底100上形成缓冲层102。缓冲层102的材料例如是GaN、AlGaN或AlN。此外，缓冲层102中可掺杂有C或Fe，以增加阻值。缓冲层102的形成方法例如是进行外延成长工艺。缓冲层102的厚度例如介于1um至4um之间。接着，于缓冲层102上形成GaN通道层104。GaN通道层104的形成方法例如是进行金属有机化学气相沉积(metal organic chemical vapordeposition，MOCVD)、分子束外延(molecular beam epitaxy，MBE)等的沉积工艺。在本实施例中，通过上述的沉积工艺可使所形成的GaN通道层104具有氮结晶相。换句话说，所形成的GaN通道层104由于具有氮结晶相而属于P型通道层。
然后，于GaN通道层104上形成阻挡层106。阻挡层106的材料例如是三元的III族金属氮化物或四元的III族金属氮化物。上述三元的III族金属氮化物例如是AlInN、InGaN或AlGaN。上述四元的III族金属氮化物例如是AlInGaN。阻挡层106的形成方法例如是进行外延成长工艺。阻挡层106的厚度例如介于5nm至80nm之间。接着，选择性地于阻挡层106上形成保护层108。保护层108的材料例如是GaN。保护层108的形成方法例如是进行外延成长工艺。保护层108的厚度例如介于1nm至50nm之间。
然后，请参照图1B，进行图案化工艺，移除部分保护层108、部分阻挡层106、部分GaN通道层104与部分缓冲层102。保留下来的缓冲层102、GaN通道层104、阻挡层106与保护层108构成堆叠结构110。在上述图案化工艺中，例如是使用干式刻蚀来移除部分保护层108、部分阻挡层106、部分GaN通道层104与部分缓冲层102。接着，于基底100上形成罩幕层112。罩幕层112覆盖整个堆叠结构110与部分基底100，并暴露出后续于基底100上形成另一堆叠结构的区域。
接着，请参照图1C，于未被罩幕层112覆盖的基底100上形成缓冲层114。缓冲层114的材料以及形成方法可与缓冲层102相同。然后，于缓冲层114上形成GaN通道层116。GaN通道层116的形成方法例如是进行MOCVD、MBE等的沉积工艺。在本实施例中，通过上述的沉积工艺可使所形成的GaN通道层116具有镓结晶相。换句话说，所形成的GaN通道层116由于具有镓结晶相而属于N型通道层。
重要的是，在本实施例中，用以形成GaN通道层104的沉积工艺与用以形成GaN通道层116的沉积工艺不同，因此所形成的通道层属于相反型态的通道层。此外，在本实施例中，利用沉积工艺来形成P型通道层与N型通道层，而非利用离子植入的方式来形成相反型态的通道层，因此可以有效地简化工艺步骤以及工艺困难度，且亦可降低生产成本。另外，在本实施例中，缓冲层114(在无缓冲层114的实施例中则为GaN通道层116)利用沉积工艺形成在具有平坦表面的基底100上，因此可以确保缓冲层114(在无缓冲层114的实施例中则为GaN通道层116)以及后续形成于其上的膜层具有良好的品质。
接着，于GaN通道层116上形成阻挡层118。阻挡层118的材料以及形成方法可与阻挡层106相同。然后，选择性地于阻挡层118上形成保护层120。保护层120的材料以及形成方法可与保护层108相同。缓冲层114、GaN通道层116、阻挡层118与保护层120构成堆叠结构122。
特别一提的是，在本实施例中，在形成堆叠结构110之后，通过调整形成缓冲层114、GaN通道层116、阻挡层118与保护层120的工艺参数，可使缓冲层114、GaN通道层116、阻挡层118与保护层120的厚度分别与缓冲层102、GaN通道层104、阻挡层106与保护层108的厚度相同。换句话说，所形成的堆叠结构110与堆叠结构122可具有大致相同的构造，其差异仅在于GaN通道层104与GaN通道层116属于相反型态的通道层，因此在后续工艺中可避免因不均匀的图案平坦度所导致的工艺不稳定，且因此无须进行额外的平坦化工艺(例如化学机械研磨工艺)。
之后，请参照图1D，移除罩幕层112。在移除罩幕层112的过程中，形成缓冲层114、GaN通道层116、阻挡层118与保护层120时残留于罩幕层112上的杂质可一并被移除。然后，于基底100上形成隔离层124。隔离层124的材料例如是氧化硅、氮化硅或氮氧化硅。隔离层124的形成方法例如是先于基底100上形成隔离材料层，所述隔离材料层覆盖堆叠结构110与堆叠结构122；然后，进行平坦化工艺或回刻蚀工艺，移除堆叠结构110与堆叠结构122的表面上的隔离层材料层。在本实施例中，由于堆叠结构110与堆叠结构122可具有大致相同的构造，因此在进行上述平坦化工艺之后，可同时暴露出堆叠结构110与堆叠结构122的顶面，使得堆叠结构110的顶面、隔离层124的顶面与堆叠结构122的顶面为共平面的。如此一来，可更有利于后续工艺的进行。
之后，于堆叠结构110、隔离层124与堆叠结构122上形成栅极126，以完成本实施例的半导体元件10。图2为半导体元件10的上视示意图，即，图1D为沿图2中I-I’剖线的剖面示意图。如图1D与图2所示，栅极126越过隔离层124而配置于堆叠结构110与堆叠结构122上。如此一来，堆叠结构110与位于其上方的栅极126可构成P型金属氧化物半导体晶体管，且堆叠结构122与位于其上方的栅极126可构成N型金属氧化物半导体晶体管。也就是说，本实施例的半导体元件10为包括P型金属氧化物半导体晶体管与N型金属氧化物半导体晶体管的互补式金属氧化物半导体晶体管。
虽然本发明已以实施例揭露如上，然其并非用以限定本发明，任何所属技术领域中相关技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视权利要求所界定者为准。

Claims (11)

1.一种半导体元件，其特征在于，包括：
第一堆叠结构，配置于基底上，所述第一堆叠结构包括：
第一GaN通道层，配置于所述基底上，具有氮结晶相；以及
第一阻挡层，配置于所述第一GaN通道层上；
第二堆叠结构，配置于所述基底上，所述第二堆叠结构包括：
第二GaN通道层，配置于所述基底上，具有镓结晶相；以及
第二阻挡层，配置于所述第二GaN通道层上；
隔离层，配置于所述第一堆叠结构与所述第二堆叠结构之间，且所述隔离层将所述第一堆叠结构及所述第二堆叠结构完全隔开；以及
栅极，配置于所述第一堆叠结构、所述隔离层与所述第二堆叠结构上。
2.如权利要求1所述的半导体元件，其特征在于，所述第一GaN通道层的厚度与所述第二GaN通道层的厚度实质上相同，且所述第一阻挡层的厚度与所述第二阻挡层的厚度实质上相同。
3.如权利要求1所述的半导体元件，其特征在于，更包括第一保护层与第二保护层，其中所述第一保护层配置于所述第一阻挡层上，且所述第二保护层配置于所述第二阻挡层上。
4.如权利要求1所述的半导体元件，其特征在于，更包括第一缓冲层与第二缓冲层，其中所述第一缓冲层配置于所述第一GaN通道层与所述基底之间，且所述第二缓冲层配置于所述第二GaN通道层与所述基底之间。
5.一种半导体元件的制造方法，其特征在于，包括：
进行第一沉积工艺，于基底上形成第一GaN通道层，其中所述第一GaN通道层具有氮结晶相；
于所述第一GaN通道层上形成第一阻挡层；
移除部分所述第一阻挡层与所述第一GaN通道层，以形成第一堆叠结构；
进行第二沉积工艺，于所述基底上形成第二GaN通道层，其中所述第二GaN通道层具有镓结晶相；
于所述第二GaN通道层上形成第二阻挡层，以构成第二堆叠结构，其中所述第一堆叠结构与所述第二堆叠结构分隔开；
于所述第一堆叠结构与所述第二堆叠结构之间形成隔离层；以及
于所述第一堆叠结构、所述隔离层与所述第二堆叠结构上形成栅极。
6.如权利要求5所述的半导体元件的制造方法，其特征在于，所述隔离层将所述第一堆叠结构及所述第二堆叠结构完全隔开。
7.如权利要求5所述的半导体元件的制造方法，其特征在于，所述第一沉积工艺与所述第二沉积工艺不同。
8.如权利要求5所述的半导体元件的制造方法，其特征在于，所述第一GaN通道层的厚度与所述第二GaN通道层的厚度实质上相同，且所述第一阻挡层的厚度与所述第二阻挡层的厚度实质上相同。
9.如权利要求5所述的半导体元件的制造方法，其特征在于，在形成所述第一阻挡层之后以及在移除部分所述第一阻挡层与所述第一GaN通道层之前，更包括于所述第一阻挡层上形成第一保护层，且在形成所述第二阻挡层之后以及在形成所述隔离层之前，更包括于所述第二阻挡层上形成第二保护层。
10.如权利要求5所述的半导体元件的制造方法，其特征在于，在进行所述第一沉积工艺之前，更包括于所述基底上形成第一缓冲层，且在形成所述第一堆叠结构之后以及在进行所述第二沉积工艺之前，更包括于所述基底上形成第二缓冲层。
11.如权利要求5所述的半导体元件的制造方法，其特征在于，在形成所述第一堆叠结构之后以及在进行所述第二沉积工艺之前，更包括于所述基底上形成罩幕层以覆盖所述第一堆叠结构，且在形成所述第二堆叠结构之后以及形成所述隔离层之前，更包括移除所述罩幕层。
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