CN1091977C - 用于非整数倍频系统的时钟同步方法电路 - Google Patents

用于非整数倍频系统的时钟同步方法电路 Download PDF

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Publication number
CN1091977C
CN1091977C CN96114575A CN96114575A CN1091977C CN 1091977 C CN1091977 C CN 1091977C CN 96114575 A CN96114575 A CN 96114575A CN 96114575 A CN96114575 A CN 96114575A CN 1091977 C CN1091977 C CN 1091977C
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CN
China
Prior art keywords
clock signal
circuit
signal
frequency
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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CN96114575A
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English (en)
Chinese (zh)
Other versions
CN1152822A (zh
Inventor
R·E·布希
K·M·齐克
R·M·霍尔
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International Business Machines Corp
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International Business Machines Corp
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Publication of CN1152822A publication Critical patent/CN1152822A/zh
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Publication of CN1091977C publication Critical patent/CN1091977C/zh
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
CN96114575A 1995-11-28 1996-11-15 用于非整数倍频系统的时钟同步方法电路 Expired - Fee Related CN1091977C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US563,415 1995-11-28
US563415 1995-11-28
US08/563,415 US5691660A (en) 1995-11-28 1995-11-28 Clock synchronization scheme for fractional multiplication systems

Publications (2)

Publication Number Publication Date
CN1152822A CN1152822A (zh) 1997-06-25
CN1091977C true CN1091977C (zh) 2002-10-02

Family

ID=24250394

Family Applications (1)

Application Number Title Priority Date Filing Date
CN96114575A Expired - Fee Related CN1091977C (zh) 1995-11-28 1996-11-15 用于非整数倍频系统的时钟同步方法电路

Country Status (5)

Country Link
US (1) US5691660A (enExample)
KR (1) KR100195855B1 (enExample)
CN (1) CN1091977C (enExample)
SG (1) SG67961A1 (enExample)
TW (1) TW316342B (enExample)

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US7242229B1 (en) 2001-05-06 2007-07-10 Altera Corporation Phase locked loop (PLL) and delay locked loop (DLL) counter and delay element programming in user mode
US6791380B2 (en) * 2001-11-27 2004-09-14 Winbond Electronics Corporation Universal clock generator
US7319728B2 (en) 2002-05-16 2008-01-15 Micron Technology, Inc. Delay locked loop with frequency control
US6801070B2 (en) * 2002-05-16 2004-10-05 Micron Technology, Inc. Measure-controlled circuit with frequency control
US7515666B2 (en) * 2005-07-29 2009-04-07 International Business Machines Corporation Method for dynamically changing the frequency of clock signals
GB0622945D0 (en) * 2006-11-17 2006-12-27 Zarlink Semiconductor Inc Fractional digital PLL
CA2677655A1 (en) * 2007-05-15 2008-11-20 Chronologic Pty Ltd. Usb based synchronization and timing system
CN101751068B (zh) * 2008-12-09 2012-04-04 华为技术有限公司 一种同步时钟产生电路和方法
CN101938277B (zh) * 2010-08-12 2012-05-30 四川和芯微电子股份有限公司 倍频系统及实现倍频的方法
CN102594451A (zh) * 2012-02-23 2012-07-18 深圳市新岸通讯技术有限公司 一种测试信号的生成方法及装置
CN103064461B (zh) * 2012-12-31 2016-03-09 华为技术有限公司 一种时钟使能信号的产生方法及装置
US10146732B2 (en) * 2013-01-22 2018-12-04 Apple Inc. Time-division multiplexed data bus interface
US9413364B2 (en) * 2014-07-09 2016-08-09 Intel Corporation Apparatus and method for clock synchronization for inter-die synchronized data transfer
WO2019233571A1 (en) 2018-06-05 2019-12-12 Telefonaktiebolaget Lm Ericsson (Publ) Lo phase correction for aas with multiple rfic
CN111679714B (zh) * 2019-12-31 2022-03-11 泰斗微电子科技有限公司 跨芯片信号同步的方法、装置及芯片
EP4375790A1 (en) * 2022-11-25 2024-05-29 LX Semicon Co., Ltd. Device and method for multi-chip clock synchronization
CN116320098A (zh) * 2023-03-07 2023-06-23 北京旋极信息技术股份有限公司 一种时钟信号的生成方法、时钟装置和信号处理系统

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US4053839A (en) * 1973-05-29 1977-10-11 Knoedl Jr George Method and apparatus for the frequency multiplication of composite waves
US3970954A (en) * 1975-04-03 1976-07-20 Bell Telephone Laboratories, Incorporated Digital frequency multiplier
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US4405898A (en) * 1980-06-30 1983-09-20 International Business Machines Corporation Pseudo synchronous clocking
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Also Published As

Publication number Publication date
CN1152822A (zh) 1997-06-25
KR100195855B1 (ko) 1999-06-15
SG67961A1 (en) 1999-10-19
KR970031357A (ko) 1997-06-26
US5691660A (en) 1997-11-25
TW316342B (enExample) 1997-09-21

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GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20021002

Termination date: 20091215