CN109189141A - A kind of novel negative pressure boostrap circuit - Google Patents
A kind of novel negative pressure boostrap circuit Download PDFInfo
- Publication number
- CN109189141A CN109189141A CN201811063366.8A CN201811063366A CN109189141A CN 109189141 A CN109189141 A CN 109189141A CN 201811063366 A CN201811063366 A CN 201811063366A CN 109189141 A CN109189141 A CN 109189141A
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- Prior art keywords
- pmos tube
- negative pressure
- branch
- charge pump
- capacitor
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
- G05F1/571—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overvoltage detector
Abstract
The present invention discloses a kind of novel negative pressure boostrap circuit, belongs to technical field of integrated circuits.The novel negative pressure boostrap circuit includes two-stage charge pump, clamper branch and detection of negative pressure branch；Wherein, the output end of two-stage charge pump is connected with the gate control end of clamper branch, and the input terminal of two-stage charge pump is connected with the output end of clamper branch；The output end of detection of negative pressure branch is connected with the substrate of all PMOS tube in two-stage charge pump and clamper branch；The input terminal of clamper branch and the input terminal of detection of negative pressure branch are connected with by bootstrapping negative pressure.Two-stage charge pump is introduced to provide the initial control voltage of switching tube；Increase a detection of negative pressure branch, switch all POMS pipes according to input negative voltage value sinks to the bottom current potential, avoids N trap breakdown problem；Value is stabilized the output voltage by introducing clamper branch, it is pressure-resistant to bear the excessively high limit to avoid entire negative pressure boostrap circuit, to realize that negative voltage is precisely booted and Lossless transport.
Description
Technical field
The present invention relates to technical field of integrated circuits, in particular to a kind of novel negative pressure boostrap circuit.
Background technique
Flash is the nonvolatile memory being most widely used at present, as SAM Stand Alone Memory or as embedded IP,
It has been widely used in the fields such as data storage, Industry Control, artificial intelligence and Internet of Things.It is well known that flash is logical
Hot electron emission mechanism realizes collection and release to the floating gate charge of storage unit；Usually set inside flash chip
Sufficiently high voltage difference is generated in respect of positive and negative charge pump circuit, to reach the condition of thermionic emission, is directed to negative sense
The transmission problem of voltage.Due to being sunk to the bottom by chip p-type, the process conditions such as the limited pressure resistance of metal-oxide-semiconductor limited, negative voltage passes
It is defeated always to be a problem.Inside flash chip, transfer tube of the PMOS tube as negative pressure is often used；In order to realize more
Good chip isolation and Lossless transport, the gate control voltage of PMOS tube have to be lower than by transmission negative pressure, at this moment just need a negative pressure
Boostrap circuit generates PMOS transfer tube gate control voltage.
It is traditional negative sense boostrap circuit structure shown in Fig. 1, using a two-stage charge pump directly to input negative pressure Vin
It boots.There are a disadvantages for this circuit structure: (1) output voltage values Vout is greater than the unlatching electricity of two PMOS tube of Vin
Press Vth；(2) PMOS tube bears higher voltage stress in circuit, and the resistance to pressure request of PMOS tube is greater than Vin+2Vth+VDD.
Summary of the invention
The purpose of the present invention is to provide a kind of novel negative pressure boostrap circuits, to solve existing negative sense boostrap circuit pair
The demanding problem of PMOS tube pressure resistance.
In order to solve the above technical problems, the present invention provides a kind of novel negative pressure boostrap circuit, including two-stage charge pump, clamper
Branch and detection of negative pressure branch；Wherein,
The output end of the two-stage charge pump is connected with the gate control end of the clamper branch, the input of the two-stage charge pump
End is connected with the output end of the clamper branch；
The substrate of all PMOS tube in the output end and the two-stage charge pump of the detection of negative pressure branch and the clamper branch
It is connected；
The input terminal of the input terminal of the clamper branch and the detection of negative pressure branch is connected with by bootstrapping negative pressure.
Optionally, the two-stage charge pump includes the first PMOS tube MP1, the second PMOS tube MP2 and third PMOS tube MP3,
First capacitor C1, the second capacitor C2 and third capacitor C3；
The grid end of the first PMOS tube MP1 meets its drain terminal, and common ground voltage VSS；The grid end of the second PMOS tube MP2
Its drain terminal is connect, and connects the source of first PMOS tube and the top crown of the first capacitor C1 jointly；The third PMOS tube
The grid end of MP3 connects its drain terminal, and connects the source of the second PMOS tube MP2 and the top crown of the second capacitor C2 jointly；Institute
The source for stating third PMOS tube connects the top crown of the third capacitor C3.
Optionally, the clamper branch includes the 4th PMOS tube MP4 and the 5th PMOS tube MP5；The 4th PMOS tube MP4
It is connected with by bootstrapping negative pressure with the drain terminal of the 5th PMOS tube MP5, grid end is all connected with the output end of the two-stage charge pump,
The source of the 4th PMOS tube MP4 connects the drain terminal of the second PMOS tube MP2, and the source of the 5th PMOS tube MP5 meets institute
State the source of the second PMOS tube MP2.
Optionally, the detection of negative pressure branch includes comparator and hysteresis buffer；The positive input of the comparator
It is connected with by bootstrapping negative pressure, negative input accesses reference voltage；The output end of comparator is defeated with the hysteresis buffer
Enter end to be connected, the output end of hysteresis buffer and the first PMOS tube MP1, the second PMOS tube MP2, the third
PMOS tube MP3, the 4th PMOS tube MP4 are connected with the substrate of the 5th PMOS tube MP5.
Optionally, the turn threshold of the comparator is that -1V arrives -2.5V.
Optionally, the bottom crown of the first capacitor C1 meets clock CLK, and the bottom crown of the second capacitor C2 connects clock
The bottom crown of CLKn, the third capacitor C3 are grounded.
A kind of novel negative pressure boostrap circuit, including two-stage charge pump, clamper branch and negative pressure inspection are provided in the present invention
Survey branch；Wherein, the output end of the two-stage charge pump is connected with the gate control end of the clamper branch, the second level charge
The input terminal of pump is connected with the output end of the clamper branch；The output end of the detection of negative pressure branch and the second level charge
Pump is connected with the substrate of all PMOS tube in the clamper branch；The input terminal of the clamper branch and the detection of negative pressure branch
The input terminal on road is connected with by bootstrapping negative pressure.
Beneficial effect is: (1) compared with traditional structure, the clamper branch newly increased realizes voltage Vout to negative by bootstrapping
The accurate voltage bootstrapping for pressing a PMOS tube cut-in voltage Vth of Vin, reduces the resistance to pressure request of PMOS tube；(2) it newly increases
Detection of negative pressure branch can real-time detection Vin negative pressure value, when reach compare threshold value after, by the institute in two-stage charge pump and clamper branch
There is the N trap potential of PMOS tube to become ground voltage VSS from the operating voltage VDD of PMOS tube, is guaranteeing what negative voltage was controllably transmitted
Under the premise of, it further reduced the resistance to pressure request of the PMOS tube of transmission negative pressure.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of traditional negative pressure boostrap circuit；
Fig. 2 is the structural schematic diagram for the novel negative pressure boostrap circuit that the embodiment of the present invention one provides.
Specific embodiment
It is further detailed to a kind of novel negative pressure boostrap circuit work proposed by the present invention below in conjunction with the drawings and specific embodiments
It describes in detail bright.According to following explanation and claims, advantages and features of the invention will be become apparent from.It should be noted that attached drawing is equal
Using very simplified form and using non-accurate ratio, only to facilitate, lucidly aid in illustrating the embodiment of the present invention
Purpose.
Embodiment one
The present invention provides a kind of novel negative pressure boostrap circuit, structure is as shown in Figure 2.The novel negative pressure boostrap circuit includes
Two-stage charge pump, clamper branch and detection of negative pressure branch；Wherein, the output end output signal Vout of the two-stage charge pump is to institute
The gate control end of clamper branch is stated, the input terminal of the two-stage charge pump is connected with the output end of the clamper branch；It is described
The output end output signal Vsub of detection of negative pressure branch all PMOS tube into the two-stage charge pump and the clamper branch
Substrate；The input terminal of the input terminal of the clamper branch and the detection of negative pressure branch is connected with by bootstrapping negative pressure Vin.
Specifically, please continue to refer to Fig. 2.The two-stage charge pump include the first PMOS tube MP1, the second PMOS tube MP2 and
Third PMOS tube MP3, first capacitor C1, the second capacitor C2 and third capacitor C3.The grid end of the first PMOS tube MP1 connects its leakage
End, and common ground voltage VSS；The grid end of the second PMOS tube MP2 connects its drain terminal, and connects first PMOS tube jointly
The top crown of source and the first capacitor C1, the bottom crown incoming clock CLK of the first capacitor C1；The third PMOS tube
The grid end of MP3 connects its drain terminal, and meets the source of the second PMOS tube MP2 and the top crown of the second capacitor C2, institute jointly
The bottom crown for stating the second capacitor C2 meets clock CLKn；The source of the third PMOS tube connects the top crown of the third capacitor C3,
The bottom crown of the third capacitor C3 is grounded.
Specifically, the clamper branch includes the 4th PMOS tube MP4 and the 5th PMOS tube MP5；The 4th PMOS tube MP4
It is connected with by bootstrapping negative pressure Vin with the drain terminal of the 5th PMOS tube MP5, grid end accesses the output of the two-stage charge pump
The drain terminal of the source output voltage V1 to the second PMOS tube MP2 of the signal Vout, the 4th PMOS tube MP4 of output are held,
The source of the source output voltage V2 of the 5th PMOS tube MP5 to the second PMOS tube MP2.
The detection of negative pressure branch includes comparator and hysteresis buffer；The positive input of the comparator with booted
Negative pressure Vin is connected, and negative input accesses reference voltage Vref；The input of the output end of comparator and the hysteresis buffer
End is connected, the output end output signal Vsub to the first PMOS tube MP1 of hysteresis buffer, the second PMOS tube MP2,
The substrate of the third PMOS tube MP3, the 4th PMOS tube MP4 and the 5th PMOS tube MP5.Further, the ratio
Turn threshold compared with device is that -1V arrives -2.5V.
The specific working principle is as follows for the novel negative pressure boostrap circuit that the embodiment of the present invention one provides:
Clock CLK and CLKn first is loaded into respectively on first capacitor C1, the second capacitor C2, and the two-stage charge pump starts work
Making, the basic functional principle based on charge pump, ground voltage VSS provides initial voltage for the two-stage charge pump and inputs, and second
PMOS tube MP2, third PMOS tube MP3 and first capacitor C1, the second capacitor C2 constitute two-stage charge pump, and third capacitor C3 is as defeated
The electric capacity of voltage regulation of voltage Vout out, every grade of pump provide the voltage drop of VDD-Vth, and the initial output voltage Vout of two-stage charge pump is
VSS+Vth-2 (VDD-Vth), this is a negative value；Wherein, VDD is the operating voltage of PMOS tube, and Vth is PMOS tube
Cut-in voltage.
Voltage Vout is loaded into the gate control end of two PMOS tube in clamper branch in the present invention, two PMOS
Transfer tube is in the open state, V1 and V2 voltage value is equal with by bootstrapping negative pressure Vin, is introduced directly by bootstrapping negative pressure Vin
The grid end and drain terminal of third PMOS tube MP3, since the third PMOS tube MP3 is diode connection type, then voltage Vout quilt
1 Vth is lifted by bootstrapping negative pressure Vin, Vout is clamped to Vin+Vth, and two-stage charge pump no longer works to voltage Vout.By
It is higher than in the grid end voltage of the 4th PMOS tube MP4, the 5th PMOS tube MP5 by bootstrapping negative pressure Vin, forces the 4th PMOS tube MP4, the
Five PMOS tube MP5 are closed, and make two-stage charge pump restore to work normally, Vout voltage is restored to VSS+ Vth -2 (VDD-
Vth), the 4th PMOS tube MP4, the 5th PMOS tube MP5 are opened again；And so on, the 4th PMOS tube MP4 and the 5th PMOS tube
MP5 circulation is in opening and closing state, and the gate control voltage Vout of the 4th PMOS tube MP4 and the 5th PMOS tube MP5 are just stable
Near (Vin-Vth), precisely boot to realize to a Vth of Vin.
With being gradually reduced for Vin, when being more than a certain negative pressure point, the comparator in detection of negative pressure branch is flipped,
By signal Vsub by the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the described 4th
The substrate electric potential of PMOS tube MP4 and the 5th PMOS tube MP5 are switched to ground voltage VSS from VDD, are guaranteeing all PMOS tube
While N trap potential highest, the resistance to pressure request of PMOS tube is reduced to-(Vin-Vth) from VDD- (Vin-Vth), is further dropped
The low resistance to pressure request of PMOS tube.
The novel negative pressure boostrap circuit provided by above-mentioned analysis, the embodiment of the present invention one by newly-increased clamper branch, is born
Press detection branch, realize Vout and boot to the accurate voltage of a Vth of Vin, at the same by improving after, PMOS tube is most
The big voltage that bears is reduced to-(Vin-Vth), reduces the resistance to pressure request of PMOS tube significantly.
In the present invention, the word that the expressions such as " connection ", " connected ", " company ", " connecing " are electrical connected, unless otherwise instructed,
Then indicate direct or indirect electric connection.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (6)
1. a kind of novel negative pressure boostrap circuit, which is characterized in that including two-stage charge pump, clamper branch and detection of negative pressure branch；
Wherein,
The output end of the two-stage charge pump is connected with the gate control end of the clamper branch, the input of the two-stage charge pump
End is connected with the output end of the clamper branch；
The substrate of all PMOS tube in the output end and the two-stage charge pump of the detection of negative pressure branch and the clamper branch
It is connected；
The input terminal of the input terminal of the clamper branch and the detection of negative pressure branch is connected with by bootstrapping negative pressure.
2. novel negative pressure boostrap circuit as described in claim 1, which is characterized in that the two-stage charge pump includes the first PMOS
Pipe MP1, the second PMOS tube MP2 and third PMOS tube MP3, first capacitor C1, the second capacitor C2 and third capacitor C3；
The grid end of the first PMOS tube MP1 meets its drain terminal, and common earthing potential VSS；The grid end of the second PMOS tube MP2
Its drain terminal is connect, and connects the source of first PMOS tube and the top crown of the first capacitor C1 jointly；The third PMOS tube
The grid end of MP3 connects its drain terminal, and connects the source of the second PMOS tube MP2 and the top crown of the second capacitor C2 jointly；Institute
The source for stating third PMOS tube connects the top crown of the third capacitor C3.
3. novel negative pressure boostrap circuit as claimed in claim 2, which is characterized in that the clamper branch includes the 4th PMOS tube
MP4 and the 5th PMOS tube MP5；The drain terminal of the 4th PMOS tube MP4 and the 5th PMOS tube MP5 is and by bootstrapping negative pressure phase
Even, grid end is all connected with the output end of the two-stage charge pump, and the source of the 4th PMOS tube MP4 connects second PMOS tube
The drain terminal of MP2, the source of the 5th PMOS tube MP5 connect the source of the second PMOS tube MP2.
4. novel negative pressure boostrap circuit as claimed in claim 3, which is characterized in that the detection of negative pressure branch includes comparator
And hysteresis buffer；The positive input of the comparator is connected with by bootstrapping negative pressure, and negative input accesses reference voltage；
The output end of comparator is connected with the input terminal of the hysteresis buffer, the output end of hysteresis buffer and the first PMOS
Pipe MP1, the second PMOS tube MP2, the third PMOS tube MP3, the 4th PMOS tube MP4 and the 5th PMOS tube
The substrate of MP5 is connected.
5. novel negative pressure boostrap circuit as claimed in claim 4, which is characterized in that the turn threshold of the comparator is -1V
To -2.5V.
6. novel negative pressure boostrap circuit as claimed in claim 5, which is characterized in that when the bottom crown of the first capacitor C1 connects
Clock CLK, the bottom crown of the second capacitor C2 connect clock CLKn, the bottom crown ground connection of the third capacitor C3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811063366.8A CN109189141B (en) | 2018-09-12 | 2018-09-12 | Negative voltage bootstrap circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811063366.8A CN109189141B (en) | 2018-09-12 | 2018-09-12 | Negative voltage bootstrap circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109189141A true CN109189141A (en) | 2019-01-11 |
| CN109189141B CN109189141B (en) | 2020-06-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811063366.8A Active CN109189141B (en) | 2018-09-12 | 2018-09-12 | Negative voltage bootstrap circuit |
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| CN107179800A (en) * | 2017-07-12 | 2017-09-19 | 长沙方星腾电子科技有限公司 | A kind of internal electric source generation circuit with clamper function |
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2018
- 2018-09-12 CN CN201811063366.8A patent/CN109189141B/en active Active
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| KR100804705B1 (en) * | 2006-07-31 | 2008-02-18 | 충북대학교 산학협력단 | The low voltage electric charge pump circuit which uses the nonvloatile memory device |
| US20090153232A1 (en) * | 2007-05-25 | 2009-06-18 | Atmel Corporation | Low voltage charge pump |
| CN101272090A (en) * | 2007-07-10 | 2008-09-24 | 清华大学 | High tension charge pump circuit |
| CN106487218A (en) * | 2015-12-30 | 2017-03-08 | 无锡华润矽科微电子有限公司 | It is applied to the charge pump circuit that wireless charging receives chip |
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| CN109189141B (en) | 2020-06-12 |
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