KR100804705B1 - The low voltage electric charge pump circuit which uses the nonvloatile memory device - Google Patents

Abstract

The present invention uses a non-volatile memory device capable of adjusting the threshold voltage as a charge transfer device, thereby adjusting the threshold voltage of the charge transfer device in an electrical manner, thereby increasing the output voltage of the charge pump circuit. A low voltage charge pump circuit using an element.

The low voltage charge pump circuit using the nonvolatile memory device of the present invention includes a power supply voltage input unit for receiving a power supply voltage, a plurality of charge transfer devices connected to the power supply voltage input unit for pumping and outputting a power supply voltage, respectively, A charge pump circuit comprising a plurality of charge storage elements connected to a charge transfer element of a capacitor and a clock driver connected to generate a clock complementary to the plurality of charge storage elements. Is a non-volatile memory device including a floating gate, a control gate, a program gate node, a source and a drain, and controlling an electrical threshold voltage of the device by a voltage applied to the program gate node, wherein the control gate and the drain are directly Connected diode Electrically connected through a connection to prevent a change in the effective coupling ratio of the nonvolatile memory device by the charge storage device when the threshold voltage is adjusted through the nonvolatile memory device between the charge storage device and the charge transfer device. The transmission gate is further electrically connected.

Nonvolatile Memory, Program Gate, Threshold Voltage, Charge Pump Circuit

Description

The low voltage electric charge pump circuit which uses the nonvloatile memory device}

1 is a circuit diagram showing a conventional general charge pump circuit.

2 is a conceptual diagram of a low voltage charge pump circuit using a nonvolatile memory device according to the present invention.

3 and 4 are conceptual views illustrating one embodiment of the nonvolatile memory device of FIG. 2.

5 and 6 are conceptual views illustrating another embodiment of the nonvolatile memory device of FIG. 2.

FIG. 7 is a circuit diagram illustrating the transmission gate of FIG. 2. FIG.

<Description of the symbols for the main parts of the drawings>

10: power voltage output unit

20: charge transfer element

30: charge storage element

40: clock driver

50: transmission gate element

60 stage

The present invention relates to a charge pump circuit, and more particularly, an output voltage of a charge pump can be increased by adjusting a threshold voltage by an electrical method using a nonvolatile memory device that can electrically adjust a threshold voltage as a charge transfer device. It relates to a low voltage charge pump circuit using a nonvolatile memory device.

In recent years, the size of the device has been reduced in order to improve the density and performance of the semiconductor product, and as the size of the device decreases, the power supply voltage applied to the device has been reduced together.

In line with this trend, Flash Electrically Erasable and Programmable Read Only Memory (hereinafter referred to as "flash EEPROM") has also been designed to operate at low supply voltages.

However, when erasing or programming the flash EEPROM, a high voltage (e.g., 10V or higher) is required, so that a high voltage required for operation of the flash EEPROM is generated from a low power supply voltage supplied from an external source. Means are needed.

A charge pump circuit is generally used to generate a high voltage from a low voltage. The charge pump circuit receives a low power supply voltage and generates a high voltage internally required.

The charge pump circuit is used to instantaneously raise the low power supply voltage input to the circuit from the outside during the operation of not only flash EEPROM but also various memory products such as DRAM (Dynamic Random Access Memory).

After configuring the MOSFET of the conventional charge pump circuit in the form of diodes or diodes in series, the capacitors in between the normal clock pulses and the phase inverted clock pulses between the stages are connected to each other. Alternately applies to odd / even stages.

The clock pulse applied in this manner turns on and off the odd and even stages periodically to boost the voltage through charge sharing of the capacitor.

FIG. 1 is a circuit diagram showing a conventional charge pump circuit of the related art, and includes a power supply voltage input unit 1, a charge transfer device 2, a charge storage device 3, and a clock driver 4.

The charge transfer device (2) is to be connected in series in a plurality of stages in the power supply voltage input section (1), a plurality of pass transistors connected to be operated in the diode that is, a plurality of NMOS transistors (NM _1, NM _2, ... NM _{n -1} , NM _n ).

Said charge storage elements (3) are each NMOS transistor _{(NM 1, NM 2, ...} NM n-1, NM n) respectively connected to the charge storage capacitor acts as a (C _1, C _2, ... in which the _n- C ₁ , C _n ).

Here, the combination of one transfer transistor and one capacitor is defined as a single stage 5, that is, a unit charge pump.

The clock drivers CLK ₁ and CLK ₂ generate and input complementary clocks to the capacitors C ₁ , C ₂ ,... C _n-1 , C _n .

On the other hand, that the number of NMOS transistors connected in series, each of the gate electrodes _{(NM 1, NM 2, ...} NM n-1, NM n) is electrically connected to its drain electrode connected to the diode, the gate of NM ₁ The electrode is electrically connected to the power supply voltage output, the gate electrode of NM ₂ is electrically connected to the first node N ₁ , the gate electrode of NM _n-1 is connected to the N _n-2 node, and NM _n is N _It is electrically connected to the _n-1 node.

Such a pump circuit generates a high output voltage V _OUT at which the level is increased by pumping the power supply voltage output from the power supply voltage output unit 1 in accordance with the clock signal of each clock driver to generate the final output.

Therefore, the power supply voltage supplied to the general charge pump circuit is pumped to a higher voltage toward the final output terminal V _OUT as the pumping time by the clock signals CLK ₁ and CLK ₂ increases.

The charge pump zero represents an output voltage as shown in Equation 1 below because the power voltage V _DD is charged through the power voltage output unit 1.

Equation 1

In Equation 1, V _OUT is the final output voltage, V _DD is the power supply voltage, V _TH is the threshold voltage of the transistor NM, and N is the number of stages in the charge pump circuit.

Therefore, in the conventional charge pump circuit, the voltage output after pumping is sensitive to the difference between the magnitude of the power supply voltage applied to the power supply voltage input unit 1 and the threshold voltage of the transistor, so that the design rule of the device is reduced and accordingly V _DD As the value decreases, the voltage pumping efficiency in the entire charge pump circuit decreases.

In other words, as the design rule of the device decreases, the power supply voltage and the threshold voltage input to the circuit decrease, and the difference between the power supply voltage and the threshold voltage gradually decreases due to the reason that the reduction rate of the threshold voltage is significantly smaller compared to the power supply voltage reduction rate. do.

Therefore, in order to maintain the function of the charge pump circuit, efforts are made to lower the threshold voltage of the charge transfer device, but when the threshold voltage of the charge transfer device becomes extremely low, the rest of the general logic circuits except the charge transfer device and the charge transfer device are Since the leakage current in the channel region is increased in all the devices used in the circuit, power consumption of the entire circuit is increased.

In addition, a separate additional and some pump circuit, the zero threshold voltage field effect transistor element (Zero V _TH MOSFET device) to order the production of and However, a zero threshold voltage field effect transistor element if used in making a more general logic element Since the process must proceed, there are problems such as an increase in mask and process cost.

As a result, the power supply voltage decreases as the design rule of the device decreases, resulting in a decrease in the pump efficiency of the charge pump circuit and a problem of failing to obtain the high voltage required for the operation of the circuit.

An object of the present invention to solve the problem according to the prior art is to electrically connect the control gate of a nonvolatile memory device having a program gate node with a drain to form a diode connection, and through the voltage applied to the program gate By adjusting the amount of negatively or positively charged charges inside the floating gate of the nonvolatile memory device, the threshold voltage is controlled by an electrical method so that the final output voltage of the charge pump circuit decreases in accordance with the reduction of the existing supply voltage. An object of the present invention is to provide a charge pump using a nonvolatile memory device capable of arbitrarily controlling an output voltage.

The low voltage charge pump circuit using the nonvolatile memory device of the present invention for solving the above technical problem, and a plurality of charge transfer device connected to the power supply voltage input unit for pumping power supply voltage connected to the power supply voltage input unit And a charge pump circuit comprising a plurality of charge storage elements connected to each of said charge transfer elements and consisting of capacitors, and a connected clock driver for generating a clock complementary to said plurality of charge storage elements. The charge transfer device includes a floating gate, a control gate, a program gate node, a source and a drain, and a nonvolatile memory device configured to control an electrical threshold voltage of the device by a voltage applied to the program gate node. With drain straight Are connected and electrically connected through a diode connection, and the effective coupling ratio of the nonvolatile memory device is changed by the charge storage device when the threshold voltage is adjusted through the nonvolatile memory device between the charge storage device and the charge transfer device. The transmission gate, which serves as a switching role, is further electrically connected to prevent damage.

According to an aspect of a low voltage charge pump circuit using the nonvolatile memory device of the present invention, the nonvolatile memory device includes a substrate connected to a ground node, a drain as a power input terminal, a source as a power output terminal, a floating gate, and the floating circuit. A control gate and a program gate sharing a gate, wherein the control gate is electrically connected to the drain to form a diode connection, and the program gate controls the threshold voltage of the device by adjusting the amount of charge inside the floating gate. Can be configured.

According to another aspect of the low voltage charge pump circuit using the nonvolatile memory device of the present invention, the nonvolatile memory device; A substrate connected to ground, a first drain, which is a power input terminal, a first source, which is a power output terminal, a first floating gate formed on the substrate, and a first floating gate formed on the first floating gate and electrically connected to the drain. A control gate forming a diode connection, a second source and a second drain formed at one side of the first source and the first drain, and a second source and a second drain electrically connected to the first floating gate. It may include a program gate for adjusting the threshold voltage of the device by adjusting the amount of charge in the first floating gate by the supplied voltage.

The invention will become more apparent through the following preferred embodiments with reference to the accompanying drawings. Hereinafter will be described in detail to enable those skilled in the art to easily understand and reproduce through embodiments of the present invention.

2 is a low voltage charge pump circuit diagram using a nonvolatile memory device according to the present invention, and FIGS. 3 and 4 are conceptual views illustrating an embodiment of the nonvolatile memory device of FIG. 2.

Referring to FIG. 2, a power supply voltage input unit 10 receiving a power supply voltage, a plurality of charge transfer devices 20 connected to the power supply voltage input unit 10 to pump and transfer a power supply voltage, and the respective charges A plurality of charge storage elements 30 connected to the transfer element 20 and consisting of capacitors, and a clock driver 40 and a transmission gate 50 connected to generate a mutually complementary clock to the plurality of charge storage elements 30. )

The charge transfer device 20 is formed of a nonvolatile memory device (NVM), each nonvolatile memory device is connected to the power supply voltage input unit 10 in series, and a capacitor (S) of the source (S) of each nonvolatile memory device. C) is connected so that one nonvolatile memory element and one capacitor C are configured as a single stage 60.

The nonvolatile memory device includes a floating gate 110, a control gate 120, a program gate node PG, a source S, and a drain D, and a voltage applied to the program gate node PG. And electrically adjusts the threshold voltage of the nonvolatile memory device.

That is, the nonvolatile memory device adjusts the threshold voltage by an electrical method by adjusting the amount of negatively or positively charged charges in the floating gate 110 by the voltage applied to the program gate node PG. do.

Accordingly, the threshold voltage of the charge transfer device 10, which is a nonvolatile memory device, is adjusted, and thus the final output voltage increases as compared with a charge pump circuit using a transistor fixed to an arbitrary threshold voltage.

In addition, as the number of stages 60 increases, the number of nonvolatile memory devices NVM having a program gate node PG increases, and the final output voltage is affected by the number of stages 60.

Meanwhile, the control gate electrode 120 of each of the plurality of non-volatile memory devices NVM ₁ , NVM ₂ ,..., NVM _n-1 , NVM _n connected in series is electrically connected to its drain D to form a diode. Being connected, the control gate electrode of NVM ₁ is electrically connected to its drain D and power supply voltage input, the control gate electrode of NVM ₂ is electrically connected to first node N1, and NVM _n is It is electrically connected to the N _n-1 node.

Looking at the configuration of the nonvolatile memory device in detail, the substrate 100 is connected to the ground, the drain (D) which is a power input terminal and the source (S) that is a power output terminal, the floating gate 110, and the floating gate 110 The control gate 120 and the program gate 130 to share the control gate 120 is electrically connected to the drain (D) to form a diode connection.

The program gate 130 adjusts the threshold voltage of the nonvolatile memory device by adjusting the amount of negative or positive charge in the floating gate 110 by using the voltage input through the program gate node PG.

In this case, the source (S) and the drain (D) is the threshold voltage of the nonvolatile memory device (NVM) is changed by the hot electron (CHE: Channel Hot Electron) generated in the channel region during the operation of the nonvolatile memory device It is preferable that the doping concentration is increased in steps as it goes to the metal contact regions of the source and the drain in order to prevent it.

In other words, when the doping concentration difference between the source S and the drain D and the substrate 100 is large, a strong electric field at the junction between the source S and the drain D and the substrate 100 when the device is in operation. (electric field), which causes a significant increase in the energy of the electrons in the channel region to generate hot electrons.

In this case, since hot electrons of the channel region 140 move toward the floating gate 110, a large amount of electrons are trapped in the gate oxide layer of the nonvolatile memory device or injected into the floating gate, thereby changing the threshold voltage of the device. It is preferable to adjust the doping concentration so that the difference in the doping concentration near the interface with the substrate 100 is small, and increase the doping concentration toward the source (S) and drain (D) metal contact regions.

In addition, in the case of a nonvolatile memory device such as a general flash EEPROM device, since the control gate and the floating gate are simultaneously etched during the control gate etching on the floating gate using a self aligned etching process, the control gate and the floating gate are separately separated. Separate production was difficult.

However, the nonvolatile memory device as the charge transfer device of the present invention only needs to maintain a constant coupling between the floating gate and the control gate without a self-aligned etching process, and thus, there is an advantage that the nonvolatile memory device can be implemented using a standard CMOS logic process.

5 and 6 are conceptual diagrams illustrating another embodiment of the nonvolatile memory device of FIG. 2, which will be described with reference to FIGS. 2, 5, and 6, but for the same components as those of the embodiment of the present invention. The description is omitted.

According to another exemplary embodiment of the present invention, the nonvolatile memory device may include a substrate 200 connected to a ground, a first drain D1 serving as a power input terminal, a first source S1 serving as a power output terminal, and an upper portion of the substrate 200. A first floating gate 210 formed on the first floating gate 210, a control gate 220 formed on the first floating gate 210 and electrically connected to the drain D to form a diode connection, and the first source ( And a second source S2 and a second drain D2 formed on one side of S1 and the first drain D1, and are supplied between the second source S2 and the second drain D2. The threshold voltage of the device is controlled by adjusting the amount of negative or positive charge in the first floating gate 210 by the voltage.

In other words, in another embodiment of the present invention, the amount of negative or positive charge inside the first floating gate 210 is adjusted by the voltage applied to the second source S2 and the second drain D2.

As a result, the threshold voltage is adjusted by controlling the amount of charge inside the first floating gate 210, and the output voltage can be adjusted by controlling the difference between the power supply voltage and the threshold voltage by adjusting the threshold voltage.

The first source S1 and the first drain D1 may include metal contact regions of the source and drain to prevent the threshold voltage of the nonvolatile memory device from being changed by hot electrons generated during operation of the nonvolatile memory device. It is preferred to be formed to increase the doping concentration step by step toward.

Meanwhile, as described above, the control gate 220 and the drain D1 of the nonvolatile memory device are directly connected and electrically connected through the diode connection.

FIG. 7 is a circuit diagram illustrating the transmission gate of FIG. 2, and includes one N-type field effect transistor and one P-type field effect transistor, and in the process of adjusting the amount of charge of the floating gate, the charge configured by the capacitor It is electrically coupled with the storage device 30 to prevent a change in the effective coupling ratio of the nonvolatile memory device NVM.

That is, when the transmission gate 50 adjusts the threshold voltage by adjusting the amount of charge charged to the floating gates 110 and 210 by the voltage applied to the program gate node PG of the nonvolatile memory device, the capacitor Since the effective coupling ratio changes under the influence of (C), it is connected so as to prevent a change in the effective coupling ratio by the capacitor (C).

와

)를 이용하여 트랜스미션 게이트(50)를 차단할 수 있도록 구성 되어 있는 것이다. 이와는 반대로, 상기 비휘발성 메모리 소자의 문턱전압의 조정이 완료되고 정상적인 차지 펌프 회로의 기능을 수행할 때에는 상기 트랜스미션 게이트(50)로 입력되는 두 개의 신(와

)를 이용하여 트랜스미션 게이트(50)를 동작할 수 있도록 구성 되어 있는 것이다. For example, when adjusting the threshold voltage of the nonvolatile memory device, two signals input to the transmission gate 50 (

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It is configured to block the transmission gate (50) using. On the contrary, when the adjustment of the threshold voltage of the nonvolatile memory device is completed and functions as a normal charge pump circuit, two scenes inputted to the transmission gate 50 ( Wow

) Is configured to operate the transmission gate 50.

As described above, according to the present invention, by controlling the amount of negatively or positively charged charges in the floating gate through the voltage applied to the program gate node, the nonvolatile memory device capable of adjusting the threshold voltage by an electrical method is a charge transfer device. As used, the output voltage of the charge pump can be arbitrarily controlled.

For example, when the design rule is reduced and the power supply voltage is reduced, the charge pump circuit is lowered by reducing the negative charge inside the floating gate of the nonvolatile memory device through voltage regulation applied to the program gate PG. To improve pumping efficiency.

As described above, the present invention additionally electrically connects the control gate of the nonvolatile memory device having the program gate node with the drain to form a diode connection, and through the voltage applied to the program gate, the inside of the floating gate of the nonvolatile memory device. By adjusting the amount of negatively or positively charged charges, the threshold voltage is controlled in an electrical manner to arbitrarily control the pumping efficiency and output voltage of the charge pump, thereby reducing the design rule and pumping the charge pump according to the reduction of the supply voltage. There is an advantage that can prevent a decrease in efficiency.

While the invention has been described in terms of the preferred embodiments with reference to the accompanying drawings, it will be apparent to those skilled in the art that many various and obvious modifications are possible without departing from the scope of the invention. Therefore, the scope of the invention should be construed by the claims described to include many such variations.

Claims (5)

A power voltage input unit for receiving a power voltage; A plurality of charge transfer devices connected to the power supply voltage input unit to pump and output a power supply voltage; A plurality of charge storage elements connected to each of said charge transfer elements and comprised of capacitors, and A charge pump circuit comprising a clock driver for transferring a clock complementary to the plurality of charge storage devices, The charge transfer device is; A non-volatile memory device includes a floating gate, a control gate, a program gate node, a source and a drain, and controls an electrical threshold voltage of the device by a voltage applied to the program gate node. The control gate and the drain are directly connected. Is electrically connected via a diode connection, Between the charge storage element and the charge transfer element; A transmission gate is further electrically connected to prevent the change of the effective coupling ratio of the nonvolatile memory device by the charge storage device when the threshold voltage is adjusted through the nonvolatile memory device. The nonvolatile memory device may include; A substrate connected to ground, A first source which is a power input terminal and a first source which is a power output terminal, A first floating gate formed on the substrate; A control gate formed on the first floating gate and electrically connected to the drain to form a diode connection; It is configured to include a second source and a second drain formed on one side of the first source and the first drain, The threshold voltage of the device is adjusted by adjusting the amount of charge inside the first floating gate by the voltage supplied between the second source and the second drain. delete delete delete The method of claim 1, The first source and the first drain; In order to prevent the threshold voltage of the nonvolatile memory device from changing due to hot electrons generated during the operation of the nonvolatile memory device, the doping concentration is gradually increased toward the metal contact regions of the source and the drain. Low voltage charge pump circuit using memory element.

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