CN105490515B - Start-up circuit with nF level capacitive loads - Google Patents
Start-up circuit with nF level capacitive loads Download PDFInfo
- Publication number
- CN105490515B CN105490515B CN201610015808.6A CN201610015808A CN105490515B CN 105490515 B CN105490515 B CN 105490515B CN 201610015808 A CN201610015808 A CN 201610015808A CN 105490515 B CN105490515 B CN 105490515B
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- voltage source
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- input voltage
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
- H02M1/34—Snubber circuits
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
- Electronic Switches (AREA)
Abstract
The present invention relates to a kind of analog power chip start-up circuit of band nF level capacitive loads, including：Power tube, band nF levels capacitive load, comparator, diode, current source, reference voltage source VREFWith input voltage source 1, input voltage source 2, it is characterised in that：Comparator input positive terminal connects diode D1 anode, and input negative terminal meets reference voltage source VREF, output end VENCPCharge pump is electrically connected, charge pump exports the grid for connecing power tube；Current source extracts electric current from input voltage source 1, and the grid of power tube is connected to after diode D1；The drain electrode electrical connection input voltage source 2 of power tube, source electrode meet output voltage VOUT, band nF levels capacitive load connection output voltage VOUTTo ground；As comparator output terminal VENCPFor it is high when, charge pump, work as VENCPFor it is low when electric charge air pump inoperative；Using the present invention chip can be made not extract high current from input voltage source in start-up course, so as to ensure that chip normally starts, output voltage gently rises to input voltage source magnitude of voltage.
Description
Technical field
The present invention relates to a kind of analog power chip circuit, and in particular to a kind of analog power chip internal parasitic load electricity
Hold the band nF level capacitive load start-up circuits of about nF levels.
Background technology
In traditional chip start-up circuit, when electric on whole circuit one electric capacity charging have a 6-7A it is big impact electricity
Stream.All added with the development of technology, in chip it is soft open circuit so that chip start when surge current in controlled range
It is interior.But it is typically all to be designed for the small capacitances that chip internal parasitic load capacitance is 1-2pF.When load capacitance is power
During the grid of pipe, its parasitic load capacitance will be nF ranks, start-up course still be present and the problem of big surge current be present,
Even cause to cause whole chip cisco unity malfunction, output voltage can not normally start.
The content of the invention
The purpose of the present invention is in place of above-mentioned the shortcomings of the prior art, there is provided and it is a kind of stable, it can reduce
Surge current, and chip can be made not extract high current from input voltage source in start-up course, so as to ensure that chip normally starts,
Output voltage gently rises to the band nF level capacitive load start-up circuits of input voltage source magnitude of voltage.
The above-mentioned purpose of the present invention can be reached by following measures, a kind of analog power core of band nF level capacitive loads
Piece start-up circuit, including：Power tube, band nF levels capacitive load, comparator, diode, current source, reference voltage source VREFWith it is defeated
Enter voltage source 1, input voltage source 2, it is characterised in that：Comparator input positive terminal connects diode D1 anode, and input negative terminal connects ginseng
Examine voltage source VREF, output end VENCPCharge pump is electrically connected, charge pump exports the grid for connecing power tube；Current source is from input voltage
Electric current is extracted in source 1, and the grid of power tube is connected after diode D1；The drain electrode electrical connection input voltage source 2 of power tube, source electrode
Meet output voltage VOUT, band nF levels capacitive load connection output voltage VOUTTo ground；As comparator output terminal VENCPFor it is high when, electric charge
Pump work, work as VENCPFor it is low when electric charge air pump inoperative.
Optimization, described current source values are 1uA.
Optimization, described current source is realized by PMOS current mirrors.
Optimization, described reference voltage source is than 1 low 0.5V of voltage source.
The present invention has the advantages that compared to prior art.
It is stable, surge can be reduced.The present invention connects diode D1 anode using comparator input positive terminal, and input is negative
Termination voltage source VREF, output end VENCP electrically connect charge pump, and charge pump exports the grid for connecing power tube；Current source is from input
Voltage source 1 extracts electric current, and the grid of power tube is connected to after diode D1；The drain electrode electrical connection input voltage source of power tube
2, source electrode meets output voltage VO UT, and output voltage VO UT is connected to the band band nF level capacitive loads of ground composition with nF levels capacitive load
Start-up circuit is stable, and the electric current for only needing to extract from VIN relative to traditional circuit is original 1/5th, is greatly reduced
Surge current, can make chip normally complete startup work, output voltage gently rises to input voltage source magnitude of voltage.
Brief description of the drawings
Fig. 1 is band band nF level capacitive load start-up circuit theory diagrams proposed by the present invention.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated；It should be appreciated that specific embodiment described herein is used only for explaining the present invention, and
It is not used in the restriction present invention.
As shown in figure 1, a kind of analog power chip start-up circuit of band nF level capacitive loads, including：Charge pump circuit, work(
Rate pipe, band nF level capacitive loads, comparator, diode, current source and input voltage source 1, input voltage source 2, reference voltage source
VREF, wherein：Comparator input positive terminal connects diode D1 anode, and input negative terminal meets reference voltage source VREF, output end VENCPElectricity
Charge pump is connected, charge pump exports the grid for connecing power tube；Current source extracts electric current from input voltage source 1, and through diode D1
The grid of power tube is connected to afterwards；The drain electrode electrical connection input voltage source 2 of power tube, source electrode meet output voltage VOUT, band nF level electricity
Hold load connection output voltage VOUTTo ground；As comparator output terminal VENCPFor it is high when, charge pump, work as VENCPFor it is low when electric charge
Air pump inoperative；Wherein, current source is realized by PMOS current mirrors, and the current source values of optimization are 1uA；Described reference voltage source is than electricity
1 low 0.5V of potential source.
Embodiment 1
In order that the present invention gets across, it is assumed that VIN=5V, VREFThe output of=4.5V charge pumps is 10V when stable, current source
For 1uA, those skilled in the art should be understood that value described above merely to explaining that the present invention is not to limit the present invention.
Completed in two stages with the start-up course with nF level capacitive load start-up circuits, the first stage, comparator anode
Input voltage V1<VREFWhen, electric charge air pump inoperative, power tube MOS grid voltage VGATEDiode D1 is passed through by a current source
It is charged, because power tube mos gate pole parasitic capacitance is bigger, then VGATESlowly rise, now VOUTFollow VGATEOn linear
Rise, this process VOUTCompare V alwaysGATEA small metal-oxide-semiconductor threshold voltage, VOUTRise to about 4V；Second stage works as V1>VREFWhen, than
The high level signal V for being compared with device outputENCP, charge pump circuit starts working, now VGATEIt is climbed to 10V, VOUTValue is quick
5V is risen to from 4V, diode D1 is operated in cut-off state, while serves pressure-resistant, prevents V1 from VGATEGo out to extract electric current.By
When charge pump is opened, VOUTOnly need to change 1V, only needed from V relative to traditional circuitINThe electric current of extraction is original five points
One of, surge current is greatly reduced, chip can be made to normally complete startup work.
Claims (5)
1. a kind of analog power chip start-up circuit of band nF level capacitive loads, including：Power tube, band nF levels capacitive load, ratio
Compared with device, diode, current source, reference voltage source VREFWith input voltage source 1, input voltage source 2, it is characterised in that：Comparator is defeated
Enter positive terminating diode D1 anode, input negative terminal meets reference voltage source VREF, output end VENCPElectrically connect charge pump, charge pump
Output connects the grid of power tube；Current source extracts electric current from input voltage source 1, and the grid of power tube are connected to after diode D1
Pole；The drain electrode electrical connection input voltage source 2 of power tube, source electrode meet output voltage VOUT, band nF levels capacitive load connection output voltage
VOUTTo ground；As comparator output terminal voltage VENCPFor it is high when, charge pump, work as VENCPFor it is low when electric charge air pump inoperative.
2. the analog power chip start-up circuit of band nF level capacitive loads according to claim 1, it is characterised in that described
Current source values be 1uA.
3. the analog power chip start-up circuit of band nF level capacitive loads according to claim 1, it is characterised in that described
The common-source common-gate current mirror circuit realiration that is made up of PMOS transistor of current source.
4. the analog power chip start-up circuit of band nF level capacitive loads according to claim 1, it is characterised in that described
Reference voltage source than 1 low 0.5V of input voltage source.
5. the analog power chip start-up circuit of band nF level capacitive loads according to claim 1, it is characterised in that band nF
The start-up course of the analog power chip start-up circuit of level capacitive load is completed in two stages, the first stage, comparator anode
Input voltage V1<VREFWhen, electric charge air pump inoperative, power tube MOS grid voltage VGATEDiode D1 is passed through by a current source
It is charged, VGATESlowly rise, VOUTFollow VGATELinear rise, VOUTCompare VGATEA small metal-oxide-semiconductor threshold voltage, VOUTRise
To 4V；Second stage, work as V1>VREFWhen, comparator output high level signal VENCP, charge pump circuit starts working, now VGATE
It is climbed to 10V, VOUTValue quickly rises to 5V from 4V, and diode D1 is operated in cut-off state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610015808.6A CN105490515B (en) | 2016-01-11 | 2016-01-11 | Start-up circuit with nF level capacitive loads |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610015808.6A CN105490515B (en) | 2016-01-11 | 2016-01-11 | Start-up circuit with nF level capacitive loads |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105490515A CN105490515A (en) | 2016-04-13 |
| CN105490515B true CN105490515B (en) | 2018-02-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610015808.6A Expired - Fee Related CN105490515B (en) | 2016-01-11 | 2016-01-11 | Start-up circuit with nF level capacitive loads |
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| CN (1) | CN105490515B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108711918B (en) * | 2018-08-22 | 2023-12-12 | 上海艾为电子技术股份有限公司 | Switch charging circuit |
| CN113300586B (en) * | 2021-06-10 | 2022-04-01 | 深圳市微源半导体股份有限公司 | Power tube soft start circuit applied to power management chip |
| CN114825912A (en) * | 2022-05-24 | 2022-07-29 | 无锡友达电子有限公司 | NMOS (N-channel metal oxide semiconductor) tube output circuit with ultralow voltage difference |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09238463A (en) * | 1996-02-29 | 1997-09-09 | Sanyo Electric Co Ltd | Charge pump circuit |
| US6459315B2 (en) * | 2000-02-24 | 2002-10-01 | Sony Corporation | Wave reforming circuit |
| CN1655431A (en) * | 2004-02-10 | 2005-08-17 | 圆创科技股份有限公司 | Slow starting electric charge pump circuit |
| CN1859001A (en) * | 2006-03-01 | 2006-11-08 | 华为技术有限公司 | DC power slow start circuit |
| JP2007159288A (en) * | 2005-12-06 | 2007-06-21 | Seiko Epson Corp | Soft start circuit and power supply |
| CN101325411A (en) * | 2008-04-16 | 2008-12-17 | 中兴通讯股份有限公司 | Slow starting circuit for electrifying DC power supply |
| CN101957625A (en) * | 2010-11-12 | 2011-01-26 | 复旦大学 | Low dropout linear voltage regulator for driving nF-stage load |
| CN103262415A (en) * | 2010-12-22 | 2013-08-21 | 惠普发展公司，有限责任合伙企业 | Mosfet switch gate driver, mosfet switch system and method |
| CN103529890A (en) * | 2012-07-06 | 2014-01-22 | 国民技术股份有限公司 | Soft start device and method |
| CN204835911U (en) * | 2015-08-27 | 2015-12-02 | 漳州科华技术有限责任公司 | Power driver chip's slow starting circuit |
-
2016
- 2016-01-11 CN CN201610015808.6A patent/CN105490515B/en not_active Expired - Fee Related
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09238463A (en) * | 1996-02-29 | 1997-09-09 | Sanyo Electric Co Ltd | Charge pump circuit |
| US6459315B2 (en) * | 2000-02-24 | 2002-10-01 | Sony Corporation | Wave reforming circuit |
| CN1655431A (en) * | 2004-02-10 | 2005-08-17 | 圆创科技股份有限公司 | Slow starting electric charge pump circuit |
| JP2007159288A (en) * | 2005-12-06 | 2007-06-21 | Seiko Epson Corp | Soft start circuit and power supply |
| CN1859001A (en) * | 2006-03-01 | 2006-11-08 | 华为技术有限公司 | DC power slow start circuit |
| CN101325411A (en) * | 2008-04-16 | 2008-12-17 | 中兴通讯股份有限公司 | Slow starting circuit for electrifying DC power supply |
| CN101957625A (en) * | 2010-11-12 | 2011-01-26 | 复旦大学 | Low dropout linear voltage regulator for driving nF-stage load |
| CN103262415A (en) * | 2010-12-22 | 2013-08-21 | 惠普发展公司，有限责任合伙企业 | Mosfet switch gate driver, mosfet switch system and method |
| CN103529890A (en) * | 2012-07-06 | 2014-01-22 | 国民技术股份有限公司 | Soft start device and method |
| CN204835911U (en) * | 2015-08-27 | 2015-12-02 | 漳州科华技术有限责任公司 | Power driver chip's slow starting circuit |
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| Publication number | Publication date |
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| CN105490515A (en) | 2016-04-13 |
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Granted publication date: 20180223 |