CN109103101A - 纳米微结构的制备方法 - Google Patents
纳米微结构的制备方法 Download PDFInfo
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- CN109103101A CN109103101A CN201710476065.7A CN201710476065A CN109103101A CN 109103101 A CN109103101 A CN 109103101A CN 201710476065 A CN201710476065 A CN 201710476065A CN 109103101 A CN109103101 A CN 109103101A
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Inorganic Chemistry (AREA)
- Nanotechnology (AREA)
- Materials Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Thin Film Transistor (AREA)
- Drying Of Semiconductors (AREA)
Abstract
本发明涉及一种纳米微结构的制备方法,包括以下步骤:提供一基板,在基板表面设置一光刻胶掩模层,厚度为H;曝光和显影得到一图案化掩模层,该图案化掩模层包括多个条状掩模块,相邻条状掩模块的间隔为L;向基板表面沉积一第一薄膜层,厚度为D,使得沉积方向与条状掩模块的厚度方向夹角为θ1,且θ1<tan‑1(L/H);改变沉积方向,向基板表面沉积一第二薄膜层,使得沉积方向与条状掩模块的厚度方向夹角为θ2,θ2<tan‑1[L/(H+D)],使得0<L‑Htanθ1‑(H+D)tanθ2<10nm,则该第一薄膜层与第二薄膜层部分重叠;去除条状掩模块;干法刻蚀所述第一薄膜层及第二薄膜层,得到一纳米微结构。
Description
技术领域
本发明涉及微纳加工技术领域,特别涉及一种纳米微结构的制备方法。
背景技术
现有技术在制备小尺寸的结构时,如果通过直接加工的方法,加工尺寸多数由加工设备的性能决定。而直接加工出细槽小于10nm的结构,已经超出了绝大多数设备的极限。即便可以加工,成本和成品率也不容易控制。
而若想得到小的细槽结构,常规的方法如蒸发剥离或刻蚀方法等都要先由光刻胶得到小尺寸的结构,然后再基于此结构进行后续的加工。但是,这些方法的问题在于:首先,小尺寸的光刻胶很难实现,过厚的胶本身很难立住,容易倒塌,过薄的胶很难实现图形转移;其次,剥离或者刻蚀过程会对光刻胶有影响,导致光刻胶的残留,对后续结构产生影响。同时,采用上述小尺寸结构制备的产品也会相应受到限制,如薄膜晶体管等。
发明内容
有鉴于此,确有必要提供一种方法简单、易操作的纳米微结构的制备方法。
一种纳米微结构的制备方法,其包括以下步骤:提供一基板,在所述基板的表面设置一光刻胶掩模层,该光刻胶掩模层的厚度为H;对该光刻胶掩模层曝光和显影得到一图案化掩模层,该图案化掩模层包括多个平行且间隔设置的条状掩模块,相邻条状掩模块的间隔距离为L,设定该图案化掩模层远离基板的表面为第一区域,该图案化掩模层相对于该光刻胶掩模层增加的表面为第二区域,相邻条状掩模块之间暴露的基板的表面为第三区域;向设置有条状掩模块的基板表面沉积一第一薄膜层,该第一薄模层的厚度为D,并使得沉积方向与条状掩模块的厚度方向夹角为θ1,且θ1<tan-1(L/H);改变沉积方向,向设置有条状掩模块的基板表面沉积一第二薄膜层,使得沉积方向与条状掩模块的厚度方向夹角为θ2,θ2<tan-1[L/(H+D)],且所述第一薄膜层和第二薄膜层覆盖整个第二区域,并使得0<L-Htanθ1-(H+D)tanθ2<10nm,则该第一薄膜层与第二薄膜层在第三区域内部分重叠,重叠区域为纳米级条带;去除条状掩模块,得到部分重叠设置的第一薄膜层和第二薄膜层;干法刻蚀所述第一薄膜层及第二薄膜层,得到一纳米微结构,该纳米微结构的宽度与重叠区域的宽度相同。
相较于现有技术,本发明提供的纳米微结构的制备方法,通过采用侧向沉积的方法得到纳米微结构,沉积过程中通过调节沉积过程参数即可实现纳米级微结构;该方法制备的纳米级微结构的宽度可根据需要进行调节;同时,沟道两侧可沉积不同的材料,从而可以实现纳米级沟道两侧是由不同材料构成。
附图说明
图1为本发明第一实施例提供的所述纳米级沟道的制备方法的流程图。
图2为本发明第一实施例提供的显影后得到的所述条状掩模块的结构示意图。
图3为本发明第一实施例提供的纳米级沟道的扫描电镜照片。
图4为本发明提供的第一薄膜层和第二薄膜层的沉积方法的流程图。
图5为本发明提供的第一薄膜层和第二薄膜层的沉积方法的流程图。
图6为本发明第二实施例提供的具有纳米级沟道的薄膜晶体管的制备方法的流程图。
图7为本发明第三实施例提供的纳米级微结构的制备方法的流程图。
图8为本发明第四实施例提供的纳米带的制备方法的流程图。
主要元件符号说明
如下具体实施例将结合上述附图进一步说明本发明。
具体实施方式
下面将结合具体实施例,对本发明提供的纳米级沟道、薄膜晶体管、纳米微结构、纳米带的制备方法作进一步详细说明。
请一并参阅图1、2,本发明第一实施例提供的纳米级沟道的制备方法,其包括以下步骤:
步骤S11,提供一基板10,在所述基板10的表面设置一光刻胶掩模层11,该光刻胶掩模层11的厚度为H;
步骤S12,对该光刻胶掩模层11曝光和显影得到一图案化掩模层12,该图案化掩模层12包括多个平行且间隔设置的条状掩模块121,相邻条状掩模块121的间隔距离为L,设定该图案化掩模层12远离基板10的表面为第一区域I,该图案化掩模层12相对于该光刻胶掩模层11增加的表面为第二区域II,相邻条状掩模块121之间暴露的基板10的表面为第三区域III;
步骤S13,以条状掩模块121的延伸方向为旋转轴旋转所述基板10,使得该基板10与水平方向夹角为θ1,且θ1<tan-1(L/H),沿竖直方向向设置有条状掩模块121的基板10的表面沉积一第一薄膜层13,该第一薄膜层13的厚度为D;
步骤S14,将该基板10旋转回至水平方向,以该旋转方向继续旋转基板10至该基板10与水平方向夹角为θ2,且θ2<tan-1[L/(H+D)],沿竖直方向向设置有条状掩模块121的基板10的表面沉积一第二薄膜层14,并使得0<Htanθ1+(H+D)tanθ2-L<10nm,则该第一薄膜层13与第二薄膜层14在第三区域内的间隔区域为纳米级沟道。
在步骤S11中,所述基板10的材料不限,可为二氧化硅、氮化硅等材料形成的绝缘基板,金、铝、镍、铬、铜等材料形成的金属基板或者硅、氮化镓、砷化镓等材料形成的半导体基板。本实施例中,所述基板10的材料为硅基板。
所述光刻胶掩模层11主要起到遮挡作用。所述光刻胶掩模层11的材料为光刻胶。其中,光刻胶的种类不限,可为正性光刻胶或负性光刻胶,可为电子束光刻胶、紫外光刻胶等,如S9912光刻胶、SU8光刻胶、PMMA胶、ZEP胶、HSQ胶等。所述光刻胶掩模层11可通过将光刻胶采用旋涂的方法直接涂敷于所述基板10上形成。所述光刻胶掩模层11的厚度H的范围可根据需要调节。所述光刻胶掩模层11的厚度H为200纳米-400纳米。优选地,所述光刻胶掩模层11的厚度H为300纳米-400纳米。本实施例中,所述光刻胶掩模层11的材料为HSQ胶,厚度为400纳米。
在步骤S12中,对所述光刻胶掩模层11进行曝光时,可预先在所述光刻胶掩模层11的表面设定一曝光图案,再对该曝光图案对应的光刻胶掩模层11进行曝光。其中,所述曝光图案的形状、尺寸可根据需要进行设定。本实施例中采用电子束曝光,曝光强度及时间可根据光刻胶厚度及材料调节。曝光后,将该光刻胶掩模层11进行显影。具体地,将该光刻胶掩模层11浸置于一显影溶液中,所述显影溶液与曝光区域充分反应,以去除部分光刻胶,从而得到一图案化掩模层12。设定该图案化掩模层12远离基板10的表面为第一区域I,该第一区域I即所述条状掩模块121的顶面;去除部分光刻胶后,该图案化掩模层12相对于光刻胶掩模层11增加了部分表面,该部分表面垂直于所述基板10的表面,将该增加的表面设定为第二区域II,该第二区域II即所述条状掩模块121的侧表面;设定相邻条状掩模块121间暴露的基板10的表面为第三区域III。本实施例中,所述显影溶液为TMAH溶液,显影时间为90s。所述图案化掩模层12包括多个平行且间隔设置的条状掩模块121。具体地,该多个条状掩模块121可排列为一排,也可排列为多排。其中,每排中相邻两条状掩模块121的间隔距离为L。相邻条状掩模块121的间隔距离L为200纳米-1000纳米。优选地,相邻条状掩模块121的间隔距离L为400纳米-500纳米。本实施例中,相邻条状掩模块121的间隔距离L为400纳米。
在步骤S13中,由于该多个条状掩模块121互相平行,该多个条状掩模块121的延伸方向为同一延伸方向,因此,可选择任一条状掩模块121的延伸方向为旋转轴的方向旋转该基板10。旋转基板10后,该基板10所在平面与水平方向的夹角为θ1,且θ1<tan-1(L/H)。又,所述条状掩模块121的厚度方向与该基板10的表面垂直,且沉积方向为竖直方向,因此,沉积方向与条状掩模块121厚度方向的夹角也为θ1,该夹角和基板所在平面与水平方向的夹角相同。优选地,该夹角θ1的范围为θ1≤45°。本实施例中,该夹角θ1为30°。可以理解,在沿竖直方向沉积该第一薄膜层13时,由于该基板10与水平方向呈一定角度,且该基板10上设置有间隔分布的条状掩模块121,该第一薄膜层13不会覆盖所述基板10及条状掩模块121的整个表面,该基板10及条状掩模块121的部分表面由于条状掩模块121的遮挡而未沉积该第一薄膜层13。进一步,该基板10的表面未沉积所述第一薄膜层13的位置可通过调节夹角θ1、条状掩模块121的厚度H或间隔距离L进行调节。
所述第一薄膜层13的材料可为金、镍、钛、铁、铜、铝等金属材料,也可为氧化铝、氧化镁、氧化锌、氧化铪、二氧化硅等非金属材料。所述第一薄膜层13的材料不限于上述列举材料,只要确保材料能够沉积为薄膜即可。所述第一薄膜层13可通过电子束蒸镀法、磁控溅射法等方法沉积。所述第一薄膜层13的厚度D的范围为D<40纳米。本实施例中,所述第一薄膜层13通过电子束蒸镀法沉积形成,该第一薄膜层13的材料为铝,厚度D为30纳米。
在步骤S14中,将该基板10旋转至水平方向的过程可根据需要选择顺时针或逆时针方向旋转,只要能够保证沉积材料仍能够沉积至设置有条状掩模块121的表面即可。所述基板10旋转至水平方向后,按照该旋转方向继续旋转至该基板10与水平方向夹角为θ2,且θ2<tan-1[L/(H+D)]。同样,沉积方向与条状掩模块121厚度方向的夹角也为θ2。优选地,该夹角θ2的范围为θ2≤45°。本实施例中,该夹角θ2为30°。同样地,在沿竖直方向沉积该第二薄膜层14时,由于该基板10与水平方向呈一定角度,且该基板10上设置有间隔分布的条状掩模块121,该第二薄膜层14不会覆盖所述基板10及掩模块121的整个表面,该基板10及条状掩模块121的部分表面由于条状掩模块121的遮挡而未沉积该第二薄膜层14。又由于在沉积该所述第一薄膜层13及第二薄膜层14的过程中,参数H、θ1、θ2、D、L符合0<Htanθ1+(H+D)tanθ2-L<10nm的条件,从而使得该第一薄膜层13和第二薄膜层14在所述基板10的表面上间隔设置,且间隔的区域的间隔距离在纳米级范围内。具体地,该间隔距离小于20纳米。优选地,该间隔距离小于10纳米。本实施例中,该间隔距离为9.67纳米。请参阅图3,图3为通过侧向沉积得到的纳米级沟道的扫描电镜照片。
所述第二薄膜层14的材料可为金、镍、钛、铁、铜、铝等金属材料,也可为氧化铝、氧化镁、氧化锌、氧化铪、二氧化硅等非金属材料。所述第二薄膜层14的材料不限于上述列举材料,只要确保材料能够沉积为薄膜即可。所述第二薄膜层14的材料与所述第一薄膜层13的材料可以相同,也可以不同。所述第二薄膜层14可通过电子束蒸镀法、磁控溅射法等方法沉积。所述第二薄膜层14的厚度不限,可根据需要调节。本实施例中,所述第二薄膜层14通过电子束蒸镀法沉积形成,该第二薄膜层14的材料为铝,厚度为30纳米。
进一步,在竖直沉积过程中可以如图1为竖直向下沉积薄膜层,同样也可竖直向上沉积。请参阅图4,将设置有条状掩模块121的基板10的表面反转方向设置为向下时,通过竖直向上沉积,也同样可在基板10及条状掩模块121上沉积薄膜层。同时,沉积过程中的夹角等参数与竖直向上沉积的方向相同。
进一步,向设置有条状掩模块121的基板10上沉积薄膜层的方法不限于此,只要满足沉积第一薄膜层13时,沉积方向与条状掩模块121的厚度方向夹角为θ1,沉积第二薄膜层14时,沉积方向与条状掩模块121的厚度方向夹角为θ2且符合0<Htanθ1+(H+D)tanθ2-L<10nm即可。可以理解,该沉积方向应在垂直于条状掩模块121的延伸方向的平面内进行调节。请参阅图5,当设置有条状掩模块121的基板10为水平固定放置时,可通过改变沉积方向与条状掩模块121的厚度方向夹角来实现沉积的目的,即调节沉积方向与条状掩模块121厚度方向夹角为θ1,沉积该第一薄膜层13;再调节沉积方向与条状掩模块121厚度方向夹角为θ2,沉积该第二薄膜层14。
本发明提供的纳米级沟道的制备方法,通过采用侧向沉积的方法得到纳米级沟道,沉积过程中通过调节沉积过程参数即可实现纳米级沟道,无需刻蚀、剥离等方法辅助,对基板材料无损伤;侧向沉积方法能够精确定位制备,可选定任意位置制备纳米级沟道;该方法制备的纳米级沟道的宽度可根据需要进行调节;同时,沟道两侧可沉积不同的材料,从而可以实现纳米级沟道两侧是由不同材料构成。
请参阅图6,本发明第二实施例提供一种具有纳米级沟道的薄膜晶体管20的制备方法,其包括以下步骤:
步骤S21,提供一基板21,在所述基板21的表面设置一栅极22,在所述栅极22远离基板21的表面设置一栅极绝缘层23;
步骤S22,在所述栅极绝缘层23远离所述栅极22的表面设置一半导体层24;
步骤S23,在所述半导体层24的表面设置间隔的两条状掩模块121、122,两条状掩模块的厚度为H,两条状掩模块的间隔距离为L;
步骤S24,以条状掩模块的延伸方向为旋转轴旋转该半导体层24,使得该半导体层24与水平方向夹角为θ1,且θ1<tan-1(L/H),沿竖直方向向设置有条状掩模块的半导体层24表面沉积一第一导电薄膜层25,该第一导电薄膜层25的厚度为D;
步骤S25,将该半导体层24旋转回至水平方向,以该旋转方向继续旋转基板至该基板与水平方向夹角为θ2,且θ2<tan-1[L/(H+D)],沿竖直方向向设置有条状掩模块的半导体层24表面沉积一第二导电薄膜层26,并使得0<Htanθ1+(H+D)tanθ2-L<10nm,则该第一导电薄膜层25与第二导电薄膜层26之间的区域为纳米级沟道,所述第一导电薄膜层25和第二导电薄膜层26即作为一源极27、一漏极28。
在步骤S21中,所述栅极22由导电材料组成,该导电材料可选择为金属、ITO、ATO、导电银胶、导电聚合物以及导电碳纳米管等。该金属材料可以为铝、铜、钨、钼、金、钛、钯或任意组合的合金。
所述栅极绝缘层23的材料可选择为氧化铝、氧化铪、氮化硅、氧化硅等硬性材料或苯并环丁烯(BCB)、聚酯或丙烯酸树脂等柔性材料。
所述栅极绝缘层23通过磁控溅射法、电子束沉积法或原子层沉积法等形成于所述栅极22的表面并覆盖所述栅极22。本实施例中,所述栅极绝缘层23通过原子层沉积法形成,该栅极绝缘层23为氧化铝层。
在步骤S22中,所述半导体层24的材料可为砷化镓、磷化镓、氮化镓、碳化硅、硅化锗、硅、锗、碳纳米管、石墨烯、硫化钼等。所述半导体层24可根据材料不同,采用直接平铺、外延生长、气相沉积法等方法形成于所述栅极绝缘层23的表面。进一步,当所述半导体层24为碳纳米管层、石墨烯层或硫化钼层时,可通过光刻胶转移至所述栅极绝缘层23的表面,再将光刻胶去掉即可。所述半导体层24的厚度可根据需要制备。所述半导体层24的厚度小于10纳米。本实施例中,所述半导体层24的厚度为2纳米。
在步骤S23-S25中,在所述半导体层24的表面制备纳米级沟道的方法与第一实施例提供的纳米级沟道的制备方法相似,其区别在于,本实施例是直接在所述半导体层24的表面上沉积导电薄膜层并作为源极和漏极,从而直接制备出具有纳米级沟道的薄膜晶体管。具体地,设定该条状掩模块121、122远离半导体层24的表面为第一区域I,该第一区域I即所述条状掩模块121、122的顶面;设定所述条状掩模块121、122的侧面为第二区域II;设定两条状掩模块121、122间暴露的半导体层24的表面为第三区域III。所述第一导电薄膜层25和第二导电薄膜层26可为金、镍、钛、铁、铝等金属材料。具体地,设置在所述半导体层14的表面的第一导电薄膜层25和第二导电薄膜层26,即作为所述薄膜晶体管20的源极27和漏极28。
进一步,制备薄膜晶体管的方法不限于此,只要通过上述步骤S23-S25制备得到所述源极27和漏极28,从而使得薄膜晶体管具有纳米级沟道即可。例如,可通过上述方法先制备源极、漏极,再制备栅极,从而得到顶栅型薄膜晶体管。
进一步,在形成所述源极27和漏极28后还可包括去除两条状掩模块121、122的步骤。去除两条状掩模块121、122的方法可采用化学试剂去除,并保证该化学试剂不会与其它结构反应。具体地,将步骤S25中得到的结构置于丙酮溶液中,两条状掩模块121、122溶于丙酮溶液中被去除。当所述第一导电薄膜层25和第二导电薄膜层26为非自支撑结构时,在去除两条状掩模块121、122的过程中,位于第一区域及第二区域的导电薄膜层由于失去支撑也同时被去掉。去除两条状掩模块121、122后,所述第一导电薄膜层25和第二导电薄膜层26仍设置在所述半导体层24的表面部分,即作为所述薄膜晶体管20的源极27和漏极28。当所述第一导电薄膜层25和第二导电薄膜层26为自支撑结构时,在去除两条状掩模块121、122后,位于第一区域及第二区域的第一导电薄膜层25和第二导电薄膜层26可通过干法刻蚀去掉。所谓自支撑结构是指该结构可以无需一支撑体而保持一特定的结构。
请参阅图7,本发明第三实施例提供一种纳米级微结构的制备方法,其包括以下步骤:
步骤S31,提供一基板30,在所述基板30的表面设置一光刻胶掩模层31,该光刻胶掩模层的厚度为H;
步骤S32,对该光刻胶掩模层31曝光、显影得到一图案化掩模层32,该图案化掩模层32包括多个平行且间隔设置的条状掩模块321,相邻条状掩模块的间隔距离为L;
步骤S33,以条状掩模块的延伸方向为旋转轴旋转所述基板30,使得该基板与水平方向夹角为θ1,且θ1<tan-1(L/H),沿竖直方向向设置有条状掩模块的基板表面沉积一第一薄膜层33,该第一薄膜层33的厚度为D;
步骤S34,将该基板30旋转回至水平方向,以该旋转方向继续旋转基板至该基板与水平方向夹角为θ2,且θ2<tan-1[L/(H+D)],沿竖直方向向设置有条状掩模块的基板表面沉积一第二薄膜层34,并使得0<L-Htanθ1-(H+D)tanθ2<10nm,则该第一薄膜层33与第二薄膜层34部分重叠;
步骤S35,去除条状掩模块321,得到部分重叠设置的第一薄膜层33及第二薄膜层34;
步骤S36,干法刻蚀所述第一薄膜层33及第二薄膜层34,使非重叠区域全部被刻蚀,从而得到一纳米级微结构35,该纳米级微结构35的宽度与重叠区域的宽度相同。
所述步骤S31-S33与第一实施例中步骤S11-S13相同,目的是在基板上通过设置间隔的条状掩模块,并用以沉积薄膜层。
在步骤S34中,该步骤与第一实施例中步骤S14相似,其区别在于,本实施例中,所述第二薄膜层34与第一薄膜层33为部分重叠设置,并且重叠部分的宽度为纳米级宽度。其中,在沉积所述第一薄膜层33和第二薄膜层34的过程中,参数H、θ1、θ2、D、L符合0<L-Htanθ1-(H+D)tanθ2<10nm的条件,从而该第一薄膜层33与第二薄膜层34在基板表面部分重叠,且重叠的区域宽度在纳米级范围内。
同样地,向设置有条状掩模块321的基板30上沉积薄膜层的方法不限于此,只要满足沉积第一薄膜层33时,沉积方向与条状掩模块321的厚度方向夹角为θ1,沉积第二薄膜层34时,沉积方向与条状掩模块321的厚度方向夹角为θ2且符合0<L-Htanθ1-(H+D)tanθ2<10nm。
在步骤S35中,去除条状掩模块321的方法可采用化学试剂去除,并保证该化学试剂不会与其它结构反应。具体地,将步骤S34中得到的结构置于丙酮溶液中,所述条状掩模块321溶于丙酮溶液中被去除。去除条状掩模块321后,如果所述第一薄膜层33与第二薄膜层34为非自支撑结构,则在去除条状掩模块321后,薄膜层在第一区域及第二区域的部分由于没有条状掩模块321的支撑也被去掉,从而只保留有沉积在第三区域内的第一薄膜层33与第二薄膜层34;如果所述第一薄膜层33与第二薄膜层34为自支撑结构,则在去除条状掩模块321后,该第一薄膜层33与第二薄膜层34在第一区域、第二区域及第三区域的部分均存在,即该第一薄膜层33与第二薄膜层34保留完整结构。
在步骤S36中,所述干法刻蚀是指通入一气体在电场作用下得到一等离子体,该等离子体可与被刻蚀物质发生反应而得到挥发性物质,比如:电感耦合等离子体刻蚀(ICPE)、反应性离子刻蚀(RIE)。具体地,通过向一等离子体系统通入一气体,所述气体可以为氧气、氯气、氢气、氩气、四氟化碳等。所述气体不限于上述列举气体,只要该气体可与该第一薄膜层33和第二薄膜层34发生反应即可。同时,所述第一薄膜层33和第二薄膜层34在刻蚀过程中全部同时被刻蚀。
当所述第一薄膜层33与第二薄膜层34保留完整结构时,该第一区域及第二区域的薄膜层可通过刻蚀等方法先去除掉,再刻蚀位于第三区域的第一薄膜层33与第二薄膜层34。在刻蚀第三区域的第一薄膜层33及第二薄膜层34的过程中,该第一薄膜层33、第二薄膜层34会同时被刻蚀。由于所述第一薄膜层33、第二薄膜层34重叠部分的厚度大于该第一薄膜层33的厚度,也大于该第二薄膜层34的厚度,在第一薄膜层33和第二薄膜层34的刻蚀速率相同的情况下,同时刻蚀第一薄膜层33及第二薄膜层34,在非重叠部分的第一薄膜层及第二薄膜层被刻蚀掉后,所述重叠部分仅部分被刻蚀,而仍未完全被刻蚀掉,则刻蚀得到的剩余的重叠部分结构即为纳米级微结构。该纳米级微结构的宽度即为重叠部分的宽度。在干法刻蚀的整个过程中,并没有设置专门的掩模,而只是单纯的刻蚀步骤,即可得到纳米级微结构。
进一步,上述刻蚀过程也可在去除条状掩模块321之前进行。具体地,当所述第一薄膜层33及第二薄膜层34沉积完成后,可直接通过干法刻蚀该第一薄膜层33及第二薄膜层34。可以理解,位于第一区域的第一薄膜层33及第二薄膜层34首先被刻蚀,第一区域的薄膜层被刻蚀掉后继续刻蚀第二区域的薄膜层、第三区域的薄膜层。
本发明提供的纳米微结构的制备方法,通过采用侧向沉积的方法得到纳米微结构,沉积过程中通过调节沉积过程参数即可实现纳米级微结构;侧向沉积方法能够精确定位制备,可选定任意位置制备纳米级微结构;该方法制备的纳米级微结构的宽度可根据需要进行调节。
请参阅图8,本发明第四实施例提供一种纳米带的制备方法,其包括以下步骤:
步骤S41,提供一基板41,在所述基板41的表面设置一半导体薄膜42,在所述半导体薄膜42的表面设置间隔的条状掩模块421,条状掩模块的厚度为H,相邻两条状掩模块的间隔距离为L;
步骤S42,以条状掩模块的延伸方向为旋转轴旋转该半导体薄膜42,使得该半导体薄膜42与水平方向夹角为θ1,且θ1<tan-1(L/H),沿竖直方向向设置有条状掩模块的半导体薄膜42沉积一第一薄膜层43,该第一薄膜层43的厚度为D;
步骤S43,将该半导体薄膜42旋转回至水平方向,以该旋转方向继续旋转该半导体薄膜42至该半导体薄膜42与水平方向夹角为θ2,且θ2<tan-1[L/(H+D)],沿竖直方向向设置有条状掩模块的半导体薄膜42表面沉积一第二薄膜层44,并使得0<L-Htanθ1-(H+D)tanθ2<10nm,则该第一薄膜层43与第二薄膜层44部分重叠;
步骤S44,去除条状掩模块421;
步骤S45,干法刻蚀所述第一薄膜层43及第二薄膜层44,从而得到一纳米级微结构45;
步骤S46,以所述纳米级微结构45为掩模刻蚀所述半导体薄膜42,得到一纳米带46。
在步骤S41中,所述半导体薄膜42为石墨烯、硫化钼等二维材料。所述半导体薄膜42可通过直接平铺、气相沉积等方法形成于所述基板41的表面。所述半导体薄膜42的厚度可根据需要进行设定。本实施例中,所述半导体薄膜42的材料为石墨烯。
所述步骤S42-S45与第三实施例中步骤S33-S36相同,目的是为了制备纳米级微结构。本实施例中,通过上述步骤得到的纳米级微结构45在后续制备纳米带的过程中可起到掩模的作用。同样地,设定该条状掩模块远离半导体薄膜的表面为第一区域,该条状掩模块的侧表面为第二区域,相邻条状掩模块之间暴露的半导体薄膜的表面为第三区域。
在步骤S46中,刻蚀所述半导体薄膜42的方法可继续采用步骤S45中刻蚀所述第一薄膜层43及第二薄膜层44的方法,上述刻蚀方法可实现刻蚀半导体薄膜42,但同时也会进一步刻蚀所述纳米级微结构45。因此,在刻蚀所述半导体薄膜42时,应保证在刻蚀掉该半导体薄膜42之前,该纳米级微结构45不会被全部刻蚀掉,以使得该纳米级微结构45起到掩模的作用,从而制备得到所述纳米带。
进一步,在刻蚀所述半导体薄膜42完成后,所述纳米级微结构45未被全部刻蚀掉,则可包括去除该纳米级微结构45的步骤。所述纳米级微结构45可采用湿法刻蚀去除。具体地,可将带有纳米级微结构45的结构置于盐酸溶液中,将该纳米级微结构45腐蚀去除。
另外,本领域技术人员还可在本发明精神内作其它变化,当然这些依据本发明精神所作的变化,都应包含在本发明所要求保护的范围内。
Claims (10)
1.一种纳米微结构的制备方法,其包括以下步骤:
提供一基板,在所述基板的表面设置一光刻胶掩模层,该光刻胶掩模层的厚度为H;
对该光刻胶掩模层曝光和显影得到一图案化掩模层,该图案化掩模层包括多个平行且间隔设置的条状掩模块,相邻条状掩模块的间隔距离为L,设定该图案化掩模层远离基板的表面为第一区域,该图案化掩模层相对于该光刻胶掩模层增加的表面为第二区域,相邻条状掩模块之间暴露的基板的表面为第三区域;
向设置有条状掩模块的基板表面沉积一第一薄膜层,该第一薄模层的厚度为D,并使得沉积方向与条状掩模块的厚度方向夹角为θ1,且θ1<tan-1(L/H);
改变沉积方向,向设置有条状掩模块的基板表面沉积一第二薄膜层,使得沉积方向与条状掩模块的厚度方向夹角为θ2,θ2<tan-1[L/(H+D)],且所述第一薄膜层和第二薄膜层覆盖整个第二区域,并使得0<L-Htanθ1-(H+D)tanθ2<10nm,则该第一薄膜层与第二薄膜层在第三区域内部分重叠;
去除条状掩模块,得到部分重叠设置的第一薄膜层和第二薄膜层;
干法刻蚀所述第一薄膜层及第二薄膜层,使非重叠区域全部被刻蚀,重叠区域仅部分被刻蚀,从而得到一纳米微结构,该纳米微结构的宽度与重叠区域的宽度相同。
2.如权利要求1所述的纳米微结构的制备方法,其特征在于,所述光刻胶掩模层的厚度为H为200纳米-400纳米。
3.如权利要求1所述的纳米微结构的制备方法,其特征在于,相邻条状掩模块的间隔距离L为200纳米-450纳米。
4.如权利要求1所述的纳米微结构的制备方法,其特征在于,所述沉积方向与条状掩模块的厚度方向夹角θ1的范围为θ1≤45°。
5.如权利要求1所述的纳米微结构的制备方法,其特征在于,所述第一薄膜层的厚度D的范围为D<40纳米。
6.如权利要求1所述的纳米微结构的制备方法,其特征在于,所述沉积方向与条状掩模块的厚度方向夹角θ2的范围为θ2≤45°。
7.如权利要求1所述的纳米微结构的制备方法,其特征在于,该条状掩模块的延伸方向与沉积方向垂直。
8.如权利要求1所述的纳米微结构的制备方法,其特征在于,所述第一薄膜层与第二薄膜层为非自支撑结构,位于第一区域和第二区域的该第一薄膜层与第二薄膜层随条状掩模块一起去除。
9.如权利要求1所述的纳米微结构的制备方法,其特征在于,所述第一薄膜层与第二薄膜层为自支撑结构,位于第一区域及第二区域的所述第一薄膜层与第二薄膜层通过刻蚀去除。
10.一种纳米微结构的制备方法,其包括以下步骤:
提供一基板,在所述基板的表面设置一光刻胶掩模层,该光刻胶掩模层的厚度为H;
对该光刻胶掩模层曝光、显影得到一图案化掩模层,该图案化掩模层包括多个平行且间隔设置的条状掩模块,相邻条状掩模块的间隔距离为L,设定该图案化掩模层远离基板的表面为第一区域,该图案化掩模层相对于该光刻胶掩模层增加的表面为第二区域,相邻条状掩模块之间暴露的基板的表面为第三区域;
以条状的条状掩模块的延伸方向为旋转轴旋转所述基板,使得该基板与水平方向夹角为θ1,且θ1<tan-1(L/H),沿竖直方向向设置有条状掩模块的基板表面沉积一第一薄膜层,该第一掩模层的厚度为D;
将该基板旋转至水平方向,以该旋转方向继续旋转基板至该基板与水平方向夹角为θ2,且θ2<tan-1[L/(H+D)],沿竖直方向向设置有条状掩模块的基板表面沉积一第二薄膜层,并使得0<L-Htanθ1-(H+D)tanθ2<10nm,则该第一薄膜层与第二薄膜层在第三区域内部分重叠;
去除条状掩模块,得到部分重叠设置的第一薄膜层和第二薄膜层;
干法刻蚀所述第一薄膜层及第二薄膜层,使非重叠区域全部被刻蚀,重叠区域仅部分被刻蚀,得到一纳米微结构,该纳米微结构的宽度与重叠区域的宽度相同。
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