CN109087945A - 一种igbt的制造方法 - Google Patents
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Abstract
本发明公开了一种IGBT的制造方法，首先在N‑衬底上形成N+少子存储区域，再通过比N+少子存储区域更大的光刻视场形成窗口，以保证P+区域可以在横向上完全覆盖N+少子存储区域，形成被N+少子存储层半包围的P+区域，通过这种方式既引入了CS区域，又最大程度的降低了CS层对器件击穿电压的影响，最终得到了平面局域少子存储IGBT，既有效提升导通压降与关断损耗间的折衷关系又最大程度的减少了少子存储区域对器件的击穿电压的影响，本发明实用性强、易于使用和推广。
Description
技术领域
本发明涉及半导体技术，具体是一种IGBT的制造方法。
背景技术
IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极晶体管)是一种双极型器件，从结构上看，正面是一个MOSFET的结构，背面是一个PIN二极管的结构，通过这种结构的组合，从而使IGBT既具有双极型功率晶体管导通压降低、电流容量大的特点，又具有功率MOSFET输入阻抗高、驱动电路简单的优点。随着电气化的普及，IGBT应用越来越广泛，诸如：新能源汽车、高铁、工业变频、白色家电等领域。IGBT之所以具有较低的通态压降，主要是在开通过程中，N-漂移区内存储大量过剩载流子。但是在关断过程中，由于背部P型集电区的存在，过剩载流子无法快速抽取，只能复合消失，这样就会造成关断的拖尾电流，大大增加了关断损耗。N-漂移区内过剩载流子的数量越多，通态压降越低，但是关断损耗也会大大增加。因此，IGBT器件在静态损耗与动态损耗之间存在着强烈的折衷关系。
由三菱电机公司提出的CSTBT(Carrier Stored Trench-gate BipolarTransistor，载流子存储槽栅双极晶体管)是在沟槽IGBT两侧槽栅之间的Pbody基区底部引入N型CS层(Carrier Stored layer，载流子存储层)，其浓度高于N-漂移区浓度，形成极低电压的扩散势，阻止空穴向上流出器件。为了保证电中性，相应数量的电子通过沟道流入N-漂移区，从而增大整体的过剩载流子浓度，降低导通压降，有效提升导通压降与关断损耗间的折衷关系。但是因为N型CS的电阻率低于N-漂移区，所以CS层的引入会降低器件的击穿电压。
发明内容
本发明的目的在于提供一种IGBT的制造方法，以解决上述背景技术中提出的问题。
为实现上述目的，本发明提供如下技术方案：
一种IGBT的制造方法，包括以下步骤：
采用N型单晶硅片，制备N型衬底，N型衬底即为N-漂移区，在N-漂移区上表面成N+少子存储层区域；
在N+少子存储层区域内形成P+区域；
形成正面的平面MOS结构，包括N+源区、栅极氧化层、发射极金属、栅极金属的部分；
进行背面减薄、注入、背金工艺，背面形成P+集电极和集电极金属。
作为本发明进一步的方案：所述N-漂移区的电阻率即为N型单晶衬底的电阻率。
作为本发明再进一步的方案：所述P+区域横向上完全覆盖N+少子存储层区域且纵向上不完全覆盖N+少子存储层区域。
作为本发明再进一步的方案：所述P+区域和N+少子存储层形成过程包括以下步骤：
步骤一、在N-漂移区上通过光刻、注入、扩散形成N+掺杂；
步骤二、形成比N+掺杂更大的光刻区域，通过注入扩散在N+掺杂区域内形成P+区域，形成了纵向上P+区域被N+少子存储层包围，横向上P+区域不被N+少子存储层包围。
与现有技术相比，本发明的有益效果是：首先在N-衬底上形成N+少子存储区域，再通过比N+少子存储区域更大的光刻视场形成窗口，以保证P+区域可以在横向上完全覆盖N+少子存储区域，形成被N+少子存储层半包围的P+区域。通过这种方式既引入了CS区域，又最大程度的降低了CS层对器件击穿电压的影响，最终得到了平面局域少子存储IGBT，既有效提升导通压降与关断损耗间的折衷关系又最大程度的减少了少子存储区域对器件的击穿电压的影响，本发明实用性强、易于使用和推广。
附图说明
图1为IGBT的制造方法最终所形成的IGBT结构剖面图。
图2为IGBT的制造方法中在N-漂移区上通过光刻、注入、扩散形成N+掺杂的示意图。
图3为IGBT的制造方法中N+掺杂区上形成比N+掺杂更大的光刻区域，通过注入扩散在N+掺杂区域内形成P+区域的示意图。
其中：N-漂移区1、N+少子存储层区域2、P+区域3、N+源区4、栅极氧化层5、发射极金属6、栅极金属7、P+集电极8、集电极金属9。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例1：
请参阅图1～3，本发明实施例中，一种IGBT的制造方法，包括以下步骤：采用N型单晶硅片，制备N型衬底，N型衬底即为N-漂移区(1)，在N-漂移区(1)上表面成N+少子存储层区域(2)，再在N+少子存储层区域(2)内形成P+区域(3)，P+区域(3)横向上完全覆盖N+少子存储层区域(2)且纵向上不完全覆盖N+少子存储层区域(2)，从而达到仅保留P+区域(3)下方N+少子存储层的目的，而后正常的形成正面的平面MOS结构，包括N+源区(4)、栅极氧化层(5)、发射极金属(6)、栅极金属(7)等部分。再进行背面减薄、注入、背金等工艺，背面形成P+集电极(8)和集电极金属(9)，最终形成具有局域少子存储层的平面IGBT。既保留了少子存储效果，达到了降低导通压降，提高开关速度的效果，同时又保留了P+区域(3)不完全被N+少子存储层(2)包围，保证了器件的击穿电压，是对传统的IGBT的一种有效优化。
所述N-漂移区(1)的电阻率即为N型单晶衬底的电阻率。
所述P+区域(3)和N+少子存储层(2)形成过程包括以下步骤：
步骤一、在N-漂移区(1)上通过光刻、注入、扩散形成N+掺杂。
步骤二、形成比N+掺杂更大的光刻区域，通过注入扩散在N+掺杂区域内形成P+区域(3)，形成了纵向上P+区域(3)被N+少子存储层(2)包围，横向上P+区域(3)不被N+少子存储层(2)包围。
所述其N+源区(4)、栅极氧化层(5)、发射极金属(6)、栅极金属(7)等部分与普通的平面IGBT没有差异，芯片正面结构完成以后，再进行背面减薄、注入、背金等工艺，背面形成P+集电极(8)和集电极金属(9)的制造流程与普通的IGBT也没有差异，最终形成了平面局域少子存储IGBT，既有效提升导通压降与关断损耗间的折衷关系又最大程度的减少了少子存储区域对器件的击穿电压的影响。
实施例2：
以600V IGBT的制造工艺流程为例，其具体工艺过程如下：
一、衬底材料准备，采用电阻率约为40Ω·cm，厚度为400～600μm的n型区熔单晶硅衬底，其晶向为<100>；
二、在N-漂移区1上通过光刻、注入、扩散形成N+掺杂区2，注入剂量。磷注入剂量1e13cm-3，注入能量100KeV，扩散温度1100℃，扩散时间60分钟。
三、形成比N+掺杂更大的光刻区域，P+区域光刻开孔宽度比N+掺杂区开孔宽度大2μm～6μm，通过硼的注入扩散在N+掺杂区域2内形成P+区域3，硼注入的剂量为5e13cm-3，注入能量为80KeV，扩散温度1100℃，扩散时间40分钟。形成了纵向上P+区域3被N+少子存储层2包围，横向上P+区域3不被N+少子存储层2包围。
步骤三、在器件正面形成N+源区、栅极氧化层、发射极金属、栅极金属等部分与普通的平面IGBT没有差异，芯片正面结构完成以后，再进行背面减薄、注入、背金等工艺，背面形成P+集电极(8)和集电极金属(9)的制造流程与普通的IGBT也没有差异。
需要特别说明的是，本申请中所述其N+源区(4)、栅极氧化层(5)、发射极金属(6)、栅极金属(7)部分与普通的平面IGBT没有差异，背面形成P+集电极(8)和集电极金属(9)的制造流程与普通的IGBT也没有差异，均为现有技术的应用，本申请的基本工艺方案是首先在N-衬底上形成N+少子存储区域，再通过比N+少子存储区域更大的光刻视场形成窗口，以保证P+区域可以在横向上完全覆盖N+少子存储区域，形成被N+少子存储层半包围的P+区域。通过这种方式既引入了CS区域，又最大程度的降低了CS层对器件击穿电压的影响，最终得到了平面局域少子存储IGBT，既有效提升导通压降与关断损耗间的折衷关系又最大程度的减少了少子存储区域对器件的击穿电压的影响。
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背离本发明的精神或基本特征的情况下，能够以其他的具体形式实现本发明。因此，无论从哪一点来看，均应将实施例看作是示范性的，而且是非限制性的，本发明的范围由所附权利要求而不是上述说明限定，因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。
此外，应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施例中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。
Claims (4)
1.一种IGBT的制造方法，其特征在于，包括以下步骤：
采用N型单晶硅片，制备N型衬底，N型衬底即为N-漂移区(1)，在N-漂移区(1)上表面成N+少子存储层区域(2)；
在N+少子存储层区域(2)内形成P+区域(3)；
形成正面的平面MOS结构，包括N+源区(4)、栅极氧化层(5)、发射极金属(6)、栅极金属(7)的部分；
进行背面减薄、注入、背金工艺，背面形成P+集电极(8)和集电极金属(9)。
2.根据权利要求1所述的IGBT的制造方法，其特征在于，所述N-漂移区(1)的电阻率即为N型单晶衬底的电阻率。
3.根据权利要求1所述的IGBT的制造方法，其特征在于，所述P+区域(3)横向上完全覆盖N+少子存储层区域(2)且纵向上不完全覆盖N+少子存储层区域(2)。
4.根据权利要求1所述的IGBT的制造方法，其特征在于，所述P+区域(3)和N+少子存储层(2)形成过程包括以下步骤：
步骤一、在N-漂移区(1)上通过光刻、注入、扩散形成N+掺杂；
步骤二、形成比N+掺杂更大的光刻区域，通过注入扩散在N+掺杂区域内形成P+区域(3)，形成了纵向上P+区域(3)被N+少子存储层(2)包围，横向上P+区域(3)不被N+少子存储层(2)包围。
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| CN103839987A (zh) * | 2012-11-23 | 2014-06-04 | 中国科学院微电子研究所 | 功率器件-mpt-ti-igbt的结构及其制备方法 |
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