CN109076036B - 一种用于传输数据的方法及系统 - Google Patents

一种用于传输数据的方法及系统 Download PDF

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Publication number
CN109076036B
CN109076036B CN201680085663.5A CN201680085663A CN109076036B CN 109076036 B CN109076036 B CN 109076036B CN 201680085663 A CN201680085663 A CN 201680085663A CN 109076036 B CN109076036 B CN 109076036B
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Prior art keywords
channel
data
adjustment
transmitter
receiver
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Chinese (zh)
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CN109076036A (zh
Inventor
斯坦利·艾姆斯·小拉基
达蒙·托希迪
格拉德·R·塔尔伯特
爱德华多·普莱特
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ATI Technologies ULC
Advanced Micro Devices Inc
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ATI Technologies ULC
Advanced Micro Devices Inc
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00Arrangements for monitoring or testing data switching networks
    • H04L43/08Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0823Errors, e.g. transmission errors
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00Arrangements for monitoring or testing data switching networks
    • H04L43/08Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0852Delays
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00Arrangements for monitoring or testing data switching networks
    • H04L43/50Testing arrangements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/04Speed or phase control by synchronisation signals
    • H04L7/06Speed or phase control by synchronisation signals the synchronisation signals differing from the information signals in amplitude, polarity or frequency or length
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/04Speed or phase control by synchronisation signals
    • H04L7/10Arrangements for initial synchronisation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0016Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033Correction by delay
    • H04L7/0041Delay of data signal
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/04Speed or phase control by synchronisation signals
    • H04L7/041Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/043Pseudo-noise [PN] codes variable during transmission

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Environmental & Geological Engineering (AREA)
  • Power Engineering (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
CN201680085663.5A 2016-06-24 2016-09-21 一种用于传输数据的方法及系统 Active CN109076036B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/192,287 2016-06-24
US15/192,287 US10749756B2 (en) 2016-06-24 2016-06-24 Channel training using a replica lane
PCT/US2016/052725 WO2017222578A1 (en) 2016-06-24 2016-09-21 Channel training using a replica lane

Publications (2)

Publication Number Publication Date
CN109076036A CN109076036A (zh) 2018-12-21
CN109076036B true CN109076036B (zh) 2022-01-28

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CN201680085663.5A Active CN109076036B (zh) 2016-06-24 2016-09-21 一种用于传输数据的方法及系统

Country Status (5)

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US (2) US10749756B2 (enExample)
JP (1) JP6703134B2 (enExample)
KR (1) KR102572281B1 (enExample)
CN (1) CN109076036B (enExample)
WO (1) WO2017222578A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10749756B2 (en) 2016-06-24 2020-08-18 Advanced Micro Devices, Inc. Channel training using a replica lane
JP7620232B2 (ja) * 2020-09-29 2025-01-23 日本電信電話株式会社 情報処理システム、情報処理方法およびプログラム
US11558120B1 (en) * 2021-09-30 2023-01-17 United States Of America As Represented By The Administrator Of Nasa Method for deskewing FPGA transmitter channels directly driving an optical QPSK modulator
US11906585B2 (en) * 2021-12-16 2024-02-20 Samsung Electronics Co., Ltd. Methods and systems for performing built-in-self-test operations without a dedicated clock source
US12321294B1 (en) * 2023-03-30 2025-06-03 Advanced Micro Devices, Inc. Data lane variation compensation for data rate enhancement

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1159224A (zh) * 1994-07-20 1997-09-10 微动公司 用于科里奥利氏流量计的降低噪音滤波系统
CN101099297A (zh) * 2004-01-28 2008-01-02 拉姆伯斯公司 通过漂移跟踪对通信通道的定期校准
US7467056B2 (en) * 2007-03-09 2008-12-16 Nortel Networks Limited Method and apparatus for aligning multiple outputs of an FPGA
CN101692634A (zh) * 2004-01-28 2010-04-07 拉姆伯斯公司 针对漂移条件的通信信道校准
CN103560785A (zh) * 2013-10-28 2014-02-05 中国电子科技集团公司第四十一研究所 一种产生相位相干信号的方法与装置
JP2014206971A (ja) * 2013-03-15 2014-10-30 インテル・コーポレーション ハイブリッドレーン低速化又は非固定バスアーキテクチャのための方法、装置、システム
CN104335197A (zh) * 2012-05-22 2015-02-04 超威半导体公司 用于存储器访问延迟训练的方法和装置
US9036757B1 (en) * 2014-09-23 2015-05-19 Oracle International Corporation Post-cursor locking point adjustment for clock data recovery

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6178213B1 (en) * 1998-08-25 2001-01-23 Vitesse Semiconductor Corporation Adaptive data recovery system and methods
US20020093986A1 (en) * 2000-12-30 2002-07-18 Norm Hendrickson Forward data de-skew method and system
US6907552B2 (en) * 2001-08-29 2005-06-14 Tricn Inc. Relative dynamic skew compensation of parallel data lines
US7072355B2 (en) 2003-08-21 2006-07-04 Rambus, Inc. Periodic interface calibration for high speed communication
US7516029B2 (en) * 2004-06-09 2009-04-07 Rambus, Inc. Communication channel calibration using feedback
US7500131B2 (en) 2004-09-07 2009-03-03 Intel Corporation Training pattern based de-skew mechanism and frame alignment
US20080130815A1 (en) * 2006-12-05 2008-06-05 Kumar S Reji Selective tracking of serial communication link data
US7590789B2 (en) * 2007-12-07 2009-09-15 Intel Corporation Optimizing clock crossing and data path latency
US8307265B2 (en) 2009-03-09 2012-11-06 Intel Corporation Interconnection techniques
US20110040902A1 (en) 2009-08-13 2011-02-17 Housty Oswin E Compensation engine for training double data rate delays
US8582706B2 (en) * 2009-10-29 2013-11-12 National Instruments Corporation Training a data path for parallel data transfer
KR101110820B1 (ko) * 2010-05-28 2012-02-27 주식회사 하이닉스반도체 슬레이브 장치, 마스터 장치와 슬레이브 장치를 포함하는 시스템 및 동작방법, 칩 패키지
US8681839B2 (en) 2010-10-27 2014-03-25 International Business Machines Corporation Calibration of multiple parallel data communications lines for high skew conditions
US8767531B2 (en) * 2010-10-27 2014-07-01 International Business Machines Corporation Dynamic fault detection and repair in a data communications mechanism
US8774228B2 (en) * 2011-06-10 2014-07-08 International Business Machines Corporation Timing recovery method and apparatus for an input/output bus with link redundancy
US8826092B2 (en) * 2011-10-25 2014-09-02 International Business Machines Corporation Characterization and validation of processor links
US9577816B2 (en) * 2012-03-13 2017-02-21 Rambus Inc. Clock and data recovery having shared clock generator
US9071407B2 (en) * 2012-05-02 2015-06-30 Ramnus Inc. Receiver clock test circuitry and related methods and apparatuses
US9030341B2 (en) 2012-06-27 2015-05-12 Broadcom Corporation Compensation for lane imbalance in a multi-lane analog-to-digital converter (ADC)
DE112015006953B4 (de) * 2015-09-26 2025-07-10 Intel Corporation Training einer gültigen lane
US10749756B2 (en) 2016-06-24 2020-08-18 Advanced Micro Devices, Inc. Channel training using a replica lane

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1159224A (zh) * 1994-07-20 1997-09-10 微动公司 用于科里奥利氏流量计的降低噪音滤波系统
CN101099297A (zh) * 2004-01-28 2008-01-02 拉姆伯斯公司 通过漂移跟踪对通信通道的定期校准
CN101692634A (zh) * 2004-01-28 2010-04-07 拉姆伯斯公司 针对漂移条件的通信信道校准
US7467056B2 (en) * 2007-03-09 2008-12-16 Nortel Networks Limited Method and apparatus for aligning multiple outputs of an FPGA
CN104335197A (zh) * 2012-05-22 2015-02-04 超威半导体公司 用于存储器访问延迟训练的方法和装置
JP2014206971A (ja) * 2013-03-15 2014-10-30 インテル・コーポレーション ハイブリッドレーン低速化又は非固定バスアーキテクチャのための方法、装置、システム
CN103560785A (zh) * 2013-10-28 2014-02-05 中国电子科技集团公司第四十一研究所 一种产生相位相干信号的方法与装置
US9036757B1 (en) * 2014-09-23 2015-05-19 Oracle International Corporation Post-cursor locking point adjustment for clock data recovery

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Experimental demonstration of robustness and accuracy of an MZI-based OSNR monitor under transmitter drift and reconfigurable networking conditions for pol-muxed 25-Gbaud QPSK and 16-QAM channels;A. Almaiman;《OFC 2014》;20140828;全文 *
非相干OCDMA系统编/解码器设计及多用户干扰抑制技术研究;陈思思;《哈尔滨工业大学硕士论文集》;20091231;全文 *

Also Published As

Publication number Publication date
JP6703134B2 (ja) 2020-06-03
US20210028995A1 (en) 2021-01-28
US11805026B2 (en) 2023-10-31
JP2019525507A (ja) 2019-09-05
US10749756B2 (en) 2020-08-18
KR102572281B1 (ko) 2023-08-29
KR20190011727A (ko) 2019-02-07
US20170373944A1 (en) 2017-12-28
CN109076036A (zh) 2018-12-21
WO2017222578A1 (en) 2017-12-28

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