JP6703134B2 - レプリカレーンを使用したチャネルトレーニング - Google Patents

レプリカレーンを使用したチャネルトレーニング Download PDF

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JP6703134B2
JP6703134B2 JP2018556345A JP2018556345A JP6703134B2 JP 6703134 B2 JP6703134 B2 JP 6703134B2 JP 2018556345 A JP2018556345 A JP 2018556345A JP 2018556345 A JP2018556345 A JP 2018556345A JP 6703134 B2 JP6703134 B2 JP 6703134B2
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Japan
Prior art keywords
lane
data
adjustment
transmitter
test pattern
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English (en)
Japanese (ja)
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JP2019525507A (ja
JP2019525507A5 (enExample
Inventor
エイムズ ラッキー ジュニア スタンリー
エイムズ ラッキー ジュニア スタンリー
トヒディ デイモン
トヒディ デイモン
アール． タルボット ジェラルド
アール． タルボット ジェラルド
プレーテ エドアルド
プレーテ エドアルド
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ATI Technologies ULC
Advanced Micro Devices Inc
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ATI Technologies ULC
Advanced Micro Devices Inc
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Publication of JP2019525507A5 publication Critical patent/JP2019525507A5/ja
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0823—Errors, e.g. transmission errors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0852—Delays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/50—Testing arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/06—Speed or phase control by synchronisation signals the synchronisation signals differing from the information signals in amplitude, polarity or frequency or length
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/10—Arrangements for initial synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0041—Delay of data signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/043—Pseudo-noise [PN] codes variable during transmission

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Environmental & Geological Engineering (AREA)
  • Power Engineering (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
JP2018556345A 2016-06-24 2016-09-21 レプリカレーンを使用したチャネルトレーニング Active JP6703134B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/192,287 2016-06-24
US15/192,287 US10749756B2 (en) 2016-06-24 2016-06-24 Channel training using a replica lane
PCT/US2016/052725 WO2017222578A1 (en) 2016-06-24 2016-09-21 Channel training using a replica lane

Publications (3)

Publication Number Publication Date
JP2019525507A JP2019525507A (ja) 2019-09-05
JP2019525507A5 JP2019525507A5 (enExample) 2019-10-31
JP6703134B2 true JP6703134B2 (ja) 2020-06-03

Family

ID=60675203

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018556345A Active JP6703134B2 (ja) 2016-06-24 2016-09-21 レプリカレーンを使用したチャネルトレーニング

Country Status (5)

Country Link
US (2) US10749756B2 (enExample)
JP (1) JP6703134B2 (enExample)
KR (1) KR102572281B1 (enExample)
CN (1) CN109076036B (enExample)
WO (1) WO2017222578A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10749756B2 (en) 2016-06-24 2020-08-18 Advanced Micro Devices, Inc. Channel training using a replica lane
JP7620232B2 (ja) * 2020-09-29 2025-01-23 日本電信電話株式会社 情報処理システム、情報処理方法およびプログラム
US11558120B1 (en) * 2021-09-30 2023-01-17 United States Of America As Represented By The Administrator Of Nasa Method for deskewing FPGA transmitter channels directly driving an optical QPSK modulator
US11906585B2 (en) * 2021-12-16 2024-02-20 Samsung Electronics Co., Ltd. Methods and systems for performing built-in-self-test operations without a dedicated clock source
US12321294B1 (en) * 2023-03-30 2025-06-03 Advanced Micro Devices, Inc. Data lane variation compensation for data rate enhancement

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5469748A (en) * 1994-07-20 1995-11-28 Micro Motion, Inc. Noise reduction filter system for a coriolis flowmeter
US6178213B1 (en) * 1998-08-25 2001-01-23 Vitesse Semiconductor Corporation Adaptive data recovery system and methods
US20020093986A1 (en) * 2000-12-30 2002-07-18 Norm Hendrickson Forward data de-skew method and system
US6907552B2 (en) * 2001-08-29 2005-06-14 Tricn Inc. Relative dynamic skew compensation of parallel data lines
US7072355B2 (en) 2003-08-21 2006-07-04 Rambus, Inc. Periodic interface calibration for high speed communication
US7400670B2 (en) 2004-01-28 2008-07-15 Rambus, Inc. Periodic calibration for communication channels by drift tracking
US7095789B2 (en) * 2004-01-28 2006-08-22 Rambus, Inc. Communication channel calibration for drift conditions
US7516029B2 (en) * 2004-06-09 2009-04-07 Rambus, Inc. Communication channel calibration using feedback
US7500131B2 (en) 2004-09-07 2009-03-03 Intel Corporation Training pattern based de-skew mechanism and frame alignment
US20080130815A1 (en) * 2006-12-05 2008-06-05 Kumar S Reji Selective tracking of serial communication link data
US7467056B2 (en) * 2007-03-09 2008-12-16 Nortel Networks Limited Method and apparatus for aligning multiple outputs of an FPGA
US7590789B2 (en) * 2007-12-07 2009-09-15 Intel Corporation Optimizing clock crossing and data path latency
US8307265B2 (en) 2009-03-09 2012-11-06 Intel Corporation Interconnection techniques
US20110040902A1 (en) 2009-08-13 2011-02-17 Housty Oswin E Compensation engine for training double data rate delays
US8582706B2 (en) * 2009-10-29 2013-11-12 National Instruments Corporation Training a data path for parallel data transfer
KR101110820B1 (ko) * 2010-05-28 2012-02-27 주식회사 하이닉스반도체 슬레이브 장치, 마스터 장치와 슬레이브 장치를 포함하는 시스템 및 동작방법, 칩 패키지
US8681839B2 (en) 2010-10-27 2014-03-25 International Business Machines Corporation Calibration of multiple parallel data communications lines for high skew conditions
US8767531B2 (en) * 2010-10-27 2014-07-01 International Business Machines Corporation Dynamic fault detection and repair in a data communications mechanism
US8774228B2 (en) * 2011-06-10 2014-07-08 International Business Machines Corporation Timing recovery method and apparatus for an input/output bus with link redundancy
US8826092B2 (en) * 2011-10-25 2014-09-02 International Business Machines Corporation Characterization and validation of processor links
US9577816B2 (en) * 2012-03-13 2017-02-21 Rambus Inc. Clock and data recovery having shared clock generator
US9071407B2 (en) * 2012-05-02 2015-06-30 Ramnus Inc. Receiver clock test circuitry and related methods and apparatuses
US8760946B2 (en) * 2012-05-22 2014-06-24 Advanced Micro Devices Method and apparatus for memory access delay training
US9030341B2 (en) 2012-06-27 2015-05-12 Broadcom Corporation Compensation for lane imbalance in a multi-lane analog-to-digital converter (ADC)
US20140281085A1 (en) 2013-03-15 2014-09-18 Gregory L. Ebert Method, apparatus, system for hybrid lane stalling or no-lock bus architectures
CN103560785B (zh) * 2013-10-28 2017-05-10 中国电子科技集团公司第四十一研究所 一种产生相位相干信号的方法与装置
US9036757B1 (en) 2014-09-23 2015-05-19 Oracle International Corporation Post-cursor locking point adjustment for clock data recovery
DE112015006953B4 (de) * 2015-09-26 2025-07-10 Intel Corporation Training einer gültigen lane
US10749756B2 (en) 2016-06-24 2020-08-18 Advanced Micro Devices, Inc. Channel training using a replica lane

Also Published As

Publication number Publication date
US20210028995A1 (en) 2021-01-28
US11805026B2 (en) 2023-10-31
JP2019525507A (ja) 2019-09-05
CN109076036B (zh) 2022-01-28
US10749756B2 (en) 2020-08-18
KR102572281B1 (ko) 2023-08-29
KR20190011727A (ko) 2019-02-07
US20170373944A1 (en) 2017-12-28
CN109076036A (zh) 2018-12-21
WO2017222578A1 (en) 2017-12-28

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