CN108922923A - 一种槽栅双极型晶体管 - Google Patents

一种槽栅双极型晶体管 Download PDF

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CN108922923A
CN108922923A CN201810748803.3A CN201810748803A CN108922923A CN 108922923 A CN108922923 A CN 108922923A CN 201810748803 A CN201810748803 A CN 201810748803A CN 108922923 A CN108922923 A CN 108922923A
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CN108922923B (zh
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陈万军
许晓锐
刘超
张波
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University of Electronic Science and Technology of China
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • H01L29/7396Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004Base region of bipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • H01L29/4236Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

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Abstract

本发明属于半导体器件技术领域,具体的说涉及一种槽栅双极型晶体管。本发明属于三维结构,主要方案是采用封闭状沟槽栅结构,并往沟槽栅反向水平缩小了P型基区,使得沟槽结构能更充分的与N‑漂移区1接触,形成产生反型层沟道的反型栅结构和产生电子积累层的积累栅结构。所以,在器件导通的时候,积累栅产生的电子积累层通过反型栅产生的沟道相连到发射极上去,形成发射极双注入,电子注入的效率被极大增强,降低了导通压降。此外,本发明采用微小的分离的P型基区,减少了反偏PN结对N漂移区中空穴的抽取,提高了发射极一侧载流子的浓度,起到了辅助降低导通压降的作用。

Description

一种槽栅双极型晶体管
技术领域
本发明属于半导体技术领域,具体的说涉及一种槽栅双极型晶体管(TrenchInsulated Gate Bipolar Transisitor,简称:TIGBT)。
背景技术
高压功率半导体器件是功率电子的重要组成部分,在诸如动力系统中的电机驱动,消费电子中变频等领域具有广泛的应用。在应用中,高压功率半导体器件需要具有低导通功耗,大导通电流,高电压阻断能力,栅驱动简单,低开关损耗等特性。绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor,简称:IGBT)由于其在中高压电力电子领域中展现出优越的性能而得到广泛的应用。但是,IGBT作为一种双极型器件,其关键参数导通压降与关断损耗之间存在折中关系,如何优化这折中关系成为提高IGBT性能的关键。
发明内容
本发明所要解决的,就是针对上述问题,提出一种发射极双注入槽栅型IGBT结构(可称为DI-IGBT),对IGBT导通压降和关断损耗的折中关系进行优化。
为实现上述目的,本发明采用如下技术方案:
一种槽栅双极型晶体管,其元胞结构包括从下至上依次层叠设置金属化集电极11、P+集电极区10、N+缓存层9和N-漂移区1;所述N-漂移区1上层外围具有闭合的沟槽栅结构,在N-漂移区1上层两侧还分别具有呈对称分布的P型基区2、N+发射区6和P+接触区7,其中P型基区2和N+发射区6与沟槽栅接触,P型基区2位于N+发射区6和P+接触区7下方,N+发射区6和P+接触区7并列设置;在N+发射区6和P+接触区7上表面还具有金属化发射极8;在N-漂移区1上层中部还具有沟槽栅结构,使每个元胞上层形成2个由沟槽栅闭合的区域;其特征在于,所述P型基区2的结深小于沟槽栅的结深,沿器件横向方向,P型基区2的宽度小于N+发射区6和P+接触区7的宽度;器件元胞的布局规则为:以器件的俯视平面建立平面直角坐标系,沿水平方向,每个元胞并列排列,沿垂直方向,相邻元胞之间以水平方向偏离半个元胞长度为基准,呈交错分布。
上述方案中,与N+发射区6接触的沟槽栅为反型栅,其他的为积累栅,P型基区2往反型栅方向水平缩小为微型区域,使得槽栅结构有更多的面积和N-漂移区1直接接触;器件结构为三维结构,采用封闭形沟槽窗口,将积累栅产生的电子积累层通过反型栅产生的沟道与发射极连接到一起。
本发明总的技术方案,主要有两点,一是本器件为三维结构器件,不同于GFP-IGBT中条状的积累栅和反型栅交替平行出现[许晓锐,一种槽栅双极型晶体管,201710082601.5],本结构通过采用封闭形沟槽窗口,将积累栅产生的电子积累层连接到沟道上去,形成双注入模式,沟槽栅的窗口形状和尺寸比根据实际器件性能要求设计。二是将常规绝缘栅双极管的P型基区结构进行改进,即把常规IGBT的P型基区往反型栅方向水平缩小,使得更多的沟槽结构与N-漂移区1直接接触形成积累栅结构,微P型基区的结深和横向长度根据实际器件性能要求设计。本发明拥有与当前商业IGBT相兼容的工艺流程。
本发明的有益效果为,通过提出新结构槽栅双极型晶体管(DI-IGBT),在不改变器件参数的前提下,优化了IGBT导通压降和关断损耗之间的折中关系,降低了功率损耗。
附图说明
图1是本发明的DI-IGBT元胞排布示意图;
图2是本发明的DI-IGBT三维结构示意图;
图3是本发明的DI-IGBT三维结构的正视图;
图4是本发明的DI-IGBT三维结构的侧视图;
图5是常规的IGBT与本发明提供的DI-IGBT的耐压电压比较图;
图6是常规的IGBT与本发明提供的DI-IGBT的阈值电压比较图;
图7是常规的IGBT与本发明提供的DI-IGBT的导通压降比较图;
图8是常规的IGBT与本发明提供的DI-IGBT在相同导通压降下的关断特性比较图;
图9是常规的IGBT与本发明提供的DI-IGBT的折中曲线比较图;
具体实施方式
下面结合附图,详细描述本发明的技术方案:
本发明提出的一种具有发射极双注入的槽栅双极型晶体管,闭合栅结构(方形、圆形、正六边形、圆形等,本发明以方形结构为代表研究)示意图如图1,2,3,4,优化了IGBT导通压降和关断损耗之间的折中关系,降低了功率损耗。本发明的主要方案是适当缩小P型基区,使得沟槽结构能更多的与N-漂移区层接触,形成积累栅结构,并且通过采用闭合状的槽栅结构,将积累栅产生的电子积累层通过反型栅产生的沟道连接到发射极上去,从而实现发射极双注入,获得低导通压降。并且,缩小P型基区也可以减少反偏PN结对N漂移区中空穴的抽取,对降低导通压降起辅助作用。
一种槽栅双极型晶体管,其元胞布局如图1所示,方框AA’的三维结构截图如图2所示,线BB’和CC’的剖面图如图3和图4所示;包括集电极结构、漂移区结构、发射极结构和沟槽结构;所述集电极结构包括P+集电极区10和位于P+集电极区10下表面的金属化集电极11;所述漂移区结构包括N+缓存层9和位于N+缓存层9上表面的N-漂移区层1,所述N+缓存层9位于P+集电极区10的上表面;所述发射极结构包括P型基区2、P+接触区7、N+发射区6和金属化发射极8,所述发射极结构位于N-漂移区层1的上层;所述N+发射区6位于器件元胞上表面的两端,且P+接触区7位于相邻两个沟槽结构之间,所述金属化发射极8位于P+接触区7和N+发射区6的上表面;所述沟槽采用封闭状窗口,其结构由栅氧化层3、多晶硅栅4和金属化栅极5构成,所述栅氧化层3沿器件垂直方向延伸入N-漂移区层1中形成沟槽,所述栅氧化层3的侧面与P型基区2、N+发射区6和N-漂移区1接触;所述多晶硅栅4位于沟槽中,所述金属化栅极5位于多晶硅栅4的上表面;其特征在于,所述沟槽结构包括反型栅结构和积累栅结构,反型栅结构侧面与N+发射区6、P型基区2、N-漂移区层1接触;积累栅结构侧面只与N-漂移区层1接触;所述的P型基区2往反型栅方向水平缩小为微型区域,使得槽栅结构有更多的面积和N-漂移区1直接接触;所述的器件结构为三维结构,采用封闭形沟槽窗口,将积累栅产生的电子积累层通过反型栅产生的沟道与发射极连接到一起。
本发明总的技术方案,主要有两点,一是本器件为三维结构器件,不同于GFP-IGBT中条状的积累栅和反型栅交替平行出现[许晓锐,一种槽栅双极型晶体管,201710082601.5],本结构通过采用封闭形沟槽窗口,将积累栅产生的电子积累层连接到沟道上去,形成双注入模式,沟槽栅的窗口形状和尺寸比根据实际器件性能要求设计。二是将常规绝缘栅双极管的P型基区结构进行改进,即把常规IGBT的P型基区往反型栅方向水平缩小,使得更多的沟槽结构与N-漂移区1直接接触形成积累栅结构,微P型基区的结深和横向长度根据实际器件性能要求设计。本发明拥有与当前商业IGBT相兼容的工艺流程。
本发明工作原理:在所述器件的金属化集电极11上加正电压,在金属化发射极8上加零电压,使栅极上加上大于阈值电压的正电压,则器件开启。由于DI-IGBT的P型基区被缩小,使得一部分槽栅结构直接与N-漂移区接触变成产生电子积累层的积累栅,并且DI-IGBT采用闭合状的积累栅中插入一个反型栅,将积累栅产生的电子积累层和反型沟道连接到一起,实现发射极双注入,极大增加了电子注入的效率,导通压降得以降低。此外,由于微小的P型基区存在,减少了反偏PN结对N漂移区中空穴的抽取,提高了电导调制效应,起到了辅助降低导通压降的作用。
当器件在相同集电极浓度下关断时,由于发射极双注入,DI-IGBT导通时有高浓度的载流子积累在发射极一侧,但是这些过剩载流子在器件关断过程中会被扩展的耗尽层迅速抽走,对电流下降时间基本没有影响。也就是说,DI-IGBT在不影响关断功耗的前提下有更低的导通功耗。
另一方面,器件在相同导通压降关断时,由于注入增强效应,DI-IGBT储存更少的过剩载流子在N缓冲层中,这部分载流子无法被耗尽层扫走,只能依靠复合来消除。所以,DI-IGBT在N缓冲层中更少的载流子储存导致更短的拖尾电流和更低的关断功耗。
对本发明提供的DI-IGBT和常规IGBT(C-IGBT)结构进行仿真对比,进一步证实了本结构的优越性。图5和图6给出了DI-IGBT和C-IGBT的耐压特性和阈值电压的对比。为了保证公平比较,必须保证DI-IGBT拥有与C-IGBT一致的阻断能力和阈值电压;图7给出了DI-IGBT和C-IGBT导通压降的对比。从图7可以看出,在室温下,DI-IGBT导通压降从1.93V降低到1.35V,实现了30%的降低量。
图8给出了DI-IGBT和C-IGBT在导通压降均为1.35V下的关断曲线对比。由于关断时候,储存在N+缓存层中的少子只能依靠复合来移除,引起较长的电流拖尾,从而增大电流下降时间和关断功耗。而在相同导通压降下,由于显著的电导调制效应,DI-IGBT在导通时有较少的少子储存在N+缓存层中。所以,DI-IGBT拥有更短的电流下降时间。其结果如图7所示,相比与C-IGBT,DI-IGBT的关断时间减少了451ns(89%)。图8给出了DI-IGBT和C-IGBT的导通压降和关断损耗折中关系曲线。有图可知,DI-IGBT拥有更加优化的导通压降和关断损耗的折中曲线。在导通压降为1.35V下,DI-IGBT的关断损耗为3.12mJ/cm2,C-IGBT的关断损耗为11.85mJ/cm2。DI-IGBT的关断损耗比C-IGBT少8.73mJ/cm2(74%)。在关断损耗为3.12mJ/cm2下,DI-IGBT的导通压降为1.35V,C-IGBT的导通压降为1.93V。DI-IGBT的导通压降比C-IGBT少0.58V(30%)。
通过对导通、关断状态下的关键参数比较,直观地展示出了本发明结构相对与常规IGBT结构在中高压功率半导体器件应用上所具有的“低功耗”的性能优势。

Claims (1)

1.一种槽栅双极型晶体管,其元胞结构包括从下至上依次层叠设置金属化集电极(11)、P+集电极区(10)、N+缓存层(9)和N-漂移区(1);所述N-漂移区(1)上层外围具有闭合的沟槽栅结构,在N-漂移区(1)上层两侧还分别具有呈对称分布的P型基区(2)、N+发射区(6)和P+接触区(7),其中P型基区(2)和N+发射区(6)与沟槽栅接触,P型基区(2)位于N+发射区(6)和P+接触区(7)下方,N+发射区(6)和P+接触区(7)并列设置;在N+发射区(6)和P+接触区(7)上表面还具有金属化发射极(8);在N-漂移区(1)上层中部还具有沟槽栅结构,使每个元胞上层形成2个由沟槽栅闭合的区域;其特征在于,所述P型基区(2)的结深小于沟槽栅的结深,沿器件横向方向,P型基区(2)的宽度小于N+发射区(6)和P+接触区(7)的宽度;器件元胞的布局规则为:以器件的俯视平面建立平面直角坐标系,沿水平方向,每个元胞并列排列,沿垂直方向,相邻元胞之间以水平方向偏离半个元胞长度为基准,呈交错分布。
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