CN108878542B - 半导体元件 - Google Patents

半导体元件 Download PDF

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CN108878542B
CN108878542B CN201711103021.6A CN201711103021A CN108878542B CN 108878542 B CN108878542 B CN 108878542B CN 201711103021 A CN201711103021 A CN 201711103021A CN 108878542 B CN108878542 B CN 108878542B
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doped region
region
diode
type doped
metal layer
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CN108878542A (zh
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韦维克
陈柏安
苏柏拉曼亚·加亚谢拉拉欧
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Nuvoton Technology Corp
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Abstract

本发明提供一种半导体元件，包括基底、隔离结构、二极管元件以及第一金属层。隔离结构位于基底中。二极管元件位于隔离结构上，其中二极管元件包括P型掺杂区、N型掺杂区与本征区，且本征区位于P型掺杂区与N型掺杂区之间。位于二极管元件两端的P型掺杂区与N型掺杂区各自形成欧姆接触。第一金属层与二极管元件的本征区电连接并形成萧特基接触以构成至少一萧特基二极管。本发明能够有效地提升元件效能、缩小元件尺寸并节省成本。

Description

半导体元件
技术领域
本发明是有关于一种半导体元件，且特别是有关于一种整合二极管元件与萧特基二极管(Schottky Barrier Diode)结构的一种半导体元件。
背景技术
在传统的半导体元件中，为了降低贯通电流(shoot through current)一般是利用萧特基二极管(Schottky Barrier Diode)来保护半导体元件并减少导通电阻和栅极电容，进而可减少功率损耗、增加半导体功率元件的开关切换速度。已知的方法是利用外接的方式将萧特基二极管与金属氧化物半导体场效应晶体管(metal oxide silicon fieldeffect transistor；MOSFET)做整合，又或是将萧特基二极管与金属氧化物半导体场效应晶体管一起封装。然而，传统的萧特基二极管的设置方式较占空间且制作成本较高，因此，如何提升元件效能、缩小元件尺寸并节省成本，实为目前的重要趋势。
发明内容
本发明提供一种半导体元件，可将萧特基二极管与二极管元件做整合以缩小元件尺寸并提升元件效能。
本发明的半导体元件包括基底、隔离结构、二极管元件以及第一金属层。隔离结构位于基底中。二极管元件位于隔离结构上，其中二极管元件包括P型掺杂区、N型掺杂区与本征区，且本征区位于P型掺杂区与N型掺杂区之间，且位于该二极管元件的两端的P型掺杂区与N型掺杂区各自形成欧姆接触(ohmic contact)。第一金属层与二极管元件的本征区电连接形成萧特基接触(Schottky contact)以构成至少一萧特基二极管。
在本发明的一实施例中，上述的二极管元件的本征区包括主体部分以及与主体部分连接的至少一凸出部分。凸出部分延伸至P型掺杂区中，且第一金属层与本征区的凸出部分及P型掺杂区电连接以构成萧特基二极管。
在本发明的一实施例中，上述的半导体元件更包括晶体管位于主动区中。晶体管包括栅极、第一掺杂区与第二掺杂区。栅极位于基底上，且第一掺杂区与第二掺杂区分别位于栅极的两侧的基底中。
在本发明的一实施例中，上述的二极管元件的P型掺杂区邻近于第一掺杂区与第二掺杂区中的一个设置，N型掺杂区邻近于第一掺杂区与第二掺杂区中的另一个设置。
在本发明的一实施例中，上述的隔离结构位于第二掺杂区与栅极之间，且二极管元件位于第二掺杂区与栅极之间的隔离结构上。
在本发明的一实施例中，上述的第一金属层与晶体管的第一掺杂区以及第二掺杂区中的一个电连接。
在本发明的一实施例中，上述的半导体元件更包括第二金属层，其中第二金属层与第一掺杂区以及第二掺杂区中的另一个电连接，且与N型掺杂区电连接。
在本发明的一实施例中，上述的二极管元件是设置在隔离结构上，且P型掺杂区、N型掺杂区以及本征区分别与隔离结构接触。
基于上述，在本发明的半导体元件中，由于第一金属层与二极管元件的本征区电连接并构成至少一萧特基二极管，因此，能够将萧特基二极管与二极管元件做整合，并且，能够有效地提升元件效能、缩小元件尺寸并节省成本。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附图式作详细说明如下。
附图说明
图1A为依照本发明一实施例的半导体元件的上视示意图。
图1B为图1A中A-A’线的剖面图。
图1C为图1A中二极管元件120的上视示意图。
图2A为依照本发明另一实施例的半导体元件的上视示意图。
图2B为图2A中B-B’线的剖面图。
图3为依照本发明另一实施例的半导体元件的剖面示意图。
图4为依照本发明另一实施例的半导体元件的剖面示意图。
图5为依照本发明另一实施例的半导体元件的剖面示意图。
附图标号
10、20、30、40、50：半导体元件
110：基底
112：隔离结构
115：绝缘层
120：二极管元件
122：P型掺杂区
124：N型掺杂区
126：本征区
126a：主体部分
126b：凸出部分
130：第一金属层
140：第二金属层
200：晶体管
202：栅极
204：第一掺杂区
206：第二掺杂区
AR：主动区
CW：接触开口
SBD：萧特基二极管
A-A’，B-B’：线
具体实施方式
图1A为依照本发明一实施例的半导体元件的上视示意图。图1B为图1A中A-A’线的剖面图。图1C为图1A中二极管元件120的上视示意图。请同时参考图1A、图1B及图1C，本实施例的半导体元件10包括基底110、隔离结构112、二极管元件120、第一金属层130、第二金属层140以及晶体管200。在本实施例中，基底110包括硅基底、绝缘层上覆硅(SOI)基底或III-V族半导体基底，但不限于此。另外，III-V族半导体基底可为SiC基底、GaAs基底或GaN基底。
如图1A及图1B的实施例所示，半导体元件10例如为对应金属氧化物半导体场效应晶体管(MOSFET)。更详细来说，本实施例的半导体元件10包括有晶体管200位于主动区AR中。晶体管200包括栅极202、第一掺杂区204与第二掺杂区206，其中，栅极202位于基底110上，且第一掺杂区204与第二掺杂区206分别位于栅极202的两侧的基底110中。第一掺杂区204可例如为晶体管200的源极区与漏极区的其中一个，而第二掺杂区206可例如为晶体管200的源极区与漏极区的其中另一个。另外，如图1B所示，隔离结构112是设置在基底110中，作为隔离晶体管200的元件以定义出主动区AR(图1A省略绘示隔离结构112)。在本实施例中，隔离结构112可为浅沟渠绝缘层(shallow trench isolation；STI)，但本发明不限于此。在其它实施例中，隔离结构112可为埋入氧化层(buried oxide；BOX)或是场氧化层(field oxide；FOX)。另外，隔离结构112的材料例如可包括氧化硅。
在本实施例中，二极管元件120是设置在隔离结构112上，其中，二极管元件120例如是PIN二极管。此外，二极管元件120为另外形成的多晶硅层或单晶硅层或是非晶硅层，而对多晶硅层或单晶硅层或是非晶硅层掺杂所形成。二极管元件120包括P型掺杂区122、N型掺杂区124与本征区126。本征区126是没有被掺杂的区域，其载子的浓度维持硅材料的本质浓度，远低于P型掺杂区域122与N型掺杂区域124的载子浓度。此外，在本实施例中，二极管元件120的P型掺杂区122、N型掺杂区124以及本征区126是分别设置在隔离结构112上并与隔离结构112接触。也就是说，二极管元件120的P型掺杂区122、N型掺杂区124以及本征区126是水平式地设置在隔离结构112上。
再来，请继续参考图1A、图1B及图1C，在本实施例中，二极管元件120的本征区126具有主体部分126a以及与主体部分126a连接的至少一凸出部分126b，且凸出部分126b是延伸至P型掺杂区122中。位于二极管元件120两端的P型掺杂区122与N型掺杂区124各自形成欧姆接触。另外，第一金属层130与本征区126的凸出部分126b及P型掺杂区122电连接形成萧特基接触以构成萧特基二极管SBD。更详细来说，如图1B所示，二极管元件120与晶体管200上覆盖有绝缘层115(图1A省略绘示绝缘层115)，且第一金属层130是通过绝缘层115的接触开口CW与本征区126的凸出部分126b及P型掺杂区122电连接。相同地，第一金属层130是通过绝缘层115的接触开口CW与晶体管200的第一掺杂区204电连接。在本实施例中，第一金属层130的材料包括金属，例如铝、铜或其合金。因此，通过第一金属层130的金属材料与本征区126b的半导体材料所形成的金属-半导体接面可构成所述萧特基二极管SBD，而通过第一金属层130的金属材料与本征区126b两旁的P型掺杂区122所形成的金属-半导体接面则可降低萧特基二极管SBD的漏电流。
在本发明实施例中，第一金属层130可与第一掺杂区204以及第二掺杂区206中的一个电连接，而第二金属层140可与第一掺杂区204以及第二掺杂区206中的另一个电连接，且与N型掺杂区124电连接。如图1A、图1B所示，第一掺杂区204例如为源极区且第二掺杂区206例如为漏极区，其中，第一金属层130是与第一掺杂区204电连接，而第二金属层140是与第二掺杂区206电连接，且与N型掺杂区124电连接。另外，如图1B所示，第二金属层140是通过绝缘层115的接触开口CW与N型掺杂区124以及第二掺杂区206电连接。然而，本发明不以上述的连接方式为限。在另一实施例中，第一掺杂区204例如为漏极区且第二掺杂区206例如为源极区，其中，第一金属层130是与第二掺杂区206电连接，而第二金属层140是与第一掺杂区204电连接，且与N型掺杂区124电连接。
由此可知，在任一实施例中，只要第一金属层130是电连接至本征区126以及源极区与漏极区的其中一个，而第二金属层140是连接至N型掺杂区124以及源极区与漏极区的其中另一个，即可达成本发明所述的连接关系。
在图1A、图1B及图1C的实施例中，由于第一金属层130通过接触开口CW与二极管元件120的本征区126及P型掺杂区122接触而形成萧特基二极管SBD，因此，能够将萧特基二极管SBD与二极管元件120做整合而形成一种嵌入式结构(embedded structure)。也就是说，与传统外接的萧特基二极管相比，本发明的半导体元件10能够有效地缩小元件尺寸并节省成本。进一步地，将二极管元件120与萧特基二极管SBD有效整合，能够同时达到高击穿电压、开关速度快与降低贯通电流等优点，并提升元件的整体效能。
图2A为依照本发明另一实施例的半导体元件的上视示意图。图2B为图2A中B-B’线的剖面图。图2A以及图2B的实施例与图1A、图1B以及图1C的实施例类似，因此，相同元件以相同标号表示，且不予赘述。图2A以及图2B与图1A、图1B以及图1C的差异在于，图2A以及图2B的半导体元件200例如为对应横向扩散金属氧化物半导体晶体管(Lateral DiffusedMetal Oxide Semiconductor；LDMOS)。
如图2A及图2B所示，半导体元件20包括有晶体管200位于主动区AR中。晶体管200包括栅极202、第一掺杂区204与第二掺杂区206，其中，栅极202位于基底110上，且第一掺杂区204与第二掺杂区206分别位于栅极202的两侧的基底110中。第一掺杂区204可例如为晶体管200的源极区，而第二掺杂区206可例如为晶体管200的漏极区。另外，如图2B所示，隔离结构112是设置在基底110中，以定义出主动区AR(图2A省略绘示隔离结构112)。在本实施例中，隔离结构112为场氧化层，但不特别以此为限。此外，在本实施例中，隔离结构112位于第二掺杂区206与栅极202之间，且二极管元件120位于第二掺杂区206与栅极202之间的隔离结构112上。然而，本发明不限于此。在另一实施例中，隔离结构112亦可位于第一掺杂区204与栅极202之间，且二极管元件120位于第一掺杂区204与栅极202之间的隔离结构112上。
在图2A及图2B的实施例中，第一金属层130是通过绝缘层115的接触开口CW与本征区126的凸出部分126b及P型掺杂区122电连接。通过第一金属层130的金属材料与本征区126的半导体材料所形成的金属-半导体接面可构成所述萧特基二极管SBD。另外，通过第一金属层130的金属材料与本征区126b两旁的P型掺杂区122所形成的金属-半导体接面则可降低萧特基二极管SBD的漏电流。在本实施例中，由于第一金属层130通过接触开口CW与二极管元件120的本征区126及P型掺杂区122接触而形成萧特基二极管SBD，因此，能够将萧特基二极管SBD与二极管元件120做整合而形成一种嵌入式结构。也就是说，与传统外接的萧特基二极管相比，本发明的半导体元件20能够有效地缩小元件尺寸并节省成本。进一步地，将二极管元件120与萧特基二极管SBD有效整合，能够同时达到高击穿电压、开关速度快与降低贯通电流等优点，并提升元件的整体效能。
图3为依照本发明另一实施例的半导体元件的剖面示意图。图3的实施例与图2A的实施例类似，因此，相同元件以相同标号表示，且不予赘述。图3与图2A的差异在于，图3的半导体元件30的二极管元件120的设置位置不同。具体来说，于图3的实施例中，二极管元件120的P型掺杂区122邻近于第一掺杂区204设置，N型掺杂区124邻近于第二掺杂区206设置，而本征区126邻近于栅极202设置。然而，本发明不限于此。在另一实施例中，二极管元件120的P型掺杂区122邻近于第二掺杂区206设置，N型掺杂区124邻近于第一掺杂区204设置，而本征区126邻近于栅极202设置。另外，在图3的实施例中，第一金属层130同样是与本征区126、P型掺杂区122以及第一掺杂区204电连接，而第二金属层140同样是与N型掺杂区124以及第二掺杂区206电连接，差异仅在于第一金属层130与第二金属层140的设置方式会随着二极管元件120的位置改变而进行调整。
相同地，在图3的实施例中，由于第一金属层130通过接触开口CW与二极管元件120的本征区126及P型掺杂区122接触而形成萧特基二极管SBD，因此，能够将萧特基二极管SBD与二极管元件120做整合而形成一种嵌入式结构。也就是说，与传统外接的萧特基二极管相比，本发明的半导体元件30能够有效地缩小元件尺寸并节省成本。进一步地，将二极管元件120与萧特基二极管SBD有效整合，能够同时达到高击穿电压、开关速度快与降低贯通电流等优点，并提升元件的整体效能。
图4为依照本发明另一实施例的半导体元件的剖面示意图。图4的实施例与图2A的实施例类似，因此，相同元件以相同标号表示，且不予赘述。图4与图2A的差异在于，图4的半导体元件40的二极管元件120的设置位置不同。具体来说，于图4的实施例中，二极管元件120是位于晶体管200的第一掺杂区204的一侧，并邻近于晶体管200的第一掺杂区204，且远离第二掺杂区206。然而，本发明不限于此。在另一实施例中，二极管元件120亦可设置于第二掺杂区206的一侧，并邻近于晶体管200的第二掺杂区206，且远离第一掺杂区204。另外，在本实施例中，第一金属层130同样是与本征区126、P型掺杂区122以及第一掺杂区204电连接，而第二金属层140同样是与N型掺杂区124以及第二掺杂区206电连接，差异仅在于第一金属层130与第二金属层140的设置方式会随着二极管元件120的位置改变而进行调整。
相同地，在图4的实施例中，由于第一金属层130通过接触开口CW与二极管元件120的本征区126及P型掺杂区122接触而形成萧特基二极管SBD，因此，能够将萧特基二极管SBD与二极管元件120做整合而形成一种嵌入式结构。也就是说，与传统外接的萧特基二极管相比，本发明的半导体元件40能够有效地缩小元件尺寸并节省成本。进一步地，将二极管元件120与萧特基二极管SBD有效整合，能够同时达到高击穿电压、开关速度快与降低贯通电流等优点，并提升元件的整体效能。
图5为依照本发明另一实施例的半导体元件的剖面示意图。图5的实施例与图3的实施例类似，因此，相同元件以相同标号表示，且不予赘述。图5与图3的差异在于，图5的半导体元件40的本征区126具有多个凸出部分126b，以构成具有指状外观的本征区126。更详细来说，第一金属层130是延伸至多个凸出部分126b上方，并通过接触开口CW分别与二极管元件120的多个凸出部分126b及P型掺杂区122电连接形成萧特基接触，以构成多个萧特基二极管SBD。
相同地，在图5的实施例中，由于第一金属层130通过接触开口CW与二极管元件120的本征区126及P型掺杂区122接触而形成萧特基二极管SBD，因此，能够将萧特基二极管SBD与二极管元件120做整合而形成一种嵌入式结构。也就是说，与传统外接的萧特基二极管相比，本发明的半导体元件50能够有效地缩小元件尺寸并节省成本。进一步地，将二极管元件120与萧特基二极管SBD有效整合，能够同时达到高击穿电压、开关速度快与降低贯通电流等优点，并提升元件的整体效能。
综上所述，在图1A至图5的实施例中，所述的半导体元件皆包括位于隔离结构上的二极管元件，其中，第一金属层与二极管元件的本征区电连接形成萧特基接触，以构成至少一萧特基二极管。因此，本发明能够将萧特基二极管与二极管元件做整合而形成一种嵌入式结构。也就是说，与传统外接的萧特基二极管相比，本发明的半导体元件能够有效地缩小元件尺寸并节省成本，使整体设计更有弹性空间。进一步地，将二极管元件与萧特基二极管有效整合，能够同时达到高击穿电压、开关速度快与降低贯通电流等优点，并提升元件的整体效能。
虽然本发明已以实施例揭露如上，然其并非用以限定本发明，任何所属技术领域中相关技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视权利要求所界定者为准。

Claims (7)

1.一种半导体元件，其特征在于，包括：
一基底；
一隔离结构，位于该基底中；
一二极管元件，位于该隔离结构上，其中该二极管元件包括一P型掺杂区、一N型掺杂区与一本征区，该本征区位于该P型掺杂区与该N型掺杂区之间，且位于该二极管元件两端的该P型掺杂区与该N型掺杂区各自形成欧姆接触；以及
一第一金属层，与该二极管元件的该本征区电连接形成萧特基接触以构成至少一萧特基二极管；
一晶体管，位于一主动区中，该隔离结构定义出该主动区，且该晶体管包括一栅极、一第一掺杂区与一第二掺杂区，其中该栅极位于该基底上，且该第一掺杂区与该第二掺杂区分别位于该栅极的两侧的该基底中。
2.如权利要求1所述的半导体元件，其特征在于，该二极管元件的该本征区包括一主体部分以及与该主体部分连接的至少一凸出部分，该凸出部分延伸至该P型掺杂区中，且该第一金属层与该本征区的该凸出部分及该P型掺杂区电连接以构成该萧特基二极管。
3.如权利要求1所述的半导体元件，其特征在于，该二极管元件的该P型掺杂区邻近于该第一掺杂区与该第二掺杂区中的一个设置，该N型掺杂区邻近于该第一掺杂区与该第二掺杂区中的另一个设置。
4.如权利要求1所述的半导体元件，其特征在于，该隔离结构位于该第二掺杂区与该栅极之间，且该二极管元件位于该第二掺杂区与该栅极之间的该隔离结构上。
5.如权利要求1所述的半导体元件，其特征在于，该第一金属层与该第一掺杂区以及该第二掺杂区中的一个电连接。
6.如权利要求5所述的半导体元件，其特征在于，更包括一第二金属层，其中该第二金属层与该第一掺杂区以及该第二掺杂区中的另一个电连接，且与该N型掺杂区电连接。
7.如权利要求1所述的半导体元件，其特征在于，该二极管元件是设置在该隔离结构上，且该P型掺杂区、该N型掺杂区以及该本征区分别与该隔离结构接触。
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