CN108874167B

CN108874167B - Keyboard state change pulse generating circuit

Info

Publication number: CN108874167B
Application number: CN201810660631.4A
Authority: CN
Inventors: 肖会芹; 凌云; 肖伸平; 曾红兵; 孔玲爽
Original assignee: Hunan University of Technology
Current assignee: Hunan University of Technology
Priority date: 2016-01-05
Filing date: 2016-01-05
Publication date: 2021-02-26
Anticipated expiration: 2036-01-05
Also published as: CN108880561B; CN108874167A; CN108880561A; CN105703780A; CN105703780B

Abstract

A keyboard state change pulse generating circuit is composed of an OR gate, an M-bit delay buffer and M XOR gates; the M-bit delay buffer is used for respectively carrying out signal delay on the M-bit key numbers output by the keyboard scanning positioning circuit; the inputs of the M exclusive-OR gates are input signals and output signals of the M-bit delay buffer respectively; the outputs of the M exclusive-OR gates are respectively connected to the input ends of the OR gates; the output end of the OR gate outputs a keyboard state change pulse. The keyboard scanning positioning circuit is realized by a circuit consisting of a matrix keyboard, a buffer register, a state code register and an encoder, and if the key operation function needs to be increased or decreased or adjusted, the circuit structure does not need to be modified, and only the encoding content of the encoder needs to be changed. The method does not need to write and run programs and works reliably.

Description

Keyboard state change pulse generating circuit

The invention discloses a matrix type keyboard scanning positioning circuit, which is a divisional application with an original application number of 201610003614.4 and an application date of 2016, 1 and 5.

Technical Field

The invention relates to a keyboard scanning circuit, in particular to a keyboard state change pulse generating circuit.

Background

With the continuous development of embedded technology, various electronic products generally adopt a microcontroller as a control core and a keyboard as a main input device, and are widely applied.

The existing keyboard scanning is mainly controlled by a microcontroller, and is performed by running a program in the microcontroller, so that the program runs off due to interference, and the scanning program cannot work normally.

The invention patent with application number CN201010153560.2, "a method for fast scanning and positioning matrix keyboard", adopts a mode of keyboard interrupt triggering to enter the scanning and positioning process of keyboard, adopts a method of repeating the keyboard scanning step for many times to judge whether the key is valid, and makes state judgment on the obtained key value; if the multiple sampling states are the same, the key value is in a stable state and is valid; if the multiple sampling states are different, the key value is invalid. The single key operation or the combined key operation needs to be judged separately, if the single key operation is carried out, the single key processing mode is entered; if the operation is a combination key operation, a combination key processing mode is entered. The method disclosed in the patent solves the problems of wrong keys, continuous key touch and other errors caused by keyboard shaking due to the mechanical characteristics of the keyboard, and the problem of supporting combined keys and repeated keys. But the single key operation and the combined key operation of the method need to be processed respectively; a keyboard operation function of executing effective operation after a certain period of time of maintaining the keyboard state is not considered; when the key operation function is increased or decreased or adjusted, the structure of the keyboard scanning and positioning program needs to be modified. When a key is pressed down, the method puts the key value of the keyboard into a queue, waits for the reading of an application program, and does not adopt a mode of outputting an interrupt signal.

Disclosure of Invention

In order to solve the technical problems of the existing keyboard scanning and positioning method, the invention provides a keyboard state change pulse generation circuit, which consists of an OR gate, an M-bit delay buffer and M exclusive OR gates; the M-bit delay buffer is used for respectively carrying out signal delay on the M-bit key numbers output by the keyboard scanning positioning circuit; the inputs of the M exclusive-OR gates are input signals and output signals of the M-bit delay buffer respectively; the outputs of the M exclusive-OR gates are respectively connected to the input ends of the OR gates; the output end of the OR gate outputs a keyboard state change pulse.

The delay buffer is an edge trigger; the trigger input ends of the edge triggers are all connected to clock pulses. The rising edge of the clock pulse is an effective triggering edge; the delay buffer latches data at the effective triggering edge of the clock pulse; the M-bit key number will only change on the active triggering edge of the clock pulse.

The keyboard scanning positioning circuit comprises a matrix keyboard, a buffer register, a state code register and an encoder. The matrix keyboard is provided with X rows and Y columns in total and is provided with N keyboard state signal output ends; the N-bit keyboard state signal is a level signal; and N is X + Y. The buffer register and the state code register are both N-bit binary registers, the N-bit data input end of the buffer register is connected to the N-bit keyboard state signal output end, the N bit of the 2 XN-bit data input end of the state code register is connected to the N-bit keyboard state signal output end, and the other N bit is connected to the N-bit data output end of the buffer register;

the encoder is provided with a 2 xN bit encoding input end, and the 2 xN bit encoding input end is connected to the 2 xN bit data output end of the state code register; the receiving pulse input end of the buffer register and the receiving pulse input end of the state code register are both connected to a clock pulse; the matrix keyboard is controlled by sampling pulses to obtain N-bit keyboard state signals. The N-bit keyboard state signal is a level signal.

The matrix keyboard consists of an X row-Y column key matrix, a row tri-state buffer, a column tri-state buffer, a row state register and a column state register; the row lines of all the key matrixes are respectively connected to the output ends of the row tri-state buffers, and the column lines of all the key matrixes are respectively connected to the output ends of the column tri-state buffers; all input ends of the row tri-state buffer and the column tri-state buffer are connected to a low level; the row lines of all the key matrixes are respectively connected to the input end of the row state register, and the column lines of all the key matrixes are respectively connected to the input end of the column state register; the output end of the row state register and the output end of the column state register jointly form a keyboard state signal output end.

When the low level of the sampling pulse is enabled to be effective, the row three-state buffer requires the column state register to carry out data latch on the rising edge of the sampling pulse, the column three-state buffer is enabled to be effective on the high level of the sampling pulse, and the row state register carries out data latch on the falling edge of the sampling pulse; alternatively, when the row tri-state buffer is enabled at the high level of the sampling pulse, the column state register is required to perform data latch at the falling edge of the sampling pulse, the column tri-state buffer is enabled at the low level of the sampling pulse, and the row state register performs data latch at the rising edge of the sampling pulse.

The buffer register and the state code register simultaneously carry out data latching on the effective triggering edge of the clock pulse; the 2 XN bit data output end of the state code register outputs a 2 XN bit state code; the state code consists of a valid state code and an invalid state code; the key number output by the encoder consists of an effective key number and an ineffective key number; the effective state codes are generated by the operation or the state of an effective keyboard, and corresponding effective key numbers are correspondingly output when the encoder inputs each effective state code; the invalid state code is generated by invalid keyboard operation or state, and when all invalid state codes are input by the encoder, an invalid key number is correspondingly output, wherein the invalid key number is a value except all valid key numbers. The value of M should be selected to satisfy 2^MGreater than or equal to the sum of the number of valid and invalid key numbers.

The N bits, 2 XN bits and M bits all refer to binary bit data. The period of the clock pulse is 20-100 ms; the period of the sampling pulse is not greater than the period of the clock pulse, and a specific example thereof is that the sampling pulse is the clock pulse.

The clock pulse and the sampling pulse are output by the oscillator, and the period of the sampling pulse is not more than that of the clock pulse. A special case of the sampling pulse is to directly use a clock pulse as the sampling pulse.

The invention has the beneficial effects that: when the key number output by the keyboard scanning positioning circuit changes, the keyboard state change pulse can be output as an interrupt request signal of the receiving device. The keyboard scanning and positioning circuit is used for positioning single key operation, combined key operation and keyboard maintenance state operation, the single key operation, the combined key operation and the keyboard maintenance state operation are converted into state codes with the same binary length through clock pulse scanning, and the state codes are processed in a unified coding mode, wherein the single key operation, the combined key operation and the keyboard maintenance state operation are only reflected on different state codes; if the key operation function needs to be increased or decreased or the key operation function needs to be adjusted, the circuit structure does not need to be modified, and the encoding content of the encoder only needs to be changed according to the corresponding relation between the increased or decreased state code and the key number, namely the storage content written into the read-only memory is modified again. The circuit does not use microcontrollers such as a single chip microcomputer and an ARM, does not need running programs, and works reliably.

Drawings

FIG. 1 is a schematic block diagram of a keyboard scanning positioning circuit;

FIG. 2 is a circuit diagram of a matrix keyboard according to an embodiment of the present invention;

FIG. 3 is a scan positioning circuit diagram of an embodiment of the present invention;

FIG. 4 is a circuit diagram of a keyboard state change pulse generation circuit according to an embodiment of the present invention;

FIG. 5 is a waveform diagram illustrating the effective operation of the keyboard according to the embodiment of the present invention.

Detailed Description

The invention is further described below with reference to the accompanying drawings.

Fig. 1 is a schematic block diagram of a keyboard scanning positioning circuit, which is composed of a matrix keyboard 400, a buffer register 100, a status code register 200, and an encoder 300, and fig. 1 further includes an oscillator 500.

The oscillator 500 is a multivibrator and has a CP clock output terminal and a CK sampling pulse output terminal, the period of the CP clock is 20-100 ms, and the period of the CK sampling pulse is not greater than the period of the CP clock.

Fig. 2 is a circuit diagram of a matrix keyboard 400 of an embodiment of the present invention, which has 2 rows, 2 columns and 4 keys, and is composed of a key S1, a key S2, a key S3, a key S4, a pull-up resistor R1 connected to a power supply + VCC, a pull-up resistor R2, a pull-up resistor R3, a pull-up resistor R4, a row tri-state buffer 401, a column tri-state buffer 402, a row state register 403, and a column state register 404. 2 output terminals Y1 and Y2 of the row tri-state buffer 401 are respectively connected to 2 row lines, and 2 output terminals Y3 and Y4 of the column tri-state buffer 402 are respectively connected to 2 column lines; all the inputs X1-X4 of the row tri-state buffer 401 and the column tri-state buffer 402 are connected to low level.

The 2 input terminals D41, D42 of the row status register 403 are connected to 2 row lines, respectively, and the 2 input terminals D43, D44 of the column status register 404 are connected to 2 column lines, respectively; the 2 output terminals Q41, Q42 of the row state register 403 output row state signals I1, I2, and the 2 output terminals Q43, Q44 of the column state register 404 output column state signals I3, I4; the 2 output terminals of the row state register 403 and the 2 output terminals of the column state register 404 form a 4-bit keyboard state signal output terminal for outputting keyboard state signals I1, I2, I3 and I4.

In an embodiment, the enable input EN1 of row tri-state buffer 401 is active low, and the enable input EN2 of column tri-state buffer 402 is active high; EN1 and EN2 are both connected to the CK sampling pulse output of oscillator 500. The receiving pulse input terminals CLK3 and CLK4 of the row state register 403 and the column state register 404 are both connected to the CK sampling pulse output terminal of the oscillator 500, the row state register 403 latches data at the falling edge of the CK sampling pulse, and the column state register 404 latches data at the rising edge of the CK sampling pulse.

When the row tri-state buffer 401 and the column tri-state buffer 402 use the same type of tri-state buffer, for example, the tri-state buffer 74HC241 is used at the same time, the enable input of 74HC241 is active high, and therefore, a not gate needs to be added between the CK sampling pulse output terminal and the enable input terminal EN1 of the row tri-state buffer 401. Similarly, when the row state register 403 and the column state register 404 use the same type of data register, for example, the row state register 403 and the column state register 404 both use the dual D flip-flop 74HC74 to form the data register, the flip-flop input of 74HC74 is active at the rising edge, and therefore, a not gate needs to be added between the CK sampling pulse output terminal and the receiving pulse input terminal CLK3 of the row state register 403.

The buffer register 100, the status code register 200 and the encoder 300 in fig. 1 constitute a scan positioning circuit, and a circuit diagram of an embodiment thereof is shown in fig. 3. The matrix keyboard circuit has 4 keys, and the keyboard status signal outputted from the matrix keyboard is 4-bit binary code, so that the buffer register 100 is required to register 4-bit binary data, and the status code register 200 is required to register 8-bit binary data. 4 data input ends of the buffer register 100 are connected to I1, I2, I3 and I4; of the 8 data inputs of the

status code register

200, 4 data inputs are connected to I1, I2, I3, I4, and the other 4 data inputs are connected to 4 outputs of the buffer register 100; the 8 inputs of the encoder 300 are connected to the 8 outputs of the status code register 200. The encoder 300 outputs a 4-bit binary key number determined by the scan location.

In fig. 3, the flip-flop 101 constitutes the buffer register 100, and the flip-flop 201 constitutes the status code register 200. The flip-flop 101 is composed of 4 edge flip-flops, and the trigger input ends of the 4 edge flip-flops are the receiving pulse input ends of the buffer register 100 and are all connected to the CP clock pulse output end of the oscillator 500; the flip-flop 201 is composed of 8 edge flip-flops, and the trigger input ends of the 8 edge flip-flops are the receiving pulse input ends of the state code register 200, and are all connected to the CP clock pulse output end of the oscillator 500. The flip-

flops

101 and 201 are preferably composed of edge-triggered D flip-flops, for example, a dual D flip-flop 74HC74 and a 4D flip-flop 74HC 175. In the embodiment of fig. 3, both the flip-flop 101 and the flip-flop 201 select the 8D flip-flop 74HC273 triggered by the rising edge, at this time, a clear input terminal not shown in fig. 3 needs to be connected to a high level, so that the clear function of the 74HC273 is in an invalid state, and only has a trigger function; the flip-flop 101 only requires 4D flip-flops, and any 4D flip-flops out of the selected 8D flip-flops 74HC273 are used. The trigger inputs CLK1, CLK2 of the two 8D flip-flops 74HC273 are both connected to CP.

In fig. 3, the rom 301 constitutes an encoder 300. The address input terminals A7-A0 of the ROM 301 are input terminals of the encoder 300, and the data output terminals D3-D0 of the ROM 301 are encoding output terminals C3-C0 of the encoder 300.

The working principle of the keyboard scanning positioning circuit is as follows:

in fig. 2, the 4 keys of the matrix keyboard are arranged in a 2 × 2 matrix, and all the row lines and column lines are connected to the power supply + VCC through pull-up resistors. The matrix keyboard is controlled by CK sampling pulses, and keyboard state signals I4, I3, I2 and I1 are obtained by an inversion method. For example, the keyboard status signal of no key press is 1111, the keyboard status signal of S1 press is 1010, and the keyboard status signal of S1, S2 press simultaneously is 0010. The 4-bit binary code of the keyboard status signal is called a key value.

The method for sampling and reading key values of the matrix keyboard by CK sampling pulse control comprises the following steps: at the low level of the CK sampling pulse, controlling all row lines to output the low level through a row three-state buffer 401, and outputting a high-resistance open column line through a column three-state buffer 402; the column state register 404 samples the read column line state as the high 2 bits of the key value on the rising edge of the CK sample pulse; at the high level of the CK sampling pulse, all column lines are controlled to output low level through the column tri-state buffer 402, and the row tri-state buffer 401 outputs high resistance state to open a row line; the row state is sampled and read by the row state register 403 as the lower 2 bits of the key value at the falling edge of the CK sampling pulse; the above process is repeated, and the 4-bit key value output by the column status register 404 and the row status register 403 is always the latest status of the matrix keyboard.

As can be seen from the method of CK sampling pulse control for sampling and reading key values for a matrix keyboard, row tri-state buffer 401 requires a column state register 404 to latch data on the rising edge of the CK sampling pulse, column tri-state buffer 402 to be enabled on the high edge of the CK sampling pulse, and row state register 403 to latch data on the falling edge of the CK sampling pulse when the low level of the CK sampling pulse is enabled. Conversely, if the row tri-state buffer 401 is enabled at the high level of the CK sample pulse, the column state register 404 is required to latch data at the falling edge of the CK sample pulse, the column tri-state buffer 402 is enabled at the low level of the CK sample pulse, and the row state register 403 latches data at the rising edge of the CK sample pulse.

In the process of sampling and reading the key value by using the CK sampling pulse control, the sampling time of the row state register 403 and the column state register 404 is exactly the time of performing state inversion on the column tri-state buffer 402 and the row tri-state buffer 401, and the row state register 403 or the column state register 404 under normal operation can be correctly sampled. If a certain timing margin is required, the CK sampling pulse connected to the column tri-state buffer 402 and the row tri-state buffer 401 can be delayed by passing the CK sampling pulse through an RC delay circuit and then connecting the CK sampling pulse to EN1 and EN2 of the row tri-state buffer 401 and the column tri-state buffer 402, wherein the delay time is determined by the RC delay circuit, and the delay time of the RC delay circuit is determined by the principle that the phase of the delayed CK sampling pulse does not exceed 90 °; or the CK sampling pulse is buffered by a plurality of gates and then connected to EN1 and EN2 of the row tri-state buffer 401 and the column tri-state buffer 402, and the delay time is the total delay time of the plurality of gates.

Under the control of the CP clock pulse, the buffer register 100 and the status code register 200 latch data at the active trigger edge of each period of the CP. In fig. 3, the rising edge trigger is active at 74HC273, and therefore the active trigger edge of the CP clock pulse is a rising edge.

4 data input terminals D20-D23 of the 8 data input terminals of the status code register 200 are directly connected to status signals I1, I2, I3, I4 output by the matrix keyboard, and the other 4 data input terminals D24-D27 are connected to data output terminals Q10-Q13 of the buffer register 100, and the 4 data input terminals D10-D13 of the buffer register 100 are directly connected to status signals I1, I2, I3, I4 output by the matrix keyboard, so that, among the 8 data output terminals of the status code register 200, the data latched by the 4 data output terminals Q20-Q23 corresponding to the status signals I1, I2, I3, I4 directly connected to the matrix keyboard output are the current status of the matrix keyboard, and their 4-bit data are called as current status key values; the data latched by the 4 data output terminals Q24-Q27 corresponding to the data output terminals connected to the buffer register 100 is the previous state of the matrix keyboard, and its 4 bits of data are called the previous state key values. The 4-bit present key value and the 4-bit previous key value output by the data output terminal of the status code register 200 together form an 8-bit status code.

The 8-bit state code is used for identifying the current state and the operation state of the matrix keyboard. For example, in the present embodiment, the status code of no key depression is 11111111; the state code of the single key press operation of the S1 key is 11111010; the state code of the pressed and maintained single key of the S1 key is 10101010; the status code of the S1 key single key release operation is 10101111; the status code of the single key press operation of the S2 key is 11110110; the state code of the single key press operation of the S4 key is 11110101; the S1 pressing operation of the S2+ S1 combination operation indicates an operation of pressing S1 after pressing S2, and the state code of this operation is 01100010 while maintaining the pressed state at S2.

The encoder 300 is used to convert the status code into a key number. In an embodiment, there are 6 valid keyboard operations and states, including:

operation 0: a single key press operation of the key S1, the key number being 0000;

operation 1: a single key of the key S2 is pressed, and the key number is 0001;

operation 2: a single key of the key S3 is pressed, with the key number 0010;

operation 3: the key S3 is in a maintenance state after the single key is pressed, and the key number is 0011;

and operation 4: after the single key of the key S4 is pressed, the combined key of the key S2 is pressed for operation, and the key number is 0100;

operation 5: the single key release operation of the key S1 has a key number 0101.

The state code and key number obtained according to the above specification are shown in code table 1:

TABLE 1 coding table

Keyboard operation	Status code (Address)	Key number (storage data)
			S1 Single Key Pushing	11111010	0000
S2 Single Key Pushing	11110110	0001
			S3 Single Key Pushing	11111001	0010
S3 Single Key Press Retention	10011001	0011
			Combined operation of S4+ S2	01010100	0100
S1 Single bond Release	10101111	0101
			Other operations or states	********	1111

The encoder 300 is a combinational logic circuit, and the circuit is designed to satisfy the logic relationship of table 1.

The encoder 300 of an embodiment is preferably comprised of a read only memory 301. The ROM 301 has 8-bit address, 2 in total ⁸4 bit binary memory cells. The 6 effective keyboard operations and states have 6 effective state codes corresponding to 6 effective key numbers; the state codes are written as the addresses a7 to a0 of the read only memory 301, and the corresponding key numbers are written as the storage data in the storage cells corresponding to the 6 valid state codes. The status codes generated by the 6 valid keyboard operations and states are invalid status codes, that is, the status codes generated by the other operations or states in table 1 are invalid status codes; in the other memory cells, an invalid key number, which is a value other than the 6 valid key numbers, is written all over, and in the embodiment, the invalid key number is 1111.

The read only memory 301 is always operated in the data output state. When the rom 301 has functions of chip select control and data output buffer control, the chip select control and the data output buffer control should be enabled.

The key number in the embodiment is a 4-bit binary code. The number of binary digits of the key number may be increased or decreased as required, and in this case, only the rom 301 matched with the number of binary digits is selected. Assuming that the number of binary digits of the key number is M, the value of M should be selected to satisfy 2^MGreater than or equal to the sum of the number of valid and invalid key numbers. When the matrix keyboard has N-bit keyboard status signal output, the rom 301 needs 2 × N bit address input and M-bit data output.

If the key operation function needs to be increased or decreased or the key operation function needs to be adjusted, the table 1 needs to be modified as needed, and the modified content is rewritten into the storage content of the rom 301.

In the embodiment, when the matrix keyboard S1 single key is pressed, the encoder 300 outputs the key number 0000 from the effective triggering edge of the CP clock pulse after the S1 single key is pressed to the effective triggering edge of the next CP clock pulse through the encoding output terminals C3 to C0; when the matrix keyboard S2 single key is pressed, the encoder 300 outputs the key number 0001 from the effective triggering edge of the CP clock pulse after the pressing of the single key S2 to the effective triggering edge of the next CP clock pulse; when the matrix keyboard is pressed S4 first and then S2, the encoder 300 outputs a key number 0100 starting from the effective trigger edge of the CP clock pulse after the combination key is pressed S2 until the effective trigger edge of the next CP clock pulse; when the matrix keyboard S1 single key is released, the encoder 300 outputs the key number 0101 from the effective triggering edge of the CP clock pulse after the S1 single key is released to the effective triggering edge of the next CP clock pulse; therefore, it can be seen that when the effective key operation of the matrix keyboard is identified, the encoder 300 outputs an effective key number with a duration of one CP clock period width from the effective triggering edge of the CP clock after the effective key operation to the effective triggering edge of the next CP clock.

In the embodiment, when the matrix keyboard S3 single key is pressed, the encoder 300 outputs the key number 0010 from the effective triggering edge of the CP clock pulse after the pressing of the single key S3 to the effective triggering edge of the next CP clock pulse; the encoder 300 outputs a key number 0011 from the start of the effective trigger edge of the next CP clock pulse to the end of the effective trigger edge of the next CP clock pulse after the holding state of pressing the single key at S3; it can thus be seen that when the sustained state of the matrix keyboard is identified, the duration of the encoder 300 outputting the valid key number is adapted to the duration of the sustained state.

When the state or operation of the keyboard is outside of the 6 valid keyboard operations and states described in table 1, the encoder 300 outputs an invalid key number 1111. Whether the valid key number is output or the invalid key number is output, the moment when the encoder 300 changes the output content is the valid trigger edge of the CP clock pulse; in an embodiment, the moment when the encoder 300 changes the output content is the rising edge of the CP clock pulse.

The period of the CP clock pulse is the scanning period of the matrix keyboard. When the scanning period of the keyboard is more than 20ms, the influence of keyboard key jitter can be effectively avoided; when the keyboard scanning period is below 100ms, keyboard operation is not missed; therefore, the period of the CP clock pulse should be controlled to be 20-100 ms.

The period requirement of the CK sampling pulse is not more than that of the CP clock pulse, so that when the state code is acquired at each effective trigger edge of the CP clock pulse, 4-bit key values output by the column state register 404 and the row state register 403 can be ensured to be always in the latest state of the matrix keyboard. A specific example of the CK sampling pulse is to directly use the CP clock pulse as the CK sampling pulse.

In the embodiment, the CP clock pulse and the CK sampling pulse are generated and output by the oscillator 500. The CP clock pulse and the CK sample pulse may also be provided by other circuits or devices.

FIG. 4 is a circuit diagram of a keyboard state change pulse generation circuit according to an embodiment of the present invention. When the effective key operation of the matrix keyboard is identified, the encoder 300 outputs an effective key number with a duration of one CP clock pulse period width from the effective trigger edge of the CP clock pulse after the effective key operation to the effective trigger edge of the next CP clock pulse. And the device for receiving the matrix type keyboard output needs to inquire the matrix type keyboard output all the time to acquire the key number. The period interval of the inquiry must be smaller than the period of the CP clock pulse.

The circuit shown in fig. 4 is used for judging whether the key number output by the matrix keyboard is changed or not, when the key number output by the matrix keyboard is changed, a keyboard state change pulse is output, and the receiving device for assisting the matrix keyboard receives the key number output by the matrix keyboard, for example, the keyboard state change pulse is used as an interrupt request signal of the receiving device.

The circuit shown in fig. 4 is composed of a delay buffer 601, an xor gate 602, an xor gate 603, an xor gate 604, an xor gate 605, and an or gate 606. The delay buffer 601 is composed of 4 edge flip-flops only having a trigger function, and the trigger input ends of the 4 edge flip-flops are the receiving pulse input ends of the delay buffer 601 and are all connected to the CP clock pulse output end of the oscillator 500; the delay buffer 601 performs data latching on the active triggering edge of the CP clock pulse.

The delay buffer 601 delays the 4-bit data C3 to C0 at the encoding output terminal of the encoder 300. 4 data input ends D63-D60 of the delay buffer 601 are connected to encoding output ends C3-C0 of the encoder 300, and data correspondingly output by 4 data output ends Q63-Q60 of the delay buffer 601 are C31-C01; after the signals of C31-C01 are buffered by the first stage of the delay buffer 601, the signals are delayed by one CP clock period compared with the signals of C3-C0, and FIG. 5 is a waveform diagram showing the effective operation of the keyboard according to the embodiment of the present invention. And setting the interval T1 of the CP clock pulse, the matrix keyboard has an effective operation, and the effective operation of the embodiment comprises the following steps: s1 single key press, S2 single key press, S3 single key press, S2 press of S4+ S2 combined operation, S1 single key release. At the next active trigger edge of an active operation, i.e. the rising edge after the interval of the CP clock pulse T1 in fig. 5, the codes C3-C0 output by the encoder 300 change; in the interval T2, the encoder 300 outputs effective codes C3-C0 of one period; during the intervals T3, T4, and thereafter, the codes C3-C0 output by the encoder 300 change again and enter a hold state, which may be, for example, the S1 single key pressing the following hold state, outputting an invalid key number, or the S3 single key pressing the following hold state, outputting a valid key number, until the next valid operation.

The D6 pulse in fig. 5 schematically shows whether the codes C3 to C0 outputted from the encoder 300 are in the hold state, unchanged, or changed, and the D6 pulse does not exist in the actual circuit. As shown in fig. 5, the D6 pulse is low, which schematically shows that the codes C3 to C0 outputted from the encoder 300 are in a hold state and do not change; the D6 pulse is high, which schematically indicates that the encoder 300 outputs one cycle of valid codes C3-C0. Q6 in FIG. 5 reflects the C31-C01 variation, and it is clear that Q6 is delayed by one CP clock period from D6. Also, the Q6 pulse is not present in an actual circuit.

In fig. 5, the codes C3 to C0 outputted from the encoder 300 are in a hold state, are unchanged, or are changed, and are actually completed by a logic circuit including a 4-bit delay buffer 601, an exclusive or gate 602, an exclusive or gate 603, an exclusive or gate 604, an exclusive or gate 605, and an or gate 606. The 4 exclusive or gates correspond to 1 bit of the encoding output terminals C3 to C0 of the encoder 300, and input signals of the 4-bit delay buffer 601 are input and output signals of the 4-bit delay buffer. For example, the two input signals of the xor gate 602 are C0 and C01, respectively, and C01 is delayed from C0 by one CP clock period, so that when C0 changes, the xor gate 602 outputs a positive pulse of 1 CP clock period width; when C0 is a CP clock cycle width change signal, xor-gate 602 outputs a positive pulse of 2 CP clock cycle widths. The xor gate 603, the xor gate 604, and the xor gate 605 respectively determine whether or not C1 to C3 have changed, and the principle is the same as that of determining whether or not C0 has changed. The output ends of the exclusive-or gate 602, the exclusive-or gate 603, the exclusive-or gate 604 and the exclusive-or gate 605 are respectively connected to the input end of the or gate 606, and the or gate 606 is used for comprehensively judging whether the C0-C3 change or not, so long as the C0-C3 change, the or gate 606 outputs a keyboard state change pulse F, and the pulse is a positive pulse.

In an embodiment, the delay buffer 601 selects the rising edge triggered 8D flip-flop 74HC 273. In an embodiment, the output of the encoder 300 is a 4-bit binary key number, and therefore, only 4D flip-flops are required for the delay buffer 601. Since the trigger inputs of the 4D flip-flops in the delay buffer 601 and the 4D flip-flops in the flip-flop 101 are both connected to the CP clock pulse output of the oscillator 500, the delay buffer 601 and the flip-flop 101 may share one 8D flip-flop 74HC 273.

Other schemes can be adopted for the delay buffer 601, for example, an RC circuit is adopted, and 4 RC circuits are used for respectively delaying C0-C3; if the delay time of the RC circuit is less than one CP clock pulse period, the encoder 300 outputs effective codes C3-C0 of one period, a keyboard state change pulse is generated at the beginning of outputting the effective codes C3-C0 and at the end of outputting the effective codes C3-C0, and the width of the keyboard state change pulse is equal to the delay time of the RC circuit; if the delay time of the RC circuit is more than or equal to one CP clock pulse period, the encoder 300 generates a keyboard state change pulse at the beginning of outputting the effective codes C3-C0 when outputting the effective codes C3-C0 of one period, and the pulse width is more than or equal to 2 CP clock pulse periods. The delay time of the RC circuit is required to not exceed 2 CP clock cycles to avoid false negatives.

In the circuit, the positioning of single key operation, combined key operation and keyboard maintenance state operation is converted into a state code with the same binary length by CP pulse scanning, and the state code is processed by adopting a uniform coding mode, wherein the single key operation, the combined key operation and the keyboard maintenance state operation are only reflected on the difference of the state code; if the key operation function needs to be increased or decreased or the key operation function needs to be adjusted, the structure of the keyboard scanning circuit does not need to be modified, and the encoder 300 only needs to be updated according to the increased or decreased state code table, that is, the storage content of the read-only memory 301 needs to be rewritten and updated. The circuit of the invention does not use microcontrollers such as a singlechip and an ARM, does not need running programs, and has reliable work.

Claims

1. A keyboard state change pulse generating circuit, comprising: is composed of an OR gate,MBit delay buffer andMthe exclusive-OR gate is formed;Mbit delay buffers for output from keyboard scanning positioning circuitMThe bit key numbers are respectively delayed;Mexclusive ORThe inputs to the gate are respectivelyMInput and output signals of the bit delay buffer;Mthe outputs of the exclusive-OR gates are respectively connected to the input ends of the OR gates; the output end of the OR gate outputs a keyboard state change pulse; the bits are binary bits;

the keyboard scanning positioning circuit comprises a matrix keyboard, a buffer register, a state code register and an encoder;

the matrix keyboard is commonXGo to,YRow of is provided withNA keyboard status signal output terminal; the above-mentionedNThe bit keyboard state signal is a level signal; the above-mentionedN＝X＋Y；

The buffer register and the status code register are bothNBit binary register, buffer registerNBit data input terminal is connected toNStatus signal output terminal of keyboard, 2 registers of status codeNIn bit data inputsNBit is connected toNA status signal output terminal of the keyboard, in additionNBit-coupled to buffer registerNA bit data output terminal;

the encoder has 2 piecesNBit-coded input, said 2 inN2 in which the bit-encoded input is connected to the status code registerNA bit data output terminal;

the receiving pulse input end of the buffer register and the receiving pulse input end of the state code register are both connected to a clock pulse; the matrix keyboard is controlled by sampling pulse to obtainNA keyboard status signal;

the matrix type keyboard consists ofXColumn-YThe device comprises a column key matrix, a row three-state buffer, a column three-state buffer, a row state register and a column state register;

the row lines of all the key matrixes are respectively connected to the output ends of the row tri-state buffers, and the column lines of all the key matrixes are respectively connected to the output ends of the column tri-state buffers; all input ends of the row tri-state buffer and the column tri-state buffer are connected to a low level; the row lines of all the key matrixes are respectively connected to the input end of the row state register, and the column lines of all the key matrixes are respectively connected to the input end of the column state register; the output end of the line state register and the column state registerAre formed by the output endsNAnd a keyboard status signal output terminal.

2. The keyboard state change pulse generating circuit of claim 1, wherein: the delay buffer is an edge trigger; the trigger input ends of the edge triggers are all connected to clock pulses.

3. The keyboard state change pulse generating circuit of claim 2, wherein: the rising edge of the clock pulse is an effective triggering edge; the delay buffer latches data at the effective triggering edge of the clock pulse; the above-mentionedMThe bit key number will only change on the active triggering edge of the clock pulse.

4. The keyboard state change pulse generating circuit of any of claims 1-3, wherein: when the low level of the sampling pulse is enabled to be effective, the row three-state buffer requires the column state register to carry out data latch on the rising edge of the sampling pulse, the column three-state buffer is enabled to be effective on the high level of the sampling pulse, and the row state register carries out data latch on the falling edge of the sampling pulse; alternatively, when the row tri-state buffer is enabled at the high level of the sampling pulse, the column state register is required to perform data latch at the falling edge of the sampling pulse, the column tri-state buffer is enabled at the low level of the sampling pulse, and the row state register performs data latch at the rising edge of the sampling pulse.

5. The keyboard state change pulse generating circuit of claim 4, wherein: the buffer register and the state code register simultaneously carry out data latching on the effective triggering edge of the clock pulse; the status code register 2NBit data output 2 inNA status code of the bit; the state code consists of a valid state code and an invalid state code; the key number output by the encoder consists of an effective key number and an ineffective key number; the effective state code is generated by effective keyboard operation or state, and the encoder corresponds to each effective state code when inputting the effective state codeOutputting the corresponding valid key number; the invalid state code is generated by invalid keyboard operation or state, and when the encoder inputs all the invalid state codes, the encoder correspondingly outputs invalid key numbers.

6. The keyboard state change pulse generating circuit of claim 5, wherein:Mthe value should be selected to satisfy 2^MGreater than or equal to the sum of the number of valid and invalid key numbers.