CN205320063U - Matrix type keyboard state recognition and coding circuit - Google Patents

Abstract

The utility model provides a matrix type keyboard state recognition and coding circuit comprises matrix type keyboard, a buffer register, the 2nd buffer register, encoder. The circuit scans via clock pulse, and the location of will operate the single bond, the state operation being maintain in key combination operation, keyboard converts active state sign indicating number and the invalid state sign indicating number of same binary system length to, invalid key that effective key of corresponding through the back output of encoder code and each active state sign indicating number number or export corresponds with all invalid state sign indicating numbers number, different single bond operation, key combination operation, keyboards is kept the state operation and is only embodied not the same at the status codes, the keyboard scanning circuit structure need not modifyd to if necessary increase/decrease keys operating function or adjustment button operating function, and it can only to need to change the encoder according to the corresponding relation between the status codes after the increase and decrease and the key number. The utility model circuit need not be compile and operating program, the reliable operation.

Description

A kind of matrix keyboard state recognition and coding circuit

Technical field

This utility model relates to the scanning circuit of a kind of keyboard, especially one matrix keyboard state recognition and coding circuit.

Background technology

Along with the development of embedded technology, the current commonly used microcontroller of each electronic product is as control core, and keyboard, as main input equipment, is widely used.

Current keyboard scan is mainly controlled by microcontroller, it is necessary to being undertaken by running the program in microcontroller, run into interference, cause program to run fast, scanning imaging system is by cisco unity malfunction.

Application number is the Scan orientation process that the mode that the patent of invention " fast scanning and positioning method of a kind of matrix keyboard " of CN201010153560.2 adopts keyboard interrupt to trigger enters keyboard, whether button is effective to adopt the method repeatedly repeating keyboard scan step to judge, and the key assignments obtained is carried out condition adjudgement; If multiple repairing weld state is identical, being then in steady statue, key assignments is effective; If multiple repairing weld state is different, key assignments is invalid. Single key stroke or Macintosh operation need individually to judge, single key stroke in this way then enters singly-bound tupe; Macintosh operation in this way, then enter Macintosh tupe. Method described in this patent solves the keyboard shake owing to the mechanical property of keyboard self causes and causes the wrong Problem-Error such as key, continuous touching, and the support issue to Macintosh and repeat key. But described method single key stroke needs to process respectively with Macintosh operation; Do not account for keyboard state and maintain a period of time keyboard operation function to rear just execution effectively operation; When increase and decrease button operation function or adjustment button operation function, it is necessary to amendment keyboard scan finder structure.

Summary of the invention

In order to solve the above-mentioned technical problem that existing keyboard scan localization method exists, this utility model provides a kind of matrix keyboard state recognition and coding circuit, is made up of matrix keyboard, the first buffer register, the second buffer register, encoder.

Described matrix keyboard has X row, Y row, is provided with N bit keyboard status signal output;Described N bit keyboard status signal is level signal; Described N=X+Y. Described matrix keyboard is provided with sampling pulse input.

Described first buffer register is N position binary register; The N bit data input of the first buffer register is connected to N bit keyboard status signal output.

Described second buffer register is N position binary register; The N bit data input of the second buffer register is connected to the N bit data outfan of the first buffer register.

Described encoder has 2 × N position coding input end; N bit data input in the coding input end of described 2 × N position is connected to the N bit data outfan of the first buffer register, and additionally N bit data input is connected to the N bit data outfan of the second buffer register; Described encoder has M position key outfan.

The reception pulse input end receiving pulse input end and the second buffer register of described first buffer register is connected to clock pulses.

Described matrix keyboard is enabled effective row three state buffer by X row-Y row key-press matrix, low level, high level enables effective row three state buffer, trailing edge latches effective row status register, rising edge latches effective column-shaped state depositor and forms; The line of all key-press matrixs is respectively connecting to the outfan of row three state buffer, and the alignment of all key-press matrixs is respectively connecting to the outfan of row three state buffer; All inputs of row three state buffer and row three state buffer are connected to low level; The line of all key-press matrixs is respectively connecting to the input of row status register, and the alignment of all key-press matrixs is respectively connecting to the input of row status register; The outfan of described row status register and the outfan of row status register collectively constitute keyboard state signal output part.

Described low level enables effective row three state buffer, the enable of the high level effective row three state buffer of enable controls input and is connected to sampling pulse; Described trailing edge latches effective row status register, the reception pulse input end of the rising edge effective column-shaped state depositor of latch is connected to sampling pulse.

Described first buffer register and the second buffer register carry out data latch at the rising edge of clock pulses simultaneously, or carry out data latch at the trailing edge of clock pulses simultaneously; The N bit data outfan of described first buffer register and the N bit data outfan of the second buffer register export the conditional code of 2 × N position jointly; Described conditional code is made up of effective status code and disarmed state code; The key number of described encoder output is made up of effective key number and invalid key number; Described effective status code is produced by effective keyboard operation or state, and encoder inputs the corresponding effectively key number of correspondence output during each effective status code; Described disarmed state code is produced by invalid keyboard operation or state, and encoder inputs all corresponding output invalid key number during all disarmed state codes.

Described encoder has M position key outfan, and the selection of M value should meet 2^MQuantity sum be more than or equal to effective key number with invalid key number.

The cycle of described clock pulses is 20～100ms; The cycle of described sampling pulse is not more than the cycle of described clock pulses, and its special case is described sampling pulse is described clock pulses.

Described a kind of matrix keyboard state recognition and coding circuit also include agitator; Described agitator output clock pulses and sampling pulse.

Described a kind of matrix keyboard state recognition and coding circuit also include keyboard state change pulse generation unit, whether the key number for the output of judgment matrix formula keyboard changes, when the key number of matrix keyboard output changes, export keyboard state change pulse.

Described keyboard state change pulse generation unit by M position delay buffer, M XOR gate and or door form;M position delay buffer is for carrying out signal delay respectively to the M position key number of matrix keyboard output; The input of the input of M XOR gate respectively M position delay buffer, output signal; The output of M XOR gate is respectively connecting to or the input of door; Or the outfan output keyboard state change pulse of door.

Described N position, 2 × N position, M position refer both to binary digit data.

The beneficial effects of the utility model are: single key stroke, Macintosh operation, keyboard will be maintained the location that state operates, the conditional code of same binary length is become by clock pulses scan conversion, adopt Unified coding mode process, single key stroke, Macintosh operation, keyboard maintain state operation be only embodied in conditional code not ibid; If needing increase and decrease button operation function or adjusting button operation function, keyboard scanning circuit structure need not be revised, only need to according to the corresponding relation change encoder between conditional code and the key number after increase and decrease, the storage content namely re-writing read only memory. Described utility model circuit does not use the microcontroller such as single-chip microcomputer, ARM, need not run program, reliable operation.

Accompanying drawing explanation

Fig. 1 is a kind of matrix keyboard state recognition and coding circuit theory diagram;

Fig. 2 is the matrix keyboard circuit diagram of this utility model embodiment;

Fig. 3 is the Scan orientation circuit diagram of this utility model embodiment;

Fig. 4 is the circuit diagram of the keyboard state change pulse generation unit of this utility model embodiment;

Fig. 5 is the waveform correlation schematic diagram that the keyboard of this utility model embodiment effectively operates.

Detailed description of the invention

Below in conjunction with accompanying drawing, the utility model is described in further detail.

Fig. 1 is a kind of matrix keyboard state recognition and coding circuit theory diagram, is made up of matrix keyboard the 400, first buffer register the 100, second buffer register 200, encoder 300, agitator 500.

Agitator 500 is multivibrator, is provided with CP output terminal of clock pulse and CK sampling pulse outfan, and the cycle of CP clock pulses is the cycle being not more than CP clock pulses in cycle of 20～100ms, CK sampling pulse.

Fig. 2 is the circuit diagram of the matrix keyboard 400 of this utility model embodiment, have 2 row, 2 row, totally 4 buttons, by button S1, button S2, button S3, button S4 be connected to the pull-up resistor R1 of power supply+VCC, pull-up resistor R2, pull-up resistor R3, pull-up resistor R4, and row three state buffer 401, row three state buffer 402, row status register 403, row status register 404 form. 2 outfans Y1, Y2 of row three state buffer 401 are respectively connecting to 2 lines, and 2 outfans Y3, Y4 of row three state buffer 402 are respectively connecting to 2 alignments; All input X1～X4 of row three state buffer 401 and row three state buffer 402 are connected to low level.

2 inputs D41, D42 of row status register 403 are respectively connecting to 2 lines, and 2 inputs D43, D44 of row status register 404 are respectively connecting to 2 alignments; 2 outfans Q41, Q42 of row status register 403 export row status signal I1, I2, and 2 outfans Q43, Q44 of row status register 404 export row status signal I3, I4; 2 outfans of row status register 403 and 2 outfans of row status register 404 collectively constitute 4 bit keyboard status signal output, export keyboard state signal I1, I2, I3, I4.

In embodiment, the enable input EN1 Low level effective of row three state buffer 401, the enable input EN2 high level of row three state buffer 402 is effective;EN1 and EN2 is connected to the CK sampling pulse outfan of agitator 500. Receive pulse input end CLK3, CLK4 of row status register 403 and row status register 404 are connected to the CK sampling pulse outfan of agitator 500, row status register 403 carries out data latch at the trailing edge of CK sampling pulse, and row status register 404 carries out data latch at the rising edge of CK sampling pulse.

When row three state buffer 401 and row three state buffer 402 use the three state buffer of same model, such as, when using three state buffer 74HC241 simultaneously, the enable input of 74HC241 is effective for high level, therefore, between the enable input EN1 of CK sampling pulse outfan and row three state buffer 401, it is necessary to increase a not gate. Similarly, when row status register 403 and row status register 404 use the data register of same model, such as, when row status register 403 and row status register 404 all use double D trigger 74HC74 to form data register, the triggering input of 74HC74 is effective for rising edge, therefore, between the reception pulse input end CLK3 of CK sampling pulse outfan and row status register 403, it is necessary to increase a not gate.

First buffer register the 100, second buffer register 200 in Fig. 1, encoder 300 form scanning encoding circuit, and embodiment circuit diagram is as shown in Figure 3. The keyboard state signal of matrix keyboard is 4 binary codes, and therefore, first buffer register the 100, second buffer register 200 all requires to deposit 4 bit binary data. 4 data input pin D10～D13 of the first buffer register 100 are connected to I1, I2, I3, I4; 4 data input pin D24～D27 of the second buffer register 200 are connected to 4 outfan Q10～Q13 of the first buffer register 100; In 8 input A0～A7 of encoder 300,44 outfan Q10～Q13 being connected to the first buffer register 100, other 44 outfan Q24～Q27 being connected to the second buffer register 200. Encoder 300 output is scanned through encoding 4 the binary system keys number determined.

In Fig. 3, trigger 101 forms the first buffer register 100, trigger 201 forms the second buffer register 200. Trigger 101 is made up of 4 edge triggered flip flops, and the trigger input CLK1 of 4 edge triggered flip flops is the reception pulse input end of the first buffer register 100, is connected to the CP output terminal of clock pulse of agitator 500; Trigger 201 is made up of 4 edge triggered flip flops, and the trigger input CLK2 of 4 edge triggered flip flops is the reception pulse input end of the second buffer register 200, is connected to the CP output terminal of clock pulse of agitator 500. Trigger 101, trigger 201 are preferably made up of the d type flip flop of edging trigger, for instance, it is made up of double D trigger 74HC74,4D trigger 74HC175,8D trigger 74HC273. In Fig. 3 embodiment, trigger 101, trigger 201 select the 8D trigger 74HC273 that rising edge triggers, and now, clear input unillustrated in Fig. 3 will be connected to high level, make the Protection Counter Functions of 74HC273 be in disarmed state, only have Trigger Function. Trigger 101 and trigger 201 all have only to 4D trigger, each arbitrarily use 4 d type flip flops in selected 8D trigger 74HC273. The trigger input of 8D trigger 74HC273 is connected to CP.

In Fig. 3, read only memory 301 forms encoder 300. The input that address input end A7～A0 is encoder 300 of read only memory 301, the coding outfan C3～C0 that data output end D3～D0 is encoder 300 of read only memory 301.

The operation principle of a kind of matrix keyboard state recognition and coding circuit is as follows:

In Fig. 2,4 buttons of matrix keyboard arrange with the matrix form of 2 × 2, and all of line and alignment are all connected to power supply+VCC by pull-up resistor. Matrix keyboard is controlled by CK sampling pulse, adopts reversal process to obtain keyboard state signal I4, I3, I2, I1. Such as, it does not have the keyboard state signal that the keyboard state signal that key is pressed is 1111, the S1 keyboard state signals pressed is 1010, S1, S2 presses simultaneously is 0010. 4 binary codes of keyboard state signal are called key assignments.

CK sampling pulse controls matrix keyboard is carried out the method for sampling reading key assignments: in the low level of CK sampling pulse, control all line output low levels by row three state buffer 401, and row three state buffer 402 exports the open alignment of high-impedance state; Sampled by row status register 404 at the rising edge of CK sampling pulse and read high 2 as key assignments of alignment state; At the high level of CK sampling pulse, controlling all alignment output low levels by row three state buffer 402, row three state buffer 401 exports the open line of high-impedance state; Sampled by row status register 403 at the trailing edge of CK sampling pulse and read low 2 as key assignments of line state; Said process goes round and begins again, and 4 key assignments of row status register 404, row status register 403 output are always the last state of matrix keyboard.

Control matrix keyboard is carried out, from CK sampling pulse, the method that key assignments is read in sampling, row three state buffer 401, when the low level of CK sampling pulse enables effective, requires that row status register 404 carries out data latch at the rising edge of CK sampling pulse, row three state buffer 402 enables effectively at the high level of CK sampling pulse, row status register 403 carries out data latch at the trailing edge of CK sampling pulse simultaneously. In turn, if row three state buffer 401 is when the high level of CK sampling pulse enables effective, require that row status register 404 carries out data latch at the trailing edge of CK sampling pulse, row three state buffer 402 enables effectively in the low level of CK sampling pulse, row status register 403 carries out data latch at the rising edge of CK sampling pulse simultaneously.

Control in the process that key assignments is read in sampling at above-mentioned CK sampling pulse, the moment that row status register 403, row status register 404 carry out sampling is precisely row three state buffer 402 and row three state buffer 401 and carries out the moment of state reversion, and row status register 403 or row status register 404 under normal operation can correctly be sampled. If requiring the allowance having in certain sequential, then can postpone being connected to the row three state buffer 402 CK sampling pulse with row three state buffer 401, method is to make CK sampling pulse be then connected to EN1, EN2 of row three state buffer 401 and row three state buffer 402 through RC delay circuit, time delay is determined by RC delay circuit, the principle determining the time delay of RC delay circuit is that the CK sample pulse phase of delay is less than 90 °; Or CK sampling pulse is then connected to EN1, EN2 of row three state buffer 401 and row three state buffer 402 after the buffering of several gate circuits, time delay now is the overall delay time of described several gate circuit.

First buffer register the 100, second buffer register 200 is under CP clock pulses controls, and the edge of effectively triggering in each cycle of CP carries out data latch. In Fig. 3,74HC273 is that rising edge triggers effectively, and therefore, the effectively triggering edge of CP clock pulses is rising edge.

4 output data of the first buffer register 100 are only through first-level buffer, and 4 output data of the second buffer register 200 have passed through level 2 buffering. Therefore, effectively trigger edge in CP clock pulses, the current state that data are matrix keyboard that 4 data output end Q10 of the first buffer register 100 correspondence～Q13 latches, its 4 bit data is called existing state key assignments; The previous state that data are matrix keyboard that 4 data output end Q24 of the second buffer register 200 correspondence～Q27 latches, its 4 bit data is called front state key assignments. 4 existing state key assignments and 4 front state key assignments collectively constitute 8 conditional codes.

8 described conditional codes are used for current state and the mode of operation of recognition matrix formula keyboard. Such as, in the present embodiment, the conditional code pressed without key is 11111111; The conditional code of S1 key singly-bound push is 11111010; The conditional code that S1 key singly-bound is pressed and maintained is 10101010; The conditional code of S1 key singly-bound release operation is 10101111; The conditional code of S2 key singly-bound push is 11110110; The conditional code of S4 key singly-bound push is 11110101; The S1 push of S2+S1 combination operation, represents after first pressing S2, maintains, at S2, the state pressed and presses the operation of S1 again, and the conditional code of this operation is 01100010.

Encoder 300 is for being converted to key number by conditional code. In embodiment, it is provided with 6 effective keyboard operations and state, including:

The singly-bound push of operation 0: button S1, key number is 0000;

The singly-bound push of operation 1: button S2, key number is 0001;

The singly-bound push of operation 2: button S3, key number is 0010;

Operation 3: button S3 singly-bound press after maintenance state, key number is 0011;

Operation 4: after button S4 singly-bound is pressed, then the Macintosh operation of the S2 that pushes button, key number is 0100;

The singly-bound release operation of operation 5: button S1, key number is 0101.

The conditional code obtained according to above-mentioned regulation and key number are shown in coding schedule 1:

Table 1 coding schedule

Keyboard operation	Conditional code (address)	Key number (storage data)
			S1 singly-bound is pressed	11111010	0000
S2 singly-bound is pressed	11110110	0001
			S3 singly-bound is pressed	11111001	0010
Maintenance pressed by S3 singly-bound	10011001	0011
			S4+S2 combination operation	01010100	0100
S1 singly-bound discharges	10101111	0101
			Other operation or states	********	1111

Encoder 300 is combinational logic circuit, designs circuit, meets the logical relation of table 1.

The encoder 300 of embodiment is preferably made up of read only memory 301. Read only memory 301 has 8 bit address, and totally 2⁸Individual 4 binary storage cells. 6 effective keyboard operations have 6 effective status codes, corresponding 6 effective keys number with state; Using conditional code address A7～A0 as read only memory 301, in the memory element corresponding with 6 effective status code-phase, using corresponding key number as storage data write. The conditional code produced outside 6 effective keyboard operations and state is disarmed state code, is namely disarmed state code produced by the operation of other in table 1 or state; In other memory element, all write invalid keys number, invalid key number is a value outside 6 effective keys number, and in embodiment, invalid key number is 1111.

Read only memory 301 always works at data output state. When read only memory 301 there is chip select control, data export dash-control function time, its chip select should be made to control, data output dash-control is in effective status.

Key number in embodiment is 4 binary codes. The number of bits of key number can increase as required, or reduces, and now, only need to select the read only memory 301 matched with this.If the selection that the number of bits of key number is M, M value should meet 2^MQuantity sum be more than or equal to effective key number with invalid key number. When matrix keyboard has N bit keyboard status signal to export, read only memory 301 needs the input of 2 × N bit address, and M-bit data exports.

If needing increase and decrease button operation function or adjusting button operation function, only need to revise table 1 as required, amended content is re-write the storage content of read only memory 301.

In embodiment, when matrix keyboard S1 singly-bound is pressed, the effective of the encoder 300 CP clock pulses after S1 singly-bound is pressed triggers along starting, and to the effectively triggering edge of next CP clock pulses, encodes outfan C3～C0 run-out key number 0000; When matrix keyboard S2 singly-bound is pressed, the effective of the encoder 300 CP clock pulses after S2 singly-bound is pressed triggers along starting, to the effectively triggering edge of next CP clock pulses, and run-out key number 0001; After matrix keyboard first presses S4, then pressing S2, the effective of the encoder 300 CP clock pulses after S2 Macintosh is pressed triggers along starting, to the effectively triggering edge of next CP clock pulses, and run-out key number 0100; When matrix keyboard S1 singly-bound discharges, the effective of the encoder 300 CP clock pulses after S1 singly-bound discharges triggers along starting, to the effectively triggering edge of next CP clock pulses, and run-out key number 0101; It can be seen that, when identify be effective button operation of matrix keyboard time, the edge of effectively triggering of the encoder 300 CP clock pulses after this effective button operation starts, to the effectively triggering edge of next CP clock pulses, output duration is effective key number of CP width clock cycle.

In embodiment, when matrix keyboard S3 singly-bound is pressed, the effective of the encoder 300 CP clock pulses after S3 singly-bound is pressed triggers along starting, to the effectively triggering edge of next CP clock pulses, and run-out key number 0010; Start on the edge of effectively triggering of ensuing CP clock pulses, press the effectively triggering edge of the next CP clock pulses after maintenance state terminates to S3 singly-bound, encoder 300 run-out key number 0011; It can therefore be seen that when identify be the maintenance state of matrix keyboard time, the persistent period of persistent period and this maintenance state that encoder 300 exports effective key number adapts.

When the state of keyboard or operation are for time outside 6 effective keyboard operations described in table 1 and state, encoder 300 exports invalid key number 1111. No matter export effective key number, or output invalid key number, encoder 300 change the moment of output content be CP clock pulses effectively trigger edge; In embodiment, encoder 300 changes the rising edge that the moment is CP clock pulses of output content.

The cycle of CP clock pulses is the scan period of matrix keyboard. The keyboard scan cycle is when more than 20ms, it is possible to be effectively shielded from the impact of keyboard shake; The keyboard scan cycle, when below 100ms, is unlikely to omit keyboard operation; Therefore, the cycle of CP clock pulses should control at 20～100ms.

The cycle request of CK sampling pulse is not more than the cycle of CP clock pulses, so, in each effective triggering of CP clock pulses along when obtaining conditional code, it is possible to ensure that 4 key assignments of row status register 404, row status register 403 output are always the last state of matrix keyboard. The special case of CK sampling pulse is directly to use CP clock pulses as CK sampling pulse.

In embodiment, CP clock pulses, CK sampling pulse produce by agitator 500 and export. CP clock pulses and CK sampling pulse can also be provided by the circuit outside a kind of matrix keyboard state recognition and coding circuit or device.

Fig. 4 is the circuit diagram of the keyboard state change pulse generation unit of this utility model embodiment. When identify be effective button operation of matrix keyboard time, the edge of effectively triggering of the encoder 300 CP clock pulses after this effective button operation starts, to the effectively triggering edge of next CP clock pulses, output duration is effective key number of CP width clock cycle. Receive the device of described matrix keyboard output, it is necessary to the output of moment inquiry matrix keyboard, obtain key number. The period distances of inquiry is necessarily less than the cycle of CP clock pulses.

Circuit shown in Fig. 4 is for whether the key number of judgment matrix formula keyboard output changes, when the key number of matrix keyboard output changes, output keyboard state change pulse, the key number receiving the output of device receiving matrix formula keyboard for auxiliary moment configuration keyboard, such as, using keyboard state change pulse as receive device interrupt request singal.

Circuit shown in Fig. 4 is made up of delay buffer 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or door 606. Delay buffer 601 is made up of 4 edge triggered flip flops only with Trigger Function, and the trigger input of 4 edge triggered flip flops is the reception pulse input end of delay buffer 601, is connected to the CP output terminal of clock pulse of agitator 500; Delay buffer 601 carries out data latch on the edge of effectively triggering of CP clock pulses.

Delay buffer 601 is for carrying out delay disposal respectively to the 4 bit data C3～C0 of the coding outfan of encoder 300. 4 data input pin D63～D60 of delay buffer 601 are connected to the coding outfan C3～C0 of encoder 300, and the data that 4 data output end Q63～Q60 of delay buffer 601 export accordingly are C31～C01; C31～C01 is after the first-level buffer of delay buffer 601, and its signal postpones a CP clock cycle than C3～C0, and Fig. 5 show the waveform correlation schematic diagram that the keyboard of this utility model embodiment effectively operates. The T1 being located at CP clock pulses is interval, and matrix keyboard existence once effectively operates, and the effectively operation of embodiment includes: S1 singly-bound is pressed, S2 singly-bound is pressed, S3 singly-bound is pressed, the S2 of S4+S2 combination operation presses, the release of S1 singly-bound. The next one in once effectively operation effectively triggers edge, i.e. rising edge after CP clock pulses T1 interval in Fig. 5, and the coding C3～C0 of encoder 300 output changes; Interval at T2, encoder 300 exports the efficient coding C3～C0 in a cycle; At T3, T4 and interval afterwards, coding C3～the C0 of encoder 300 output changes again and enters maintenance state, this maintenance state is probably such as S1 singly-bound and presses maintenance state below, output invalid key number, it is also likely to be S3 singly-bound and presses maintenance state below, export effective key number, until effectively operate next time.

D6 pulse in Fig. 5 schematically illustrates the coding C3～C0 of encoder 300 output and is in maintenance state, it does not have change, still changes, is absent from described D6 pulse in side circuit. As it is shown in figure 5, D6 pulse is low level, the coding C3～C0 schematically illustrating encoder 300 output is in maintenance state, it does not have change;D6 pulse is high level, schematically illustrates encoder 300 and exports the efficient coding C3～C0 in a cycle. Q6 reflection in Fig. 5 is the situation of change of C31～C01, it is clear that Q6 postpones a CP clock cycle than D6. Equally, side circuit is absent from described Q6 pulse.

In Fig. 5, coding C3～the C0 of encoder 300 output is in maintenance state, it is not changed in, still changes, be really the logic circuit being made up of 4 delay buffers 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or door 606 and complete. Encode in outfan C3～C0 with encoder 300 respectively 1 of 4 XOR gates is corresponding, the input of input respectively 4 delay buffers 601, output signal. Such as, two of XOR gate 602 input signal respectively C0 and C01, C01 postpone a CP clock cycle than C0, and therefore, when C0 changes, XOR gate 602 exports the positive pulse of 1 CP width clock cycle; When C0 is a CP change width clock cycle signal, XOR gate 602 exports the positive pulse of 2 CP width clock cycle. XOR gate 603, XOR gate 604, XOR gate 605 judge whether C1～C3 changes respectively, and principle is with to judge whether C0 changes identical. XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 outfan be respectively connecting to or the input of door 606, or whether door 606 changes for comprehensive descision C0～C3, as long as C0～C3 changes, or namely door 606 exports keyboard state change pulse F, this pulse is positive pulse.

In embodiment, delay buffer 601 selects the 8D trigger 74HC273 that rising edge triggers.

Delay buffer 601 can also adopt other schemes, for instance, adopt RC circuit, utilize 4 RC circuit respectively C0～C3 to be postponed; If the time delay of RC circuit is less than a CP clock cycle, when then encoder 300 exports the efficient coding C3～C0 in a cycle, starting and export efficient coding C3～C0 to terminate all to produce a keyboard state change pulse at output efficient coding C3～C0, the width of keyboard state change pulse is equal to RC circuit delay time; If the time delay of RC circuit is be more than or equal to a CP clock cycle, when then encoder 300 exports the efficient coding C3～C0 in a cycle, producing a keyboard state change pulse when exporting efficient coding C3～C0 and starting, pulse width is be more than or equal to 2 CP clock cycles. Require that the time delay of RC circuit is less than 2 CP clock cycles, in order to avoid producing to fail to report.

In described utility model circuit, single key stroke, Macintosh operation, keyboard will be maintained the location that state operates, the conditional code of same binary length is become by CP pulse scan conversion, adopt Unified coding mode process, single key stroke, Macintosh operation, keyboard maintain state operation be only embodied in conditional code not ibid; If needing increase and decrease button operation function or adjusting button operation function, it is not necessary to amendment keyboard scanning circuit structure, only need to update encoder 300 according to the state code table after increase and decrease, namely re-write the storage content updating read only memory 301. Described utility model circuit does not use the microcontroller such as single-chip microcomputer, ARM, need not run program, reliable operation.

Claims (6)

1. a matrix keyboard state recognition and coding circuit, it is characterised in that be made up of matrix keyboard, the first buffer register, the second buffer register, encoder;

Described matrix keyboard has X row, Y row, is provided with N bit keyboard status signal output; Described N=X+Y;

Described first buffer register is N position binary register; The N bit data input of the first buffer register is connected to N bit keyboard status signal output;

Described second buffer register is N position binary register; The N bit data input of the second buffer register is connected to the N bit data outfan of the first buffer register;

Described encoder has 2 × N position coding input end; N bit data input in the coding input end of described 2 × N position is connected to the N bit data outfan of the first buffer register, and additionally N bit data input is connected to the N bit data outfan of the second buffer register; Described encoder has M position key outfan;

The reception pulse input end receiving pulse input end and the second buffer register of described first buffer register is connected to clock pulses; Described matrix keyboard is provided with sampling pulse input.

2. a kind of matrix keyboard state recognition according to claim 1 and coding circuit, it is characterised in that: described matrix keyboard is enabled effective row three state buffer by X row-Y row key-press matrix, low level, high level enables effective row three state buffer, trailing edge latches effective row status register, rising edge latches effective column-shaped state depositor and forms; The line of all key-press matrixs is respectively connecting to the outfan of row three state buffer, and the alignment of all key-press matrixs is respectively connecting to the outfan of row three state buffer; All inputs of row three state buffer and row three state buffer are connected to low level; The line of all key-press matrixs is respectively connecting to the input of row status register, and the alignment of all key-press matrixs is respectively connecting to the input of row status register; The outfan of described row status register and the outfan of row status register collectively constitute keyboard state signal output part.

3. a kind of matrix keyboard state recognition according to claim 2 and coding circuit, it is characterised in that: described low level enables effective row three state buffer, the enable of the high level effective row three state buffer of enable controls input and is connected to sampling pulse; Described trailing edge latches effective row status register, the reception pulse input end of the rising edge effective column-shaped state depositor of latch is connected to sampling pulse.

4. a kind of matrix keyboard state recognition according to claim 1 and coding circuit, it is characterised in that: also include keyboard state change pulse generation unit.

5. a kind of matrix keyboard state recognition according to claim 4 and coding circuit, it is characterised in that: described keyboard state change pulse generation unit by M position delay buffer, M XOR gate and or door form; M position delay buffer is for carrying out signal delay respectively to the M position key number of matrix keyboard output; The input of the input of M XOR gate respectively M position delay buffer, output signal; The output of M XOR gate is respectively connecting to or the input of door; Or the outfan output keyboard state change pulse of door.

6. a kind of matrix keyboard state recognition according to claim 1 and coding circuit, it is characterised in that: also include agitator; Described agitator output clock pulses and sampling pulse.