CN105700696A - Matrix keyboard scanning and coding circuit - Google Patents
Matrix keyboard scanning and coding circuit Download PDFInfo
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- CN105700696A CN105700696A CN201610003429.5A CN201610003429A CN105700696A CN 105700696 A CN105700696 A CN 105700696A CN 201610003429 A CN201610003429 A CN 201610003429A CN 105700696 A CN105700696 A CN 105700696A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/02—Input arrangements using manually operated switches, e.g. using keyboards or dials
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M11/00—Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys
- H03M11/20—Dynamic coding, i.e. by key scanning
Abstract
The invention discloses a matrix keyboard scanning and coding circuit. The circuit comprises a matrix keyboard, a first shift register, a second shift register, a status code register and a coder; according to the circuit, through control of a scanning pulse and a shift pulse which satisfy a specific time sequence demand, the single-key operations, combined key operations or maintained statuses of the matrix keyboard are converted into valid status codes and invalid status codes with the same binary length; after the codes are coded by the coder, a valid key number corresponding to each valid status code is output or invalid key numbers corresponding to all invalid status codes are output; different single-key operations, combined key operations or maintained statuses are only reflected in the differences of the status codes; if key operation functions need to be reduced or increased, or if the key operation functions need to be adjusted, the structure of the keyboard scanning circuit does not need to be modified; and only the coder needs to be modified according to the corresponding relationships between the increased or reduced status codes and the key numbers. According to the circuits disclosed by the invention, it is unnecessary to compile and operate programs; and the work is reliable.
Description
Technical field
The present invention relates to the scanning circuit of a kind of keyboard, especially a kind of matrix keyboard scanning encoding circuit。
Background technology
Along with the development of embedded technology, the current commonly used microcontroller of each electronic product is as control core, and keyboard, as main input equipment, is widely used。
Current keyboard scan is mainly controlled by microcontroller, it is necessary to being undertaken by running the program in microcontroller, run into interference, cause program to run fast, scanning imaging system is by cisco unity malfunction。
Application number is the Scan orientation process that the mode that the patent of invention " fast scanning and positioning method of a kind of matrix keyboard " of CN201010153560.2 adopts keyboard interrupt to trigger enters keyboard, whether button is effective to adopt the method repeatedly repeating keyboard scan step to judge, and the key assignments obtained is carried out condition adjudgement；If multiple repairing weld state is identical, being then in steady statue, key assignments is effective；If multiple repairing weld state is different, key assignments is invalid。Single key stroke or Macintosh operation need individually to judge, single key stroke in this way then enters singly-bound tupe；Macintosh operation in this way, then enter Macintosh tupe。Method described in this patent solves the keyboard shake owing to the mechanical property of keyboard self causes and causes the wrong Problem-Error such as key, continuous touching, and the support issue to Macintosh and repeat key。But described method single key stroke needs to process respectively with Macintosh operation；Do not account for keyboard state and maintain a period of time keyboard operation function to rear just execution effectively operation；When increase and decrease button operation function or adjustment button operation function, it is necessary to amendment keyboard scan finder structure。
Summary of the invention
In order to solve the above-mentioned technical problem that existing keyboard scan localization method exists, the invention provides a kind of matrix keyboard scanning encoding circuit, be made up of matrix keyboard, the first shift register, the second shift register, conditional code depositor, encoder。
Described matrix keyboard scanning encoding circuit is carried out Synchronization Control by scanning impulse, shift pulse。
Described matrix keyboard has X row, Y row, is provided with N bit keyboard status signal output；Described N bit keyboard status signal is level signal；Described N=X+Y。
Described first shift register has the input of N parallel-by-bit, the output of N parallel-by-bit and Serial output function；Described second shift register has serial input, N parallel-by-bit output function。
The N parallel-by-bit input of described first shift register is connected to N bit keyboard status signal output；The serial input terminal of the second shift register is connected to the serial output terminal of the first shift register；First shift register, the second shift register shift pulse input be connected to shift pulse, the presetting pulse input of the first shift register is connected to scanning impulse。The presetting pulse of described first shift register carries out input and latch for the N parallel-by-bit of the first shift register is inputted data。
Described conditional code depositor is 2 × N position binary register；N bit data input in conditional code depositor is connected to the N parallel-by-bit outfan of the first shift register, and additionally N bit data input is connected to the N parallel-by-bit outfan of the second shift register；The reception pulse input end of described conditional code depositor is connected to scanning impulse。
Described encoder has 2 × N position coding input end, and described 2 × N position coding input end is connected to 2 × N bit data outfan of conditional code depositor。
Described scanning impulse, shift pulse sequential meet claimed below: in one cycle, scanning impulse has 1 pulse, and shift pulse has N number of pulse；Described scanning impulse, shift pulse go round and begin again according to the order of 1 scanning impulse, N number of shift pulse。
The cycle of described scanning impulse is 20～100ms。
Described first shift register, the second shift register shift pulse edge effective；When the presetting pulse of described first shift register is that edge is effective and scanning impulse is positive pulse, it is desirable to the presetting pulse of the first shift register is that rising edge is effective, and the reception pulse of conditional code depositor is that trailing edge is effective；When the presetting pulse of described first shift register is that edge is effective and scanning impulse is negative pulse, it is desirable to the presetting pulse of the first shift register is that trailing edge is effective, and the reception pulse of conditional code depositor is that rising edge is effective。Or, the presetting pulse of described first shift register be high level effective time, it is desirable to scanning impulse is positive pulse, and the reception pulse of conditional code depositor is that trailing edge is effective；When the presetting pulse of the first shift register is Low level effective, it is desirable to scanning impulse is negative pulse, the reception pulse of conditional code depositor is that rising edge is effective。
The conditional code of 2 × N bit data outfan output, 2 × N position of described conditional code depositor；Described conditional code is made up of effective status code and disarmed state code；The key number of described encoder output is made up of effective key number and invalid key number；Described effective status code is produced by effective keyboard operation or state, and encoder inputs the corresponding effectively key number of correspondence output during each effective status code；Described disarmed state code is produced by invalid keyboard operation or state, and encoder inputs all corresponding output invalid key number during all disarmed state codes。
Described encoder has M position key outfan, and the selection of M value should meet 2MQuantity sum be more than or equal to effective key number with invalid key number。
Described matrix keyboard scanning encoding circuit also includes keyboard state change pulse generation unit, and whether the key number for the output of judgment matrix formula keyboard changes, and when the key number of matrix keyboard output changes, exports keyboard state change pulse。
Described keyboard state change pulse generation unit by M position delay buffer, M XOR gate and or door form；M position delay buffer is for carrying out signal delay respectively to the M position key number of matrix keyboard output；The input of the input of M XOR gate respectively M position delay buffer, output signal；The output of M XOR gate is respectively connecting to or the input of door；Or the outfan output keyboard state change pulse of door。
Described matrix keyboard is made up of X row-Y row key-press matrix, row three state buffer, row three state buffer, row status register, column-shaped state depositor；The line of all key-press matrixs is respectively connecting to the outfan of row three state buffer, and the alignment of all key-press matrixs is respectively connecting to the outfan of row three state buffer；All inputs of row three state buffer and row three state buffer are connected to low level；The line of all key-press matrixs is respectively connecting to the input of row status register, and the alignment of all key-press matrixs is respectively connecting to the input of row status register；The outfan of described row status register and the outfan of row status register collectively constitute keyboard state signal output part。
Described matrix keyboard is controlled to obtain keyboard state signal by sampling pulse；Described sampling pulse selects in scanning impulse, shift pulse；Described row three state buffer is when the low level of sampling pulse enables effective, it is desirable to row status register carries out data latch at the rising edge of sampling pulse, row three state buffer enables effectively at the high level of sampling pulse, row status register carries out data latch at the trailing edge of sampling pulse；Or, row three state buffer is when the high level of sampling pulse enables effective, it is desirable to row status register carries out data latch at the trailing edge of sampling pulse, row three state buffer enables effectively in the low level of sampling pulse, row status register carries out data latch at the rising edge of sampling pulse。
Described N position, 2 × N position, M position refer both to binary digit data。
The invention has the beneficial effects as follows: single key stroke, Macintosh operation, keyboard will be maintained the Scan orientation that state operates, by meeting scanning impulse that specific time sequence requires, shift pulse controls to convert to the conditional code of same binary length, adopt Unified coding mode process, single key stroke, Macintosh operation, keyboard maintain state operation be only embodied in conditional code not ibid；If needing increase and decrease button operation function or adjusting button operation function, keyboard scanning circuit structure need not be revised, only need to according to the corresponding relation change encoder between conditional code and the key number after increase and decrease, the storage content namely re-writing read only memory。Described invention circuit does not use the microcontroller such as single-chip microcomputer, ARM, need not run program, reliable operation。
Accompanying drawing explanation
Fig. 1 is matrix keyboard scanning encoding schematic block circuit diagram；
Fig. 2 is the matrix keyboard circuit diagram of the embodiment of the present invention；
Fig. 3 is the scanning encoding circuit diagram of the embodiment of the present invention；
Fig. 4 is the first shift-register circuit figure of the embodiment of the present invention；
Fig. 5 is the pulse sequence figure of the embodiment of the present invention；
Fig. 6 is the impulse circuit schematic diagram of the embodiment of the present invention；
Fig. 7 is the circuit diagram of the keyboard state change pulse generation unit of the embodiment of the present invention；
Fig. 8 is the waveform correlation schematic diagram that the keyboard of the embodiment of the present invention effectively operates。
Detailed description of the invention
Below in conjunction with accompanying drawing, the invention will be further described。
Fig. 1 is matrix keyboard scanning encoding schematic block circuit diagram, is made up of matrix keyboard the 400, first shift register the 100, second shift register 200, conditional code depositor 500, encoder 300。
Fig. 2 is the circuit diagram of the matrix keyboard 400 of the embodiment of the present invention, have 2 row, 2 row, totally 4 buttons, by button S1, button S2, button S3, button S4 be connected to the pull-up resistor R1 of power supply+VCC, pull-up resistor R2, pull-up resistor R3, pull-up resistor R4, and row three state buffer 401, row three state buffer 402, row status register 403, row status register 404 form。2 outfans Y1, Y2 of row three state buffer 401 are respectively connecting to 2 lines, and 2 outfans Y3, Y4 of row three state buffer 402 are respectively connecting to 2 alignments；All input X1～X4 of row three state buffer 401 and row three state buffer 402 are connected to low level。
2 inputs D41, D42 of row status register 403 are respectively connecting to 2 lines, and 2 inputs D43, D44 of row status register 404 are respectively connecting to 2 alignments；2 outfans Q41, Q42 of row status register 403 export row status signal I1, I2, and 2 outfans Q43, Q44 of row status register 404 export row status signal I3, I4；2 outfans of row status register 403 and 2 outfans of row status register 404 collectively constitute 4 bit keyboard status signal output, export keyboard state signal I1, I2, I3, I4。
In embodiment, the enable input EN1 Low level effective of row three state buffer 401, the enable input EN2 high level of row three state buffer 402 is effective；EN1 and EN2 is connected to the sampling pulse CK outfan of agitator 500。Receive pulse input end CLK3, CLK4 of row status register 403 and row status register 404 are connected to the sampling pulse CK outfan of agitator 500, row status register 403 carries out data latch at the trailing edge of sampling pulse CK, and row status register 404 carries out data latch at the rising edge of sampling pulse CK。
When row three state buffer 401 and row three state buffer 402 use the three state buffer of same model, such as, when using three state buffer 74HC241 simultaneously, the enable input of 74HC241 is effective for high level, therefore, between the enable input EN1 of sampling pulse CK outfan and row three state buffer 401, it is necessary to increase a not gate。Similarly, when row status register 403 and row status register 404 use the data register of same model, such as, when row status register 403 and row status register 404 all use double D trigger 74HC74 to form data register, the triggering input of 74HC74 is effective for rising edge, therefore, between the reception pulse input end CLK3 of sampling pulse CK outfan and row status register 403, it is necessary to increase a not gate。
First shift register the 100, second shift register 200 in Fig. 1, conditional code depositor 500, encoder 300 form scanning encoding circuit, and embodiment circuit diagram is as shown in Figure 3。The status signal of embodiment matrix keyboard circuit output has 4, therefore, first shift register the 100, second shift register 200 is all 4 binary shift registers, wherein, first shift register 100 has parallel input, parallel output and Serial output function, and the second shift register 200 has serial input, parallel output function；4 parallel input terminal L0～L3 of the first shift register 100 are sequentially connected to I1, I2, I3, I4, and the serial input terminal D2 of the second shift register 200 is connected to the serial output terminal Q13 of the first shift register 100。Shift pulse input CLK1, CLK2 of first shift register the 100, second shift register 200 are connected to shift pulse CP2, and the presetting pulse input CLK0 of the first shift register 100 is connected to scanning impulse CP1。
Conditional code depositor 500 requires to deposit 8 bit binary data, 4 parallel output terminal Q13～Q10 being connected to the first shift register 100 in its 8 bit data input D57～D50, other 4 parallel output terminal Q23～Q20 being connected to the second shift register 200；In embodiment, D57～D54 is connected to Q23～Q20, D53～D50 and is connected to Q13～Q10。The reception pulse input end CLK5 of conditional code depositor 500 is connected to scanning impulse CP1。
8 input A7～A0 of encoder 300 are connected to 8 data output end Q57～Q50 of conditional code depositor 500。Encoder 300 output is scanned through encoding 4 the binary system keys number determined。
In Fig. 3 embodiment, the second shift register 200 can select to be made up of various medium-scale integration shift registers, or is made up of edge triggered flip flop；When being formed the second shift register 200 by edge triggered flip flop, it is preferable that be made up of the d type flip flop of edging trigger。Conditional code depositor 500 is made up of edge triggered flip flop, it is preferable that be made up of the d type flip flop of edging trigger, for instance, select double D trigger CD4013 or 4D trigger 74HC175 or 8D trigger 74HC273 composition。
Fig. 4 is the circuit diagram of the first shift register 100 of the embodiment of the present invention, is made up of 4 set, the equal high level of reset function 101～104,8 nor gates 105～112 of effective d type flip flop。In embodiment, d type flip flop 101～104 selects double D trigger CD4013, and it is effective that it triggers rising edge of a pulse。Scanning impulse CP1 controls the set of d type flip flop 101～104, reset function by 8 nor gates 105～112。For d type flip flop 101, when scanning impulse CP1 is high level, nor gate 105, nor gate 106 output low level, the set of d type flip flop 101, reset function are invalid；When scanning impulse CP1 is low level and L0=0, nor gate 105 is output asNor gate 106 is output as L0, and namely the set function of d type flip flop 101 is invalid, reset function effective, makes Q10=0；When scanning impulse CP1 is low level and L0=1, nor gate 105 is output asNor gate 106 is output as L0, and namely the set function of d type flip flop 101 is effective, reset function is invalid, makes Q10=1。The operation principle of d type flip flop 102～104 is the same with d type flip flop 101, when scanning impulse CP1 is low level, and Q10=L0, Q11=L1, Q12=L2, Q13=L3；When scanning impulse CP1 is high level, owing to triggering pulse input end CLK10, CLK11, CLK12, CLK13 of d type flip flop 101～104 are connected to CP2, therefore, rising edge at each shift pulse CP2, first shift register 100 moves once position, i.e. Q13=Q12, Q12=Q11, Q11=Q10, Q10=0。
In Fig. 3 embodiment, encoder 300 is read only memory。The input that address input end A7～A0 is encoder 300 of read only memory, the coding outfan C3～C0 that data output end D3～D0 is encoder 300 of read only memory。
The operation principle of matrix keyboard scanning encoding circuit is as follows:
Scanning encoding circuit scanning impulse CP1, shift pulse CP2 control under work, relevant pulse sequence figure is as shown in Figure 5。
In embodiment, the sequential of CP1, CP2 meets claimed below: in one cycle, and CP1 has 1 pulse, and CP2 has 4 pulses；Each pulse goes round and begins again according to the order of 1 CP1 pulse, 4 CP2 pulses。
CP1, CP2 pulse meeting timing requirements can be produced by various pulsqe distributors, and Fig. 6 is the impulse circuit schematic diagram of the embodiment of the present invention, is made up of agitator 801, enumerator 802, pulsqe distributor 803。Clock pulse CP in Fig. 5 is produced by agitator, and CP delivers to enumerator 802 and counts, and enumerator 802 is 10 system Counters, and 10 states (numerical value) of its result P are followed successively by P0 → P9, as shown in Figure 5。Pulsqe distributor 803 in embodiment adopts ROM memory to realize, hereon referred to as pulse distribution ROM memory。The address input of pulse distribution ROM memory is connected to the counting output of enumerator 802, and 2 bit data outfans of pulse distribution ROM memory are output as CP1 pulse, CP2 pulse respectively。The write content of pulse distribution ROM memory is in Table 1。
Table 1 pulse distribution ROM memory tables of data
ROM memory address in table 1, namely enumerator output is at least 4 binary codes。Generally, if enumerator 802 adopts binary addition rule, then corresponding 4 binary codes 0000～1001 of P0～P9 order, namely ROM memory address realm is 0000～1001, and the storage content of address 0000～1001 is content corresponding for P0～P9 in table 1。
Pulse distribution ROM memory needs 2 bit data outputs。If the address input of pulse distribution ROM memory has R position, when matrix keyboard has N bit keyboard status signal to export, the selection of R needs to meet 2RBe more than or equal to 2 × (N+1)。
Agitator 801 is multivibrator。The cycle of scanning impulse CP1 is 20～100ms。CP1, CP2 can also be provided by the circuit outside matrix keyboard scanning encoding circuit or device。
In Fig. 2,4 buttons of matrix keyboard arrange with the matrix form of 2 × 2, and all of line and alignment are all connected to power supply+VCC by pull-up resistor。Matrix keyboard is controlled by sampling pulse CK, adopts reversal process to obtain keyboard state signal I4, I3, I2, I1。Such as, it does not have the keyboard state signal that the keyboard state signal that key is pressed is 1111, the S1 keyboard state signals pressed is 1010, S1, S2 presses simultaneously is 0010。4 binary codes of keyboard state signal are called key assignments。Sampling pulse CK can select in scanning impulse CP1, shift pulse CP2, it is preferable that by shift pulse CP2 simultaneously as sampling pulse CK。
Sampling pulse CK controls matrix keyboard is carried out the method for sampling reading key assignments: in the low level of sampling pulse CK, control all line output low levels by row three state buffer 401, and row three state buffer 402 exports the open alignment of high-impedance state；Sampled by row status register 404 at the rising edge of sampling pulse CK and read high 2 as key assignments of alignment state；At the high level of sampling pulse CK, controlling all alignment output low levels by row three state buffer 402, row three state buffer 401 exports the open line of high-impedance state；Sampled by row status register 403 at the trailing edge of sampling pulse CK and read low 2 as key assignments of line state；Said process goes round and begins again, and 4 key assignments of row status register 404, row status register 403 output are always the last state of matrix keyboard。
Control matrix keyboard is carried out, from sampling pulse CK, the method that key assignments is read in sampling, row three state buffer 401, when the low level of sampling pulse CK enables effective, requires that row status register 404 carries out data latch at the rising edge of sampling pulse CK, row three state buffer 402 enables effectively at the high level of sampling pulse CK, row status register 403 carries out data latch at the trailing edge of sampling pulse CK simultaneously。In turn, if row three state buffer 401 is when the high level of sampling pulse CK enables effective, require that row status register 404 carries out data latch at the trailing edge of sampling pulse CK, row three state buffer 402 enables effectively in the low level of sampling pulse CK, row status register 403 carries out data latch at the rising edge of sampling pulse CK simultaneously。
Control in the process that key assignments is read in sampling at above-mentioned sampling pulse CK, the moment that row status register 403, row status register 404 carry out sampling is precisely row three state buffer 402 and row three state buffer 401 and carries out the moment of state reversion, and row status register 403 or row status register 404 under normal operation can correctly be sampled。If requiring the allowance having in certain sequential, then can postpone being connected to the row three state buffer 402 sampling pulse CK with row three state buffer 401, method is to make sampling pulse CK be then connected to EN1, EN2 of row three state buffer 401 and row three state buffer 402 through RC delay circuit, time delay is determined by RC delay circuit, the principle determining the time delay of RC delay circuit is that the sampling pulse CK phase place of delay is less than 90 °；Or sampling pulse CK is then connected to EN1, EN2 of row three state buffer 401 and row three state buffer 402 after the buffering of several gate circuits, time delay now is the overall delay time of described several gate circuit。
Status signal I1, I2, I3, I4 of matrix keyboard 400 output, under the control of scanning impulse CP1, is carried out data latch by the first shift register 100, and the now output of the first shift register 100 is called existing state key assignments；The control via 4 CP2 pulses in a upper cycle of second shift register 200, the output that a upper periodic scanning pulses CP1 is latching to the first shift register 100 is displaced to the second shift register 200 outfan, therefore, now the output of the second shift register 200 is called front state key assignments。
The front state key assignments that existing state key assignments that first shift register 100 is exported by scanning impulse CP1, the second shift register 200 export is latched in the outfan of conditional code depositor 500, and the output of conditional code depositor 500 is similarly front state key assignments and existing state key assignments。
The equal edge of shift pulse of first shift register the 100, second shift register 200 is effective, and therefore, CP2 can be positive pulse, it is also possible to be negative pulse。
When the presetting pulse of the first shift register 100 is that edge is effective and scanning impulse CP1 is positive pulse, it is desirable to the presetting pulse of the first shift register 100 is that rising edge is effective, and the reception pulse of conditional code depositor 500 is that trailing edge is effective；When the presetting pulse of the first shift register 100 is that edge is effective and scanning impulse CP1 is negative pulse, it is desirable to the presetting pulse of the first shift register 100 is that trailing edge is effective, and the reception pulse of conditional code depositor 500 is that rising edge is effective。The presetting pulse of the first shift register 100 be high level effective time, it is desirable to scanning impulse CP1 is positive pulse, and the reception pulse of conditional code depositor 500 is that trailing edge is effective；When the presetting pulse of the first shift register 100 is Low level effective, it is desirable to scanning impulse CP1 is negative pulse, the reception pulse of conditional code depositor 500 is that rising edge is effective。In embodiment, the presetting pulse of the first shift register 100 is Low level effective, so scanning impulse CP1 is negative pulse, the reception pulse of conditional code depositor 500 is that rising edge is effective。
In embodiment, 4 existing state key assignments and 4 front state key assignments of the output of conditional code depositor 500 data output end collectively constitute 8 conditional codes。8 described conditional codes are used for current state and the mode of operation of recognition matrix formula keyboard。Such as, in the present embodiment, the conditional code pressed without key is 11111111；The conditional code of S1 key singly-bound push is 11111010；The conditional code that S1 key singly-bound is pressed and maintained is 10101010；The conditional code of S1 key singly-bound release operation is 10101111；The conditional code of S2 key singly-bound push is 11110110；The conditional code of S4 key singly-bound push is 11110101；The S1 push of S2+S1 combination operation, represents after first pressing S2, maintains, at S2, the state pressed and presses the operation of S1 again, and the conditional code of this operation is 01100010。
Encoder 300 is for being converted to key number by conditional code。In embodiment, it is provided with 6 effective keyboard operations and state, including:
The singly-bound push of operation 0: button S1, key number is 0000；
The singly-bound push of operation 1: button S2, key number is 0001；
The singly-bound push of operation 2: button S3, key number is 0010；
Operation 3: button S3 singly-bound press after maintenance state, key number is 0011；
Operation 4: after button S4 singly-bound is pressed, then the Macintosh operation of the S2 that pushes button, key number is 0100；
The singly-bound release operation of operation 5: button S1, key number is 0101。
The conditional code obtained according to above-mentioned regulation and key number are shown in coding schedule 2:
Table 2 coding schedule
| Keyboard operation | Conditional code (address) | Key number (storage data) |
| S1 singly-bound is pressed | 11111010 | 0000 |
| S2 singly-bound is pressed | 11110110 | 0001 |
| S3 singly-bound is pressed | 11111001 | 0010 |
| Maintenance pressed by S3 singly-bound | 10011001 | 0011 |
| S4+S2 combination operation | 01010100 | 0100 |
| S1 singly-bound discharges | 10101111 | 0101 |
| Other operation or states | ******** | 1111 |
Encoder 300 is combinational logic circuit, designs circuit, meets the logical relation of table 2。
The encoder 300 of embodiment is preferably made up of read only memory 301。Read only memory 301 has 8 bit address, and totally 28Individual 4 binary storage cells。6 effective keyboard operations have 6 effective status codes, corresponding 6 effective keys number with state；Using conditional code address A7～A0 as read only memory 301, in the memory element corresponding with 6 effective status code-phase, using corresponding key number as storage data write。The conditional code produced outside 6 effective keyboard operations and state is disarmed state code, is namely disarmed state code produced by the operation of other in table 2 or state；In other memory element, all write invalid keys number, invalid key number is a value outside 6 effective keys number, and in embodiment, invalid key number is 1111。
Read only memory 301 always works at data output state。When read only memory 301 there is chip select control, data export dash-control function time, its chip select should be made to control, data output dash-control is in effective status。
Key number in embodiment is 4 binary codes。The number of bits of key number can increase as required, or reduces, and now, only need to select the read only memory 301 matched with this。If the selection that the number of bits of key number is M, M value should meet 2MQuantity sum be more than or equal to effective key number with invalid key number。When matrix keyboard has N bit keyboard status signal to export, read only memory 301 needs the input of 2 × N bit address, and M-bit data exports。
If needing increase and decrease button operation function or adjusting button operation function, only need to revise table 2 as required, amended content is re-write the storage content of read only memory 301。
The edge of the scanning impulse CP1 that conditional code depositor 500 carries out the moment of data latch is called state latch edge, is the rising edge of CP1 in embodiment。In embodiment, when matrix keyboard S1 singly-bound is pressed, preset through CP1, latch after, from the state latch of CP1 along, to the state latch edge of next CP1, coding outfan C3～C0 run-out key number 0000；When matrix keyboard S2 singly-bound is pressed, preset through CP1, latch after, from the state latch of CP1 along, to the state latch edge of next one CP1, run-out key number 0001；After matrix keyboard first presses S4, then pressing S2, encoder 300 is pressed at S2 Macintosh, preset through CP1, latch after, from the state latch of CP1 along, to the state latch edge of next one CP1, run-out key number 0100；When matrix keyboard S1 singly-bound discharges, preset through CP1, latch after, from the state latch of CP1 along, to the state latch edge of next one CP1, run-out key number 0101；It can be seen that, when identify be effective button operation of matrix keyboard time, the state latch of the encoder 300 CP1 after this effective button operation is along starting, and to the state latch edge of next CP1, output duration is effective key number of a CP1 periodic width。
In embodiment, when matrix keyboard S3 singly-bound is pressed, encoder 300 is pressed at S3 singly-bound, preset through CP1, latch after, from the state latch of CP1 along, to the state latch edge of next one CP1, run-out key number 0010；At the state latch of ensuing CP1 along starting, press maintenance state to S3 singly-bound and terminate, preset through CP1, latch after, from the state latch of CP1 along, to the state latch edge of next one CP1, encoder 300 run-out key number 0011；It can therefore be seen that when identify be the maintenance state of matrix keyboard time, the persistent period of persistent period and this maintenance state that encoder 300 exports effective key number adapts。
When the state of keyboard or operation are for time outside 6 effective keyboard operations described in table 2 and state, encoder 300 exports invalid key number 1111。No matter it is export effective key number, or output invalid key number, encoder 300 changes the state latch edge that the moment is CP1 of output content；In embodiment, encoder 300 changes the rising edge that the moment is CP1 of output content。
The cycle of CP1 is the scan period of matrix keyboard。The keyboard scan cycle is when more than 20ms, it is possible to be effectively shielded from the impact of keyboard shake；The keyboard scan cycle, when below 100ms, is unlikely to omit keyboard operation；Therefore, the cycle of CP1 should control at 20～100ms。
Fig. 7 is the circuit diagram of the keyboard state change pulse generation unit of the embodiment of the present invention。When identify be effective button operation of matrix keyboard time, the state latch of the encoder 300 CP1 after this effective button operation is along starting, and to the state latch edge of next one CP1, output duration is effective key number of a CP1 periodic width。Receive the device of described matrix keyboard output, it is necessary to the output of moment inquiry matrix keyboard, obtain key number。The period distances of inquiry is necessarily less than the cycle of CP1。
Circuit shown in Fig. 7 is for whether the key number of judgment matrix formula keyboard output changes, when the key number of matrix keyboard output changes, output keyboard state change pulse, the key number receiving the output of device receiving matrix formula keyboard for auxiliary moment configuration keyboard, such as, using keyboard state change pulse as receive device interrupt request singal。
Circuit shown in Fig. 7 is made up of delay buffer 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or door 606。Delay buffer 601 is made up of 4 edge triggered flip flops only with Trigger Function, and the trigger input of 4 edge triggered flip flops is the reception pulse input end of delay buffer 601, is connected to CP1；Delay buffer 601 carries out data latch on the state latch edge of CP1。
Delay buffer 601 is for carrying out delay disposal respectively to the 4 bit data C3～C0 of the coding outfan of encoder 300。4 data input pin D63～D60 of delay buffer 601 are connected to the coding outfan C3～C0 of encoder 300, and the data that 4 data output end Q63～Q60 of delay buffer 601 export accordingly are C31～C01；C31～C01 is after the first-level buffer of delay buffer 601, and its signal postpones a CP1 pulse period than C3～C0, and Fig. 8 show the waveform correlation schematic diagram that the keyboard of the embodiment of the present invention effectively operates。The T1 being located at CP1 pulse is interval, matrix keyboard existence once effectively operates, and the effectively operation of embodiment includes: S1 singly-bound is pressed, S2 singly-bound is pressed, S3 singly-bound is pressed, the S1 of S4+S1 combination operation presses, the S2 of S4+S2 combination operation presses, the release of S1 singly-bound。On the next state latch edge of once effectively operation, i.e. rising edge after CP1 pulse T1 interval in Fig. 8, the coding C3～C0 of encoder 300 output changes；Interval at T2, encoder 300 exports the efficient coding C3～C0 of a CP1 pulse period；At T3, T4 and interval afterwards, coding C3～the C0 of encoder 300 output changes again and enters maintenance state, this maintenance state is probably such as S1 singly-bound and presses maintenance state below, output invalid key number, it is also likely to be S3 singly-bound and presses maintenance state below, export effective key number, until effectively operate next time。
D6 pulse in Fig. 8 schematically illustrates the coding C3～C0 of encoder 300 output and is in maintenance state, it does not have change, still changes, is absent from described D6 pulse in side circuit。As shown in Figure 8, D6 pulse is low level, and the coding C3～C0 schematically illustrating encoder 300 output is in maintenance state, it does not have change；D6 pulse is high level, schematically illustrates encoder 300 and exports the efficient coding C3～C0 in a cycle。What the Q6 in Fig. 8 reflected is the situation of change of C31～C01, it is clear that Q6 postpones a CP1 pulse period than D6。Equally, side circuit is absent from described Q6 pulse。
In Fig. 8, coding C3～the C0 of encoder 300 output is in maintenance state, it is not changed in, still changes, be really the logic circuit being made up of 4 delay buffers 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or door 606 and complete。Encode in outfan C3～C0 with encoder 300 respectively 1 of 4 XOR gates is corresponding, the input of input respectively 4 delay buffers 601, output signal。Such as, two inputs signal respectively C0 and C01, C01 of XOR gate 602 postpone a CP1 pulse period than C0, and therefore, when C0 changes, XOR gate 602 exports the positive pulse of 1 CP1 pulse period width；When C0 is a CP1 pulse period change width signal, XOR gate 602 exports the positive pulse of 2 CP1 pulse period width。XOR gate 603, XOR gate 604, XOR gate 605 judge whether C1～C3 changes respectively, and principle is with to judge whether C0 changes identical。XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 outfan be respectively connecting to or the input of door 606, or whether door 606 changes for comprehensive descision C0～C3, as long as C0～C3 changes, or namely door 606 exports keyboard state change pulse F, and this pulse is positive pulse。
In embodiment, delay buffer 601 selects the 8D trigger 74HC273 that rising edge triggers。
Delay buffer 601 can also adopt other schemes, for instance, adopt RC circuit, utilize 4 RC circuit respectively C0～C3 to be postponed；If the time delay of RC circuit is less than a CP1 pulse period, when then encoder 300 exports the efficient coding C3～C0 in a cycle, starting and export efficient coding C3～C0 to terminate all to produce a keyboard state change pulse at output efficient coding C3～C0, the width of keyboard state change pulse is equal to RC circuit delay time；If the time delay of RC circuit is be more than or equal to a CP1 pulse period, when then encoder 300 exports the efficient coding C3～C0 in a cycle, producing a keyboard state change pulse when exporting efficient coding C3～C0 and starting, this pulse width is be more than or equal to 2 CP1 pulse periods。Require that the time delay of RC circuit is less than 2 CP1 pulse periods, in order to avoid producing to fail to report。
In described invention circuit, single key stroke, Macintosh operation, keyboard will be maintained the location that state operates, the conditional code of same binary length is converted to by 2 Pulse Width Control meeting specific time sequence requirement, adopt Unified coding mode process, single key stroke, Macintosh operation, keyboard maintain state operation be only embodied in conditional code not ibid；If needing increase and decrease button operation function or adjusting button operation function, it is not necessary to amendment keyboard scanning circuit structure, only need to update encoder 300 according to the state code table after increase and decrease, namely re-write the storage content updating read only memory。Described invention circuit does not use the microcontroller such as single-chip microcomputer, ARM, need not run program, reliable operation。
Claims (10)
1. a matrix keyboard scanning encoding circuit, it is characterised in that be made up of matrix keyboard, the first shift register, the second shift register, conditional code depositor, encoder；
Described matrix keyboard scanning encoding circuit is carried out Synchronization Control by scanning impulse, shift pulse；
Described matrix keyboard has X row, Y row, is provided with N bit keyboard status signal output；Described N bit keyboard status signal is level signal；Described N=X+Y；
Described first shift register has the input of N parallel-by-bit, the output of N parallel-by-bit and Serial output function；Described second shift register has serial input, N parallel-by-bit output function；
The N parallel-by-bit input of described first shift register is connected to N bit keyboard status signal output；The serial input terminal of the second shift register is connected to the serial output terminal of the first shift register；First shift register, the second shift register shift pulse input be connected to shift pulse, the presetting pulse input of the first shift register is connected to scanning impulse；
Described conditional code depositor is 2 × N position binary register；N bit data input in conditional code depositor is connected to the N parallel-by-bit outfan of the first shift register, and additionally N bit data input is connected to the N parallel-by-bit outfan of the second shift register；The reception pulse input end of described conditional code depositor is connected to scanning impulse；
Described encoder has 2 × N position coding input end, and described 2 × N position coding input end is connected to 2 × N bit data outfan of conditional code depositor；
Described scanning impulse, shift pulse sequential meet claimed below: in one cycle, scanning impulse has 1 pulse, and shift pulse has N number of pulse；Described scanning impulse, shift pulse go round and begin again according to the order of 1 scanning impulse, N number of shift pulse。
2. matrix keyboard scanning encoding circuit according to claim 1, it is characterised in that: the cycle of described scanning impulse is 20～100ms。
3. matrix keyboard scanning encoding circuit according to claim 1, it is characterised in that: described first shift register, the second shift register shift pulse edge effective；When the presetting pulse of described first shift register is that edge is effective and scanning impulse is positive pulse, it is desirable to the presetting pulse of the first shift register is that rising edge is effective, and the reception pulse of conditional code depositor is that trailing edge is effective；Or, when the presetting pulse of described first shift register is that edge is effective and scanning impulse is negative pulse, it is desirable to the presetting pulse of the first shift register is that trailing edge is effective, and the reception pulse of conditional code depositor is that rising edge is effective。
4. matrix keyboard scanning encoding circuit according to claim 1, it is characterised in that: described first shift register, the second shift register shift pulse edge effective；The presetting pulse of described first shift register be high level effective time, it is desirable to scanning impulse is positive pulse, and the reception pulse of conditional code depositor is that trailing edge is effective；Or, when the presetting pulse of the first shift register is Low level effective, it is desirable to scanning impulse is negative pulse, the reception pulse of conditional code depositor is that rising edge is effective。
5. matrix keyboard scanning encoding circuit according to claim 1, it is characterised in that: the conditional code of 2 × N bit data outfan output, 2 × N position of described conditional code depositor；Described conditional code is made up of effective status code and disarmed state code；The key number of described encoder output is made up of effective key number and invalid key number；Described effective status code is produced by effective keyboard operation or state, and encoder inputs the corresponding effectively key number of correspondence output during each effective status code；Described disarmed state code is produced by invalid keyboard operation or state, and encoder inputs all corresponding output invalid key number during all disarmed state codes。
6. matrix keyboard scanning encoding circuit according to claim 5, it is characterised in that: described encoder has M position key outfan, and the selection of M value should meet 2MQuantity sum be more than or equal to effective key number with invalid key number。
7. matrix keyboard scanning encoding circuit according to claim 6, it is characterized in that: also include keyboard state change pulse generation unit, whether the key number for the output of judgment matrix formula keyboard changes, when the key number of matrix keyboard output changes, export keyboard state change pulse。
8. matrix keyboard scanning encoding circuit according to claim 7, it is characterised in that: described keyboard state change pulse generation unit by M position delay buffer, M XOR gate and or door form；M position delay buffer is for carrying out signal delay respectively to the M position key number of matrix keyboard output；The input of the input of M XOR gate respectively M position delay buffer, output signal；The output of M XOR gate is respectively connecting to or the input of door；Or the outfan output keyboard state change pulse of door。
9. matrix keyboard scanning encoding circuit according to claim 1, it is characterised in that: described matrix keyboard by forming X row, the key-press matrix of Y row, row three state buffer, row three state buffer, row status register, column-shaped state depositor form；The line of all key-press matrixs is respectively connecting to the outfan of row three state buffer, and the alignment of all key-press matrixs is respectively connecting to the outfan of row three state buffer；All inputs of row three state buffer and row three state buffer are connected to low level；The line of all key-press matrixs is respectively connecting to the input of row status register, and the alignment of all key-press matrixs is respectively connecting to the input of row status register；The outfan of described row status register and the outfan of row status register collectively constitute keyboard state signal output part。
10. matrix keyboard scanning encoding circuit according to claim 9, it is characterised in that: described matrix keyboard is controlled to obtain keyboard state signal by sampling pulse；Described sampling pulse selects in scanning impulse, shift pulse；Described row three state buffer is when the low level of sampling pulse enables effective, it is desirable to row status register carries out data latch at the rising edge of sampling pulse, row three state buffer enables effectively at the high level of sampling pulse, row status register carries out data latch at the trailing edge of sampling pulse；Or, row three state buffer is when the high level of sampling pulse enables effective, it is desirable to row status register carries out data latch at the trailing edge of sampling pulse, row three state buffer enables effectively in the low level of sampling pulse, row status register carries out data latch at the rising edge of sampling pulse。
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| EP0188151A1 (en) * | 1984-12-20 | 1986-07-23 | Automobiles Peugeot | Keyboard device |
| CN101510127A (en) * | 2009-03-30 | 2009-08-19 | 北京中星微电子有限公司 | Method, apparatus and chip for implementing keyboard module composite key function |
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| CN108572739A (en) | 2018-09-25 |
| CN108572739B (en) | 2021-03-16 |
| CN105700696B (en) | 2018-06-15 |
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