CN108874167A - A kind of keyboard state change pulse generation circuit - Google Patents
A kind of keyboard state change pulse generation circuit Download PDFInfo
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- CN108874167A CN108874167A CN201810660631.4A CN201810660631A CN108874167A CN 108874167 A CN108874167 A CN 108874167A CN 201810660631 A CN201810660631 A CN 201810660631A CN 108874167 A CN108874167 A CN 108874167A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/02—Input arrangements using manually operated switches, e.g. using keyboards or dials
- G06F3/0202—Constructional details or processes of manufacture of the input device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M11/00—Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys
- H03M11/20—Dynamic coding, i.e. by key scanning
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Abstract
A kind of keyboard state change pulse generation circuit, by or door, M delay buffer and M XOR gate form；M delay buffers are used to carry out signal delay respectively to the position the M key number of keyboard scan positioning circuit output；The input of M XOR gate is respectively the input of M delay buffers, output signal；The output of M XOR gate is respectively connected to or the input terminal of door；Or the output end of door exports keyboard state change pulse.Keyboard scan positions circuit and is realized by the circuit that matrix keyboard, buffer register, state Code memory, encoder form, button operation function is either adjusted if necessary to increase and decrease button operation function, modification circuit structure is not needed, the encoded content of encoder need to be only changed.The method does not have to write and run program, reliable operation.
Description
Present patent application is divisional application, and application No. is 201610003614.4, the applying date is in January, 2016 for original bill
5 days, entitled matrix keyboard Scan orientation circuit.
Technical field
The present invention relates to a kind of keyboard scanning circuit, especially a kind of keyboard state change pulse generation circuit.
Background technique
With the continuous development of embedded technology, current each electronic product generallys use microcontroller as control core
The heart, keyboard are widely used as main input equipment.
Current keyboard scan is mainly controlled by microcontroller, need by operation microcontroller in program come into
Row, encounters interference, program is caused to run fast, and scanner program is by cisco unity malfunction.
Application No. is the patents of invention of CN201010153560.2 " a kind of fast scanning and positioning method of matrix keyboard " to adopt
The Scan orientation process for entering keyboard with the mode that keyboard interrupt triggers is judged using the method that keyboard scan step is repeated several times
Whether key is effective, and carries out state judgement to key assignments obtained；If multiple repairing weld state is identical, it is in and stablizes shape
State, key assignments are effective；If multiple repairing weld state is different, key assignments is invalid.Single key stroke or combination key operation need individually judgement, such as
It is single key stroke, then enters singly-bound tupe；Combination key operation in this way then enters Macintosh tupe.Described in the patent
Method solves the shake of the keyboard as caused by the mechanical property of keyboard itself and causes the Problem-Errors such as wrong key, continuous touching,
And the support issue to Macintosh and repeat key.But the method single key stroke needs to handle respectively with key operation is combined；
Not accounting for keyboard state maintains a period of time just to execute the keyboard operation function of effectively operating after；Increase and decrease button operation function
When either adjusting button operation function, need to modify keyboard scan finder structure.When having by key pressing, the method is
Keyboard key assignments is put into queue, waits application program to read, not by the way of exporting interrupt signal.
Summary of the invention
In order to solve above-mentioned technical problem existing for existing keyboard scan localization method, the present invention provides a kind of keyboard shapes
State change pulse generation circuit, by or door, M delay buffer and M XOR gate form；M delay buffers are used for key
The position the M key number of disk Scan orientation circuit output carries out signal delay respectively；The input of M XOR gate is respectively M delay bufferings
The input of device, output signal；The output of M XOR gate is respectively connected to or the input terminal of door；Or the output end of door exports keyboard
State change pulse.
The delay buffer is edge triggered flip flop；The triggering input terminal of the edge triggered flip flop is connected to clock arteries and veins
Punching.The rising edge of the clock pulses is effectively to trigger edge；The delay buffer carries out on effective triggering edge of clock pulses
Data latch；The M key number can only change on effective triggering edge of clock pulses.
The keyboard scan positioning circuit includes matrix keyboard, buffer register, state Code memory, encoder.Institute
It states matrix keyboard and shares X row, Y column, be equipped with N bit keyboard status signal output；The N bit keyboard status signal is level letter
Number；The N=X+Y.The buffer register and state Code memory are N binary registers, the position N of buffer register
Data input pin is connected to N bit keyboard status signal output, the position the N company in the position the 2 × N data input pin of state Code memory
It is connected to N bit keyboard status signal output, in addition the N position the N data output ends for being connected to buffer register；
The encoder has 2 × N coding input ends, and the coding input end 2 × N is connected to state Code memory
2 × N data output ends；The reception pulse input end of the reception pulse input end and state Code memory of the buffer register
It is connected to clock pulses；The matrix keyboard is controlled by sampling pulse and obtains N bit keyboard status signal.The N bit keyboard
Status signal is level signal.
The matrix keyboard is by X row-Y column key-press matrix, row three state buffer, column three state buffer, row Status register
Device, column-shaped state register group at；The line of all key-press matrixs is respectively connected to the output end of row three state buffer, all keys
Matrix column line is respectively connected to the output end of column three state buffer；All inputs of row three state buffer and column three state buffer
End is connected to low level；The line of all key-press matrixs is respectively connected to the input terminal of row status register, all key-press matrixs
Alignment be respectively connected to the input terminal of column status register；The output end of the row status register and column status register
Output end collectively constitutes keyboard state signal output end.
The row three state buffer is when the low level of sampling pulse enables effective, it is desirable that column status register is in sampling arteries and veins
The rising edge of punching carries out data latch, column three state buffer exists in enabled effective, the row status register of the high level of sampling pulse
The failing edge of sampling pulse carries out data latch；Either, row three state buffer is when the high level of sampling pulse enables effective,
It is required that column status register sampling pulse failing edge carry out data latch, column three state buffer sampling pulse low level
Enabled effective, row status register carries out data latch in the rising edge of sampling pulse.
The buffer register and state Code memory clock pulses effective triggering along carrying out data latch simultaneously；Institute
State the status code that 2 × N data output ends of state Code memory export 2 × N；The status code is by effective status code and in vain
Status code composition；The key number of the encoder output is made of effective key number and invalid key number；The effective status code is by effective
Keyboard operation or state generate, and encoder inputs the corresponding effectively key number of corresponding output when each effective status code；The nothing
It imitates status code to be generated by invalid keyboard operation or state, encoder inputs all corresponding output invalid key when all invalid state codes
Number, invalid key number is a value except all effective keys number.The selection of M value should meet 2MMore than or equal to effective key number and in vain
The sum of quantity of key number.
The position N, 2 × N, M refer both to binary digit data.The period of the clock pulses is 20~100ms；Institute
The period for stating sampling pulse is not more than the period of the clock pulses, and special case is that the sampling pulse is the clock pulses.
The clock pulses and sampling pulse are exported by oscillator, and the period of sampling pulse is not more than the week of clock pulses
Phase.The special case of sampling pulse is directly to use clock pulses as sampling pulse.
The beneficial effects of the invention are as follows：It, being capable of run-out key when the key number of keyboard scan positioning circuit output changes
Plate-like state change pulse, the interrupt request singal as reception device.By keyboard scan positioning circuit to single key stroke, Macintosh
Operation, keyboard maintain the positioning of state operation, by clock pulses scan transformation at the status code of same binary length, using system
The mode of one coding is handled, and single key stroke, combination key operation, keyboard maintain state to operate the difference for being only embodied in status code
On；Button operation function is either adjusted if necessary to increase and decrease button operation function, modification circuit structure is not needed, only needs basis
The encoded content of corresponding relationship change encoder between status code and key number after increase and decrease remodifies the read-only storage of write-in
The storage content of device.The circuit does not use the microcontrollers such as single-chip microcontroller, ARM, does not have to operation program, reliable operation.
Detailed description of the invention
Fig. 1 is keyboard scan positioning schematic block circuit diagram；
Fig. 2 is the matrix keyboard circuit diagram of the embodiment of the present invention；
Fig. 3 is the Scan orientation circuit diagram of the embodiment of the present invention；
Fig. 4 is the circuit diagram of the keyboard state change pulse generation circuit of the embodiment of the present invention；
Fig. 5 is the waveform correlation schematic diagram that the keyboard of the embodiment of the present invention effectively operates.
Specific embodiment
Below in conjunction with attached drawing, the invention will be further described.
Fig. 1 is keyboard scan positioning schematic block circuit diagram, is posted by matrix keyboard 400, buffer register 100, status code
Storage 200, encoder 300 form, and Fig. 1 further includes oscillator 500.
Oscillator 500 is multivibrator, is equipped with CP output terminal of clock pulse and CK sampling pulse output end, CP clock arteries and veins
The period of punching is 20~100ms, and the period of CK sampling pulse is not more than the period of CP clock pulses.
Fig. 2 is the circuit diagram of the matrix keyboard 400 of the embodiment of the present invention, 2 rows, 2 column is shared, totally 4 keys, by key
S1, key S2, key S3, key S4 and be connected to the pull-up resistor R1 of power supply+VCC, pull-up resistor R2, pull-up resistor R3, on
Pull-up resistor R4 and row three state buffer 401, column three state buffer 402, row status register 403, column status register 404
Composition.2 output ends Y1, Y2 of row three state buffer 401 are respectively connected to 2 lines, and 2 of column three state buffer 402 are defeated
Outlet Y3, Y4 is respectively connected to 2 alignments；All input terminal X1~X4 of row three state buffer 401 and column three state buffer 402
It is connected to low level.
2 input terminals D41, D42 of row status register 403 are respectively connected to 2 lines, and the 2 of column status register 404
A input terminal D43, D44 are respectively connected to 2 alignments；2 output ends Q41, Q42 of row status register 403 export row state
Signal I1, I2,2 output ends Q43, Q44 of column status register 404 export column status signal I3, I4；Row status register
403 2 output ends and 2 output ends of column status register 404 collectively constitute 4 bit keyboard status signal outputs, export
Keyboard state signal I1, I2, I3, I4.
In embodiment, the enabled input EN1 low level of row three state buffer 401 is effective, and column three state buffer 402 enables
It is effective to input EN2 high level；EN1 and EN2 is connected to the CK sampling pulse output end of oscillator 500.Row status register 403
It is exported with reception pulse input end CLK3, CLK4 of column status register 404 CK sampling pulse for being connected to oscillator 500
End, row status register 403 carry out data latch in the failing edge of CK sampling pulse, and column status register 404 samples arteries and veins in CK
The rising edge of punching carries out data latch.
When row three state buffer 401 and column three state buffer 402 are using the three state buffer with model, for example, making simultaneously
When with three state buffer 74HC241, the enabled input of 74HC241 is that high level is effective, therefore, CK sampling pulse output end with
Between the enabled input terminal EN1 of row three state buffer 401, need to increase a NOT gate.Similarly, when row status register 403
With column status register 404 using the data register with model, for example, row status register 403 and column status register 404
When using double D trigger 74HC74 composition data register, the triggering input of 74HC74 is that rising edge is effective, therefore, in CK
Between sampling pulse output end and the reception pulse input end CLK3 of row status register 403, need to increase a NOT gate.
Buffer register 100, state Code memory 200, encoder 300 in Fig. 1 form Scan orientation circuit, implement
Example circuit diagram is as shown in Figure 3.Matrix keyboard circuit has 4 keys, and the keyboard state signal of matrix keyboard output is 4 two
Ary codes, therefore, buffer register 100 require deposit 4 bit binary datas, state Code memory 200 require deposit 8 two into
Data processed.4 data input pins of buffer register 100 are connected to I1, I2, I3, I4；8 data of state Code memory 200
In input terminal, 4 data input pins are connected to I1, I2, I3, I4, and in addition 4 data input pins are connected to buffer register 100
4 output ends；8 input terminals of encoder 300 are connected to 8 output ends of state Code memory 200.Encoder 300 is defeated
It is scanned 4 determining binary system keys number of positioning out.
In Fig. 3, trigger 101 forms buffer register 100, trigger 201 forms state Code memory 200.Trigger
101 are made of 4 edge triggered flip flops, and the triggering input terminal of 4 edge triggered flip flops is the reception pulse input of buffer register 100
End, is connected to the CP output terminal of clock pulse of oscillator 500；Trigger 201 is made of 8 edge triggered flip flops, 8 edge touchings
The triggering input terminal for sending out device is the reception pulse input end of state Code memory 200, is connected to the CP clock arteries and veins of oscillator 500
Rush output end.Trigger 101, trigger 201 are preferably made of the d type flip flop of edging trigger, for example, by double D trigger
74HC74,4D trigger 74HC175 composition.In Fig. 3 embodiment, trigger 101, trigger 201 select rising edge to trigger
8D trigger 74HC273 makes the clearing of 74HC273 at this point, clear input unillustrated in Fig. 3 is connected to high level
Function is in invalid state, only has Trigger Function；Trigger 101 only needs 4D trigger, arbitrarily uses selected 8D trigger
4 d type flip flops in 74HC273.Triggering input terminal CLK1, CLK2 of two 8D trigger 74HC273 is connected to CP.
In Fig. 3, read-only memory 301 forms encoder 300.Address input end A7~A0 of read-only memory 301 is to compile
The input terminal of code device 300, data output end D3~D0 of read-only memory 301 are coding output end C3~C0 of encoder 300.
The working principle that keyboard scan positions circuit is as follows：
In Fig. 2,4 keys of matrix keyboard are arranged with 2 × 2 matrix form, and all lines and alignment all pass through
Pull-up resistor is connected to power supply+VCC.Matrix keyboard is controlled by CK sampling pulse, using reversal process obtain keyboard state signal I4,
I3,I2,I1.For example, it is 1010 that the keyboard state signal of key pressing, which is not the keyboard state signal that 1111, S1 is pressed, S1, S2
The keyboard state signal pressed simultaneously is 0010.4 binary codes of keyboard state signal are known as key assignments.
The control of CK sampling pulse carries out the method that key assignments is read in sampling to matrix keyboard：In the low electricity of CK sampling pulse
It is flat, all lines are controlled by row three state buffer 401 and export low level, column three state buffer 402 exports the open column of high-impedance state
Line；It is sampled in the rising edge of CK sampling pulse by column status register 404 and reads alignment state as the 2 high of key assignments；In CK
The high level of sampling pulse controls all alignments by column three state buffer 402 and exports low level, and row three state buffer 401 is defeated
The open line of high-impedance state out；It is sampled in the failing edge of CK sampling pulse by row status register 403 and reads line state as key
Low 2 of value；In cycles, 4 key assignments that column status register 404, row status register 403 export are always the above process
The last state of matrix keyboard.
Sampling is carried out to matrix keyboard from the control of CK sampling pulse and reads the method for key assignments it is found that row three state buffer
401 when the low level of CK sampling pulse enables effective, while requiring column status register 404 in the rising edge of CK sampling pulse
Data latch, column three state buffer 402 are carried out in enabled effective, the row status register 403 of the high level of CK sampling pulse in CK
The failing edge of sampling pulse carries out data latch.In turn, if row three state buffer 401 makes in the high level of CK sampling pulse
When can be effective, while column status register 404 being required to carry out data latch, column three state buffer in the failing edge of CK sampling pulse
402 CK sampling pulse low level is enabled effectively, row status register 403 in the rising edge of CK sampling pulse carries out data lock
It deposits.
During above-mentioned CK sampling pulse controls sampling and reads key assignments, row status register 403, column status register
404 precisely column three state buffers 402 and at the time of the 401 carry out state reversion of row three state buffer at the time of sampled, just
Often the row status register 403 under work or column status register 404 can be sampled correctly.If it is required that having in certain timing
Allowance, then can be to being connected to column three state buffer 402 and the CK sampling pulse of row three state buffer 401 postpones, method
Be enable CK sampling pulse by RC retardation ratio circuit be then connected to row three state buffer 401 and column three state buffer 402 EN1,
EN2, delay time are determined by RC retardation ratio circuit, determine that the principle of the delay time of RC retardation ratio circuit is, the CK of delay samples arteries and veins
Phase is rushed no more than 90 °；Either CK sampling pulse is then connected to row three state buffer 401 after the buffering of several gate circuits
With EN1, EN2 of column three state buffer 402, delay time at this time is the overall delay time of several gate circuits.
Buffer register 100, state Code memory 200 have under the control of CP clock pulses in each period of CP
Effect triggering is along progress data latch.In Fig. 3,74HC273 is that rising edge triggering is effective, therefore, effective triggering of CP clock pulses
Edge is rising edge.
4 data input pin D20~D23 in 8 data input pins of state Code memory 200 are connected directly to matrix
Status signal I1, I2, I3, I4 of formula keyboard output, in addition 4 data input pin D24~D27 are connected to buffer register 100
Data output end Q10~Q13,4 data input pin D10~D13 of buffer register 100 are connected directly to matrix keyboard
Status signal I1, I2, I3, I4 of output, therefore, on effective triggering edge of CP clock pulses, 8 of state Code memory 200
In data output end, 4 data corresponding with status signal I1, I2, I3, I4 for being connected directly to matrix keyboard output are defeated
The data that outlet Q20~Q23 is latched are the current state of matrix keyboard, and 4 digits are stated to be existing state key assignments；It is slow with being connected to
The data for rushing the corresponding 4 data output end Q24~Q27 latch of data output end of register 100 are matrix keyboard
Previous state, state key assignments before 4 digits are stated to be.The existing state key assignments and 4 of 4 of 200 data output end of state Code memory output
State key assignments collectively constitutes 8 status codes before position.
The current state and mode of operation of 8 status codes matrix keyboard for identification.For example, the present embodiment
In, the status code of no key pressing is 11111111；The status code of S1 key singly-bound pushing operation is 11111010；S1 key singly-bound is pressed
And the status code maintained is 10101010；The status code of S1 key singly-bound release operation is 10101111；S2 key singly-bound pushing operation
Status code be 11110110；The status code of S4 key singly-bound pushing operation is 11110101；The S1 of S2+S1 combination operation presses behaviour
Make, after expression first presses S2, maintains the state pressed to press the operation of S1 again in S2, the status code of the operation is 01100010.
Encoder 300 is used to status code being converted to key number.In embodiment, it is equipped with 6 effective keyboard operations and state,
Including：
Operation 0：The singly-bound pushing operation of key S1, key number are 0000；
Operation 1：The singly-bound pushing operation of key S2, key number are 0001；
Operation 2：The singly-bound pushing operation of key S3, key number are 0010；
Operation 3：Key S3 singly-bound press after maintenance state, key number be 0011；
Operation 4：After key S4 singly-bound is pressed, then the combination key operation of S2 is pressed the button, key number is 0100；
Operation 5：The singly-bound of key S1 discharges operation, and key number is 0101.
The status code and key number obtained according to above-mentioned regulation is shown in coding schedule 1：
1 coding schedule of table
| Keyboard operation | Status code (address) | Key number (storing data) |
| S1 singly-bound is pressed | 11111010 | 0000 |
| S2 singly-bound is pressed | 11110110 | 0001 |
| S3 singly-bound is pressed | 11111001 | 0010 |
| S3 singly-bound presses maintenance | 10011001 | 0011 |
| S4+S2 combination operation | 01010100 | 0100 |
| The release of S1 singly-bound | 10101111 | 0101 |
| Other operations or state | ******** | 1111 |
Encoder 300 is combinational logic circuit, designs circuit, meets the logical relation of table 1.
The encoder 300 of embodiment is preferably made of read-only memory 301.Read-only memory 301 has 8 bit address, and totally 28
A 4 binary storage cells.6 effective keyboard operations and state have 6 effective status codes, corresponding 6 effective keys number；
It, will in storage unit corresponding with 6 effective status codes using status code as address A7~A0 of read-only memory 301
Corresponding key number is written as storing data.The status code generated except 6 effective keyboard operations and state is invalid state
Code, i.e., other operations or state in table 1 are generated for invalid state code；In other storage units, all write-in is invalid
Key number, invalid key number are that one except 6 effective keys number is worth, and in embodiment, invalid key number is 1111.
Read-only memory 301 always works at data output state.When read-only memory 301 has piece selected control system, data
When exporting cushioning control function, its piece selected control system, data output cushioning control should be made to be in effective status.
Key number in embodiment is 4 binary codes.The number of bits of key number can according to need increase, or subtract
It is few, at this point, need to only select the read-only memory 301 to match with this.If the number of bits of key number is M, the selection of M value
2 should be metMMore than or equal to the sum of effective key number and the quantity of invalid key number.When matrix keyboard has N bit keyboard status signal defeated
When out, read-only memory 301 needs the input of 2 × N bit address, M-bit data output.
Button operation function is either adjusted if necessary to increase and decrease button operation function, only need to modify table 1 as needed, it will
Modified content re-writes the storage content of read-only memory 301.
In embodiment, when matrix keyboard S1 singly-bound is pressed, CP clock pulses of the encoder 300 after S1 singly-bound is pressed
Effective triggering along starting, to effective triggering edge of next CP clock pulses until, coding output end C3~C0 run-out key number
0000；When matrix keyboard S2 singly-bound is pressed, effective triggering edge of CP clock pulses of the encoder 300 after S2 singly-bound is pressed
Start, until effective triggering edge of next CP clock pulses, run-out key number 0001；After matrix keyboard first presses S4,
S2 is pressed again, and encoder 300 starts on effective triggering edge that S2 combines the CP clock pulses after key pressing, until next CP clock
Until effective triggering edge of pulse, run-out key number 0100；When the release of matrix keyboard S1 singly-bound, encoder 300 is in S1 singly-bound
Effective triggering edge of CP clock pulses after release starts, until effective triggering edge of next CP clock pulses, run-out key
Number 0101；Therefore, it can be seen that when identification be effective button operation of matrix keyboard when, encoder 300 is effectively pressed at this
Effective triggering edge of CP clock pulses after key operation starts, until effective triggering edge of next CP clock pulses, output
Duration is effective key number of CP width clock cycle.
In embodiment, when matrix keyboard S3 singly-bound is pressed, CP clock pulses of the encoder 300 after S3 singly-bound is pressed
Effective triggering along starting, until effective triggering edge of next CP clock pulses, run-out key number 0010；In next CP
Effective triggering edge of clock pulses starts, until effective touching of next CP clock pulses after S3 singly-bound presses maintenance state
Until sending out edge, 300 run-out key number 0011 of encoder；Therefore, it can be seen that when identification be the maintenance state of matrix keyboard when,
Encoder 300 exports the duration of effective key number and the duration of the maintenance state is adapted.
When except the state of keyboard or operation being 6 effective keyboard operations described in table 1 and state, encoder
300 output invalid keys number 1111.Effective key number, or output invalid key number are either exported, encoder 300 changes output content
At the time of for CP clock pulses effective triggering edge；In embodiment, encoder 300 is CP clock arteries and veins at the time of changing output content
The rising edge of punching.
The period of CP clock pulses is the scan period of matrix keyboard.The keyboard scan period, can in 20ms or more
It has been effectively shielded from the influence of keyboard shake；The keyboard scan period in 100ms or less, is unlikely to omit keyboard operation；
Therefore, the period of CP clock pulses should control in 20~100ms.
The cycle request of CK sampling pulse is not more than the period of CP clock pulses, in this way, each effective in CP clock pulses
When triggering is along acquisition status code, 4 key assignments that can guarantee that column status register 404, row status register 403 export are always
The last state of matrix keyboard.The special case of CK sampling pulse is directly to use CP clock pulses as CK sampling pulse.
In embodiment, CP clock pulses, CK sampling pulse are generated and are exported by oscillator 500.CP clock pulses and CK
Sampling pulse can also be provided by other circuits or device.
Fig. 4 is the circuit diagram of the keyboard state change pulse generation circuit of the embodiment of the present invention.What it is when identification is matrix form
When effective button operation of keyboard, effective triggering edge of CP clock pulses of the encoder 300 after effective button operation starts,
Until effective triggering edge of next CP clock pulses, output duration is the effective of CP width clock cycle
Key number.The device for receiving the matrix keyboard output, needs to inquire the output of matrix keyboard constantly, obtains key number.Inquiry
Period distances be necessarily less than period of CP clock pulses.
Whether key number of the circuit shown in Fig. 4 for the output of judgment matrix formula keyboard changes, when matrix keyboard exports
Key number when changing, export keyboard state change pulse, the reception device receiving matrix formula for auxiliary moment configuration keyboard
The key number of keyboard output, for example, using keyboard state change pulse as the interrupt request singal of reception device.
Circuit shown in Fig. 4 by delay buffer 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or
Door 606 forms.Delay buffer 601 is made of 4 edge triggered flip flops only with Trigger Function, the touching of 4 edge triggered flip flops
The reception pulse input end that input terminal is delay buffer 601 is sent out, the CP output terminal of clock pulse of oscillator 500 is connected to；
Delay buffer 601 carries out data latch on effective triggering edge of CP clock pulses.
Delay buffer 601 is used to carry out at delay 4 data C3~C0 of the coding output end of encoder 300 respectively
Reason.4 data input pin D63~D60 of delay buffer 601 are connected to coding output end C3~C0 of encoder 300, delay
The data that 4 data output end Q63~Q60 of buffer 601 are accordingly exported are C31~C01；C31~C01 is by delay buffering
After the first-level buffer of device 601, signal ratio C3~C0 postpones a CP clock cycle, and Fig. 5 show the embodiment of the present invention
The waveform correlation schematic diagram that effectively operates of keyboard.It is located at the section T1 of CP clock pulses, matrix keyboard exists primary effective
It operates, effective operation of embodiment includes：S1 singly-bound is pressed, S2 singly-bound is pressed, S3 singly-bound is pressed, the S2 of S4+S2 combination operation
It presses, the release of S1 singly-bound.On the next effective triggering edge once effectively operated, i.e. in Fig. 5 after the section CP clock pulses T1
Rising edge, encoder 300 export coding C3~C0 change；In the section T2, encoder 300 exports having for a cycle
Effect coding C3~C0；In T3, T4 and section later, coding C3~C0 that encoder 300 exports changes again and enters maintenance
State, the maintenance state may be that such as S1 singly-bound presses subsequent maintenance state, export invalid key number, it is also possible to S3 singly-bound
Subsequent maintenance state is pressed, effective key number is exported, until effectively operation next time.
Coding C3~C0 that D6 pulse in Fig. 5 schematically illustrates the output of encoder 300 is not become in maintenance state
Change, still change, the D6 pulse is not present in actual circuit.As shown in figure 5, D6 pulse is low level, schematic table
Show that coding C3~C0 that encoder 300 exports is not changed in maintenance state；D6 pulse is high level, schematically illustrates volume
Code device 300 exports efficient coding C3~C0 of a cycle.What the Q6 in Fig. 5 reflected is the situation of change of C31~C01, it is clear that
Q6 ratio D6 postpones a CP clock cycle.Equally, the Q6 pulse is not present in actual circuit.
In Fig. 5, coding C3~C0 that encoder 300 exports is not changed, still changes in maintenance state,
Really by 606 4 delay buffers 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or door groups
At logic circuit complete.1 corresponding, input point that 4 XOR gates encode in output end C3~C0 respectively with encoder 300
It Wei not the inputs of 4 delay buffers 601, output signal.For example, two input signals of XOR gate 602 be respectively C0 and
C01, C01 ratio C0 postpone a CP clock cycle, and therefore, when C0 changes, XOR gate 602 exports 1 CP clock
The positive pulse of pulse period width；When C0 is a CP change width clock cycle signal, XOR gate 602 exports 2
The positive pulse of CP width clock cycle.XOR gate 603, XOR gate 604, XOR gate 605 judge whether C1~C3 sends out respectively
Changing, principle with judge it is identical whether C0 changes.XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605
Output end is respectively connected to or whether the input terminal of door 606 or door 606 change for comprehensive descision C0~C3, as long as C0
~C3 changes or door 606 exports keyboard state change pulse F, which is positive pulse.
In embodiment, delay buffer 601 selects the 8D trigger 74HC273 of rising edge triggering.In embodiment, encoder
300 outputs are 4 binary system keys number, therefore, 4 d type flip flops of delay buffer 601 needs.Due to delay buffer 601
In 4 d type flip flops and trigger 101 in the triggering input terminals of 4 d type flip flops be connected to the CP clock of oscillator 500
Pulse output end, therefore, delay buffer 601 and trigger 101 can share a 8D trigger 74HC273.
Delay buffer 601 can also use other schemes, for example, using RC circuit, using 4 RC circuits respectively to C0
~C3 is postponed；If the clock cycle CP of delay time of RC circuit less than one, encoder 300 exports a week
When efficient coding C3~C0 of phase, starting and export efficient coding C3~C0 in output efficient coding C3~C0 terminates all to generate one
The width of a keyboard state change pulse, keyboard state change pulse is equal to RC circuit delay time；If the delay of RC circuit
Time is more than or equal to a CP clock cycle, then when encoder 300 exports efficient coding C3~C0 of a cycle, defeated
A keyboard state change pulse is generated when efficient coding C3~C0 starts out, pulse width is more than or equal to 2 CP clock pulses
Period.It is required that the delay time of RC circuit is no more than 2 CP clock cycles, failed to report in order to avoid generating.
In the invention circuit, the positioning of state operation will be maintained to single key stroke, combination key operation, keyboard, by CP
Pulse scan transformation is handled by the way of Unified coding at the status code of same binary length, single key stroke, combination
Key operation, keyboard maintain state operation to be only embodied in not being same as above for status code；If necessary to increase and decrease button operation function either
Button operation function is adjusted, modification keyboard scanning circuit structure is not needed, need to only be updated and be encoded according to the state code table after increase and decrease
Device 300 re-writes the storage content for updating read-only memory 301.The invention circuit do not use single-chip microcontroller,
The microcontrollers such as ARM do not have to operation program, reliable operation.
Claims (10)
1. a kind of keyboard state change pulse generation circuit, it is characterised in that：By or door, M delay buffer and M XOR gate
Composition；M delay buffers are used to carry out signal delay respectively to the position the M key number of keyboard scan positioning circuit output；M exclusive or
The input of door is respectively the input of M delay buffers, output signal；The output of M XOR gate be respectively connected to or door it is defeated
Enter end；Or the output end of door exports keyboard state change pulse；Institute's rheme is binary digit.
2. keyboard state change pulse generation circuit according to claim 1, it is characterised in that：The delay buffer is
Edge triggered flip flop；The triggering input terminal of the edge triggered flip flop is connected to clock pulses.
3. keyboard state change pulse generation circuit according to claim 2, it is characterised in that：The clock pulses it is upper
It rises and triggers edge along to be effective；The delay buffer carries out data latch on effective triggering edge of clock pulses；The M key number
It can only change on effective triggering edge of clock pulses.
4. keyboard state change pulse generation circuit according to any one of claim 1-3, it is characterised in that：The key
Disk Scan orientation circuit includes matrix keyboard, buffer register, state Code memory, encoder.
5. keyboard state change pulse generation circuit according to claim 4, it is characterised in that：The matrix keyboard is total
There are X row, Y column, is equipped with N bit keyboard status signal output；The N bit keyboard status signal is level signal；The N=X+Y；
The buffer register and state Code memory are N binary registers, the position the N data input pin of buffer register
It is connected to N bit keyboard status signal output, the position N in the position the 2 × N data input pin of state Code memory is connected to N keys
Disk status signal output, in addition the N position N data output ends for being connected to buffer register；
The encoder has 2 × N coding input ends, and the coding input end 2 × N is connected to 2 × N of state Code memory
Position data output end；
The reception pulse input end of the buffer register and the reception pulse input end of state Code memory are connected to clock
Pulse；The matrix keyboard is controlled by sampling pulse and obtains N bit keyboard status signal.
6. keyboard state change pulse generation circuit according to claim 5, it is characterised in that：The matrix keyboard by
X row-Y column key-press matrix, row three state buffer, column three state buffer, row status register, column-shaped state register group at.
7. keyboard state change pulse generation circuit according to claim 6, it is characterised in that：The row of all key-press matrixs
Line is respectively connected to the output end of row three state buffer, and the alignment of all key-press matrixs is respectively connected to the defeated of column three state buffer
Outlet；All input terminals of row three state buffer and column three state buffer are connected to low level；The line of all key-press matrixs point
It is not connected to the input terminal of row status register, the alignment of all key-press matrixs is respectively connected to the input of column status register
End；The output end of the row status register and the output end of column status register collectively constitute the output of N bit keyboard status signal
End.
8. keyboard state change pulse generation circuit according to claim 7, it is characterised in that：The row three state buffer
When the low level of sampling pulse enables effective, it is desirable that column status register sampling pulse rising edge carry out data latch,
Column three state buffer carries out data in the failing edge of sampling pulse in enabled effective, the row status register of high level of sampling pulse
It latches；Either, row three state buffer is when the high level of sampling pulse enables effective, it is desirable that column status register is in sampling arteries and veins
The failing edge of punching carries out data latch, column three state buffer exists in enabled effective, the row status register of the low level of sampling pulse
The rising edge of sampling pulse carries out data latch.
9. keyboard state change pulse generation circuit according to claim 5, it is characterised in that：The buffer register and
State Code memory carries out data latch on effective triggering edge of clock pulses simultaneously；2 × N data of the state Code memory
Output end exports 2 × N status codes；The status code is made of effective status code and invalid state code；The encoder is defeated
Key number out is made of effective key number and invalid key number；The effective status code is generated by effective keyboard operation or state, coding
Device inputs the corresponding effectively key number of corresponding output when each effective status code；The invalid state code by invalid keyboard operation or
State generates, and encoder inputs all corresponding output invalid key number when all invalid state codes.
10. keyboard state change pulse generation circuit according to claim 9, it is characterised in that：The selection of M value should meet
2MMore than or equal to the sum of effective key number and the quantity of invalid key number.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810660631.4A CN108874167B (en) | 2016-01-05 | 2016-01-05 | Keyboard state change pulse generating circuit |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610003614.4A CN105703780B (en) | 2016-01-05 | 2016-01-05 | Matrix keyboard Scan orientation circuit |
| CN201810660631.4A CN108874167B (en) | 2016-01-05 | 2016-01-05 | Keyboard state change pulse generating circuit |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610003614.4A Division CN105703780B (en) | 2016-01-05 | 2016-01-05 | Matrix keyboard Scan orientation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108874167A true CN108874167A (en) | 2018-11-23 |
| CN108874167B CN108874167B (en) | 2021-02-26 |
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| CN201810660969.XA Expired - Fee Related CN108880561B (en) | 2016-01-05 | 2016-01-05 | Matrix type keyboard scanning and positioning method |
| CN201610003614.4A Active CN105703780B (en) | 2016-01-05 | 2016-01-05 | Matrix keyboard Scan orientation circuit |
| CN201810660631.4A Expired - Fee Related CN108874167B (en) | 2016-01-05 | 2016-01-05 | Keyboard state change pulse generating circuit |
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| CN201610003614.4A Active CN105703780B (en) | 2016-01-05 | 2016-01-05 | Matrix keyboard Scan orientation circuit |
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| SU1005011A1 (en) * | 1981-06-09 | 1983-03-15 | Уфимский Ордена Ленина Авиационный Институт Им.Орджоникидзе | Data input device |
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- 2016-01-05 CN CN201610003614.4A patent/CN105703780B/en active Active
- 2016-01-05 CN CN201810660631.4A patent/CN108874167B/en not_active Expired - Fee Related
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| JPS6062259A (en) * | 1983-09-16 | 1985-04-10 | Hitachi Ltd | Data transmission equipment |
| CN1049415A (en) * | 1989-08-09 | 1991-02-20 | 东少青 | Abacus interface arrangement of general computer |
| US20060247880A1 (en) * | 2005-04-29 | 2006-11-02 | International Business Machines Corporation | Testable digital delay line |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN108880561B (en) | 2022-03-18 |
| CN108874167B (en) | 2021-02-26 |
| CN108880561A (en) | 2018-11-23 |
| CN105703780A (en) | 2016-06-22 |
| CN105703780B (en) | 2018-09-11 |
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