CN108874164B - Matrix keyboard inversion method scanning method - Google Patents
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- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
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Abstract
A matrix keyboard inversion method scanning method, X row lines and Y column lines of the matrix keyboard are connected with pull-up resistors, and sampling pulses control the X row lines and the Y column lines to be in a low level state alternately; the Y row line state when the X row lines are at a low level is latched to obtain a Y-bit row state signal, and the X row line state when the Y row lines are at a low level is latched to obtain an X-bit row state signal; the X-bit row state signal and the Y-bit column state signal jointly form an output N-bit keyboard state signal. The method realizes the reversal scanning of the matrix keyboard by adopting a sequential logic circuit, does not use microcontrollers such as a single chip microcomputer and an ARM, does not need running programs, and works reliably.
Description
The invention discloses a matrix type keyboard scanning circuit and a coding circuit, which are filed by divisional application, wherein the original application number is 201610003060.8, and the application date is 2016, 1, 5 and 2016.
Technical Field
The invention relates to a keyboard scanning method, in particular to a matrix type keyboard inversion method scanning method.
Background
With the continuous development of embedded technology, various electronic products generally adopt a microcontroller as a control core and a keyboard as a main input device, and are widely applied.
The existing keyboard scanning is mainly controlled by a microcontroller, and is performed by running a program in the microcontroller, so that the program runs off due to interference, and the scanning program cannot work normally.
The invention patent with application number CN201010153560.2, "a method for fast scanning and positioning matrix keyboard", adopts a mode of keyboard interrupt triggering to enter the scanning and positioning process of keyboard, adopts a method of repeating the keyboard scanning step for many times to judge whether the key is valid, and makes state judgment on the obtained key value; if the multiple sampling states are the same, the key value is in a stable state and is valid; if the multiple sampling states are different, the key value is invalid. The single key operation or the combined key operation needs to be judged separately, if the single key operation is carried out, the single key processing mode is entered; if the operation is a combination key operation, a combination key processing mode is entered. The method disclosed in the patent solves the problems of wrong keys, continuous key touch and other errors caused by keyboard shaking due to the mechanical characteristics of the keyboard, and the problem of supporting combined keys and repeated keys. But the single key operation and the combined key operation of the method need to be processed respectively; a keyboard operation function of executing effective operation after a certain period of time of maintaining the keyboard state is not considered; when the key operation function is increased or decreased or adjusted, the structure of the keyboard scanning and positioning program needs to be modified.
Disclosure of Invention
In order to solve the technical problems of the existing keyboard scanning and positioning method, the invention provides a matrix keyboard inversion method scanning method, wherein X row lines and Y column lines of the matrix keyboard are connected with pull-up resistors, and sampling pulses are used for controlling the X row lines and the Y column lines to be alternately in a low-level state; the Y row line state when the X row lines are at a low level is latched to obtain a Y-bit row state signal, and the X row line state when the Y row lines are at a low level is latched to obtain an X-bit row state signal; the X-bit row state signal and the Y-bit column state signal jointly form an output N-bit keyboard state signal; and N is X + Y.
The sampling pulse controls X row lines and Y column lines to be alternately in a low level state, and the low level state is realized by a row tri-state buffer and a column tri-state buffer; the row lines of all the key matrixes are respectively connected to the output ends of the row tri-state buffers, and the column lines of all the key matrixes are respectively connected to the output ends of the column tri-state buffers; all inputs of the row and column tri-state buffers are connected to a low level.
The Y-bit row state signal is obtained by latching the Y-column line state when the X-column lines are at a low level, and the X-bit row state signal is obtained by latching the X-column line state when the Y-column lines are at a low level, wherein the Y-bit row state signal is realized by a row state register and a column state register; the row lines of all the key matrixes are respectively connected to the input ends of the row state registers, and the column lines of all the key matrixes are respectively connected to the input ends of the column state registers.
Enabling the row tri-state buffer to be effective at the low level of the sampling pulse, and enabling the column tri-state buffer to be effective at the high level of the sampling pulse; the column state register latches data at a rising edge of the sampling pulse, and the row state register latches data at a falling edge of the sampling pulse. Or, the row three-state buffer is enabled to be effective at the high level of the sampling pulse, and the column three-state buffer is enabled to be effective at the low level of the sampling pulse; the column state register latches data at a falling edge of the sampling pulse, and the row state register latches data at a rising edge of the sampling pulse.
The N-bit keyboard state signal is sent to a circuit consisting of a first shift register, a second shift register, a state code register and an encoder for encoding; the matrix keyboard scanning circuit is composed of a matrix keyboard circuit, a first shift register, a second shift register, a state code register and an encoder, and is synchronously controlled by scanning pulses, first shift pulses and second shift pulses. The matrix keyboard circuit comprises a key matrix of X row lines and Y column lines, a row tri-state buffer, a column tri-state buffer, a row state register and a column state register.
The first shift register has N-bit synchronous parallel input and serial output functions; the second shift register has serial input and 2 XN bit parallel output functions.
The N-bit parallel input end of the first shift register is connected to the N-bit keyboard state signal output end; the serial input end of the second shift register is connected to the serial output end of the first shift register; the clock pulse input end of the first shift register is connected to the first shift pulse, the shift pulse input end of the second shift register is connected to the second shift pulse, and the parallel input control end of the first shift register is connected to the scanning pulse.
The state code register is a 2 XN bit binary register; the 2 XN bit data input end of the state code register is connected to the 2 XN bit parallel output end of the second shift register; and the receiving pulse input end of the state code register is connected to the scanning pulse.
The encoder has a 2 xn bit encoding input connected to the 2 xn bit data output of the status code register.
The time sequence of the scanning pulse, the first shift pulse and the second shift pulse meets the following requirements:
every 1+ N first shift pulses are a scanning period;
in a scanning period, during the 1 st first shift pulse period, the scanning pulse enables the effective level for the parallel input of the first shift register;
in one scanning period, in N first shifting pulse periods after the 1 st first shifting pulse period, scanning pulses are used for inputting enabling invalid levels to the first shifting register in parallel;
in one scanning period, the second shift pulse has N shift pulses.
The period of the scanning pulse is 20-100 ms.
The shift pulse edges of the first shift register and the second shift register are effective; the effective edge time of the N shift pulses of the second shift pulse is not later than the effective edge time of the corresponding N shift pulses of the first shift pulse.
The serial shift and the parallel input presetting of the first shift register are controlled by a first shift pulse, and the serial shift or the parallel input presetting is realized at the effective edge of the first shift pulse.
The 2 XN bit data output end of the state code register outputs a 2 XN bit state code; the state code consists of a valid state code and an invalid state code; the key number output by the encoder consists of an effective key number and an ineffective key number; the effective state codes are generated by the operation or the state of an effective keyboard, and corresponding effective key numbers are correspondingly output when the encoder inputs each effective state code; the invalid state code is generated by invalid keyboard operation or state, and when the encoder inputs all the invalid state codes, the encoder correspondingly outputs invalid key numbers.
The encoder has an M-bit key number output, and M should be selected to satisfy 2MGreater than or equal to the sum of the number of valid and invalid key numbers.
The matrix type keyboard scanning circuit further comprises a keyboard state change pulse generating unit which is used for judging whether the key number output by the matrix type keyboard changes or not, and when the key number output by the matrix type keyboard changes, the keyboard state change pulse is output.
The keyboard state change pulse generation unit consists of an OR gate, an M-bit delay buffer and M XOR gates; the M-bit delay buffer is used for respectively carrying out signal delay on the M-bit key numbers output by the matrix keyboard; the inputs of the M exclusive-OR gates are input signals and output signals of the M-bit delay buffer respectively; the outputs of the M exclusive-OR gates are respectively connected to the input ends of the OR gates; the output end of the OR gate outputs a keyboard state change pulse.
The N bits, 2 XN bits and M bits all refer to binary bit data.
The invention has the beneficial effects that: the scanning of the matrix keyboard by the inversion method is realized by adopting a sequential logic circuit, a microcontroller such as a single chip microcomputer and an ARM (advanced RISC machine) is not used, a running program is not needed, and the operation is reliable; the method comprises the steps of scanning and positioning single key operation, combined key operation and keyboard maintenance state operation, converting a plurality of pulses meeting specific time sequence requirements into state codes with the same binary length, and processing the state codes in a unified coding mode, wherein the single key operation, the combined key operation and the keyboard maintenance state operation are only reflected on different state codes; if the key operation function needs to be increased or decreased or adjusted, the structure of the keyboard scanning circuit does not need to be modified, and the encoding content of the encoder is changed according to the corresponding relation between the increased or decreased state codes and the key numbers, namely the storage content written into the read-only memory is modified again.
Drawings
FIG. 1 is a schematic block diagram of a matrix keyboard scanning circuit;
FIG. 2 illustrates a matrix keyboard circuit according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of scan encoding according to an embodiment of the present invention;
FIG. 4 is a pulse timing diagram of an embodiment of the present invention;
FIG. 5 is a schematic diagram of a pulse circuit of an embodiment of the present invention;
FIG. 6 is a circuit diagram of a keyboard state change pulse generating unit according to an embodiment of the present invention;
FIG. 7 is a waveform diagram illustrating the operation of the keyboard according to the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
Fig. 1 is a schematic block diagram of a matrix keyboard scanning circuit, which is composed of a matrix keyboard 400, a first shift register 100, a second shift register 200, a status code register 500, and an encoder 300. Matrix keyboard 400 is a matrix keyboard circuit.
Fig. 2 shows an embodiment of a matrix keyboard circuit of the present invention, which has 2 rows, 2 columns, and 4 keys, and is composed of a key S1, a key S2, a key S3, a key S4, a pull-up resistor R1 connected to a power supply + VCC, a pull-up resistor R2, a pull-up resistor R3, a pull-up resistor R4, a row tri-state buffer 401, a column tri-state buffer 402, a row state register 403, and a column state register 404. 2 output terminals Y1 and Y2 of the row tri-state buffer 401 are respectively connected to 2 row lines, and 2 output terminals Y3 and Y4 of the column tri-state buffer 402 are respectively connected to 2 column lines; all the inputs X1-X4 of the row tri-state buffer 401 and the column tri-state buffer 402 are connected to low level.
The 2 input terminals D41, D42 of the row status register 403 are connected to 2 row lines, respectively, and the 2 input terminals D43, D44 of the column status register 404 are connected to 2 column lines, respectively; the 2 output terminals Q41, Q42 of the row state register 403 output row state signals I1, I2, and the 2 output terminals Q43, Q44 of the column state register 404 output column state signals I3, I4; the 2 output terminals of the row state register 403 and the 2 output terminals of the column state register 404 form a 4-bit keyboard state signal output terminal for outputting keyboard state signals I1, I2, I3 and I4.
In an embodiment, the enable input EN1 of row tri-state buffer 401 is active low, and the enable input EN2 of column tri-state buffer 402 is active high; EN1 and EN2 are both connected to the sampling pulse CK output of the oscillator 500. The receiving pulse input terminals CLK3 and CLK4 of the row state register 403 and the column state register 404 are connected to the output terminal of the sampling pulse CK of the oscillator 500, the row state register 403 latches data at the falling edge of the sampling pulse CK, and the column state register 404 latches data at the rising edge of the sampling pulse CK.
When the row tri-state buffer 401 and the column tri-state buffer 402 use the same type of tri-state buffer, for example, the tri-state buffer 74HC241 is used at the same time, the enable input of 74HC241 is active high, and therefore, a not gate needs to be added between the output of the sampling pulse CK and the enable input EN1 of the row tri-state buffer 401. Similarly, when the row state register 403 and the column state register 404 use the same type of data register, for example, the row state register 403 and the column state register 404 both use the dual D flip-flop 74HC74 to form the data register, the trigger input of 74HC74 is active at the rising edge, and therefore, a not gate needs to be added between the output terminal of the sampling pulse CK and the input terminal CLK3 of the receiving pulse of the row state register 403.
The first shift register 100, the second shift register 200, and the status code register 500 in fig. 1 constitute a scanning circuit, and the encoder 300 constitutes an encoding circuit, and a circuit diagram of an embodiment thereof is shown in fig. 3. The matrix keyboard circuit of the embodiment outputs 4 bits of status signal, so the first shift register 100 is a 4-bit binary shift register with synchronous parallel input and serial output function, and the second shift register 200 is an 8-bit binary shift register with serial input and parallel output function. The 4 parallel input ends L0-L3 of the first shift register 100 are connected to I1, I2, I3 and I4 in sequence, and the serial input end D2 of the second shift register 200 is connected to the serial output end Q1 of the first shift register 100. The clock pulse input terminal CLK1 of the first shift register 100 is connected to the first shift pulse CP1, the shift pulse input terminal CLK2 of the second shift register 200 is connected to the second shift pulse CP2, and the parallel input control terminal LD of the first shift register 100 is connected to the scan pulse CP 3.
The status code register 500 is required to register 8-bit binary data, and 8-bit data input terminals D57-D50 thereof are connected to 8-bit parallel output terminals Q27-Q20 of the second shift register 200; the receiving pulse input terminal CLK5 of the state code register 500 is connected to the scan pulse CP 3.
The 8 inputs A7-A0 of the encoder 300 are connected to the 8 data outputs Q57-Q50 of the status code register 500. The encoder 300 outputs a 4-bit binary key number determined by the scan encoding.
In the embodiment of fig. 3, the first shift register 100 may alternatively be composed of a 74HC166 or other shift registers with synchronous parallel input and serial output functions, or may alternatively be composed of edge flip-flops. The second shift register 200 may alternatively be formed of a 74HC164 or the like, which has a serial input, parallel output function, and a mid-scale integrated shift register, or may alternatively be formed of edge flip-flops. When the first shift register 100 and the second shift register 200 are formed of edge flip-flops, edge flip-flops are preferably formed of edge flip-flops. The status code register 500 is composed of edge flip-flops, preferably edge-triggered D flip-flops, for example, a select dual D flip-flop 74HC74, or a 4D flip-flop 74HC175, or an 8D flip-flop 74HC 273.
In the embodiment of fig. 3, the encoder 300 is a read-only memory. The address input ends A7-A0 of the ROM are the input ends of the encoder 300, and the data output ends D3-D0 of the ROM are the encoding output ends C3-C0 of the encoder 300.
The working principle of the matrix keyboard scanning circuit is as follows:
the scan circuit operates under the control of the scan pulse CP3, the first shift pulse CP1, and the second shift pulse CP2, and a related pulse timing chart is shown in fig. 4.
The timings of the CP1, CP2, CP3 in the embodiment satisfy the following requirements: one scan cycle for every 5 CP1 pulses. In one scanning period, the 1 st CP1 pulse period is a parallel input control period, CP3 enables effective level for parallel input of the first shift register 100, and the first shift register 100 carries out parallel input presetting under the control of the 1 st CP1 pulse; the next 4 CP1 pulse periods are shift periods, CP3 enables inactive levels for the parallel input of the first shift register 100, and the first shift register 100 performs serial shifting under the control of the CP1 pulse. In one scan period, CP2 has 4 shift pulses.
The CP1, CP2, and CP3 pulses meeting the timing requirements can be generated by various pulse dividers, and fig. 5 is a schematic diagram of a pulse circuit according to an embodiment of the present invention, which is composed of an oscillator 801, a counter 802, and a pulse divider 803. The clock pulse CP in fig. 4 is generated by an oscillator, CP is sent to the counter 802 for counting, the counter 802 is a 10-ary counter, and the 10 states (values) of the result P are sequentially P0 → P9, as shown in fig. 4. The pulse distributor 803 in an embodiment is implemented using a ROM memory, referred to herein as a pulse distribution ROM memory. An address input of the pulse allocation ROM memory is connected to a count output of the counter 802, and a 3-bit data output of the pulse allocation ROM memory outputs a CP1 pulse, a CP2 pulse, and a CP3 pulse, respectively. The write contents of the burst allocation ROM memory are shown in table 1.
TABLE 1 pulse Allocation ROM memory data sheet
The ROM memory address, i.e. the counter output, in table 1 is at least a 4-bit binary code. Generally, if the counter 802 adopts binary plus method, the P0-P9 sequentially correspond to 4-bit binary codes 0000-1001, i.e. the ROM memory address range is 0000-1001, and the storage contents of the addresses 0000-1001 are the contents corresponding to P0-P9 in Table 1.
Burst allocation ROM memories require 3-bit data output. When the matrix keyboard circuit has N-bit keyboard state signal output, the selection of R needs to satisfy 2R2 x (N +1) or more.
In fig. 2, the 4 keys of the matrix keyboard are arranged in a 2 × 2 matrix, and all the row lines and column lines are connected to the power supply + VCC through pull-up resistors. The matrix keyboard is controlled by a sampling pulse CK, and keyboard state signals I4, I3, I2 and I1 are acquired by adopting an inversion method. For example, the keyboard status signal of no key press is 1111, the keyboard status signal of S1 press is 1010, and the keyboard status signal of S1, S2 press simultaneously is 0010. The 4-bit binary code of the keyboard status signal is called a key value. The sampling pulse CK may be one of the scan pulse CP3, the first shift pulse CP1, and the second shift pulse CP2, and preferably the first shift pulse CP1 is used as the sampling pulse CK at the same time.
The method for sampling and reading key values of the matrix keyboard by the control of the sampling pulse CK comprises the following steps: at the low level of the sampling pulse CK, the row tri-state buffer 401 controls all row lines to output the low level, and the column tri-state buffer 402 outputs a high-resistance open column line; the upper 2 bits of the read column line state as the key value are sampled by the column state register 404 on the rising edge of the sampling pulse CK; at the high level of the sampling pulse CK, the column tri-state buffer 402 controls all column lines to output low level, and the row tri-state buffer 401 outputs high resistance state to open a row line; the row state register 403 samples and reads the lower 2 bits of the row line state as the key value at the falling edge of the sampling pulse CK; the above process is repeated, and the 4-bit key value output by the column status register 404 and the row status register 403 is always the latest status of the matrix keyboard.
In the method for controlling the matrix keyboard to sample and read the key value by the sampling pulse CK, the row tri-state buffer 401 requires the column state register 404 to perform data latch at the rising edge of the sampling pulse CK, the column tri-state buffer 402 to perform data latch at the high level of the sampling pulse CK, and the row state register 403 to perform data latch at the falling edge of the sampling pulse CK when the low level of the sampling pulse CK is enabled. Conversely, if the row tri-state buffer 401 is enabled at the high level of the sampling pulse CK, the column state register 404 is required to latch data at the falling edge of the sampling pulse CK, the column tri-state buffer 402 is enabled at the low level of the sampling pulse CK, and the row state register 403 latches data at the rising edge of the sampling pulse CK.
In the process of controlling the sampling read key value by the sampling pulse CK, the sampling time of the row state register 403 and the column state register 404 is just the time of performing state inversion on the column tri-state buffer 402 and the row tri-state buffer 401, and the row state register 403 or the column state register 404 under normal operation can be correctly sampled. If a certain timing margin is required, the sampling pulse CK connected to the column tri-state buffer 402 and the row tri-state buffer 401 can be delayed by connecting the sampling pulse CK to EN1 and EN2 of the row tri-state buffer 401 and the column tri-state buffer 402 through an RC delay circuit, wherein the delay time is determined by the RC delay circuit, and the delay time of the RC delay circuit is determined by the principle that the phase of the delayed sampling pulse CK is not more than 90 °; or the sampling pulse CK is buffered by several gates and then connected to EN1 and EN2 of the row tri-state buffer 401 and the column tri-state buffer 402, and the delay time is the total delay time of the several gates.
The first shift register 100 performs data input latch on the status signals I1, I2, I3 and I4 output by the matrix keyboard 400 under the control of the scan pulse CP3 and the first shift pulse CP1, and at this time, the latched data inside the first shift register 100 is referred to as a current key value. The second shift register 200 shifts the previous two current key values to the output terminal of the second shift register 200 under the control of 8 CP2 pulses in the previous two cycles, at this time, the first shifted-in 4-bit data in the output of the second shift register 200 is called as the current key value, and the last shifted-in 4-bit data is called as the previous key value.
The scan pulse CP3 latches the current key value and the previous key value output by the second shift register 200 at the output terminal of the status code register 500, and the outputs of the status code register 500 are the previous key value and the current key value.
The shift pulses of the first shift register 100 and the second shift register 200 are both edge-effective; in the shift period of one scanning period, the effective edge timings of the 4 shift pulses of CP2 are not later than the effective edge timings of the corresponding 4 shift pulses of CP 1.
The serial shift and the parallel input preset of the first shift register 100 are both controlled by the first shift pulse CP1, and the serial shift or the parallel input preset is implemented at the effective edge of the first shift pulse CP 1. In the embodiment, the first shift register 100 is selectively composed of 74HC166, and the parallel input is controlled to be enabled at low level, so that the first shift register 100 performs the parallel input presetting at the rising edge of CP1 when the scan pulse CP3 is at low level, and the first shift register 100 performs the serial shift at the rising edge of CP1 when the scan pulse CP3 is at high level.
In the embodiment, the 4-bit present key value and the 4-bit previous key value output by the data output terminal of the status code register 500 together form an 8-bit status code. The 8-bit state code is used for identifying the current state and the operation state of the matrix keyboard. For example, in the present embodiment, the status code of no key depression is 11111111; the state code of the single key press operation of the S1 key is 11111010; the state code of the pressed and maintained single key of the S1 key is 10101010; the status code of the S1 key single key release operation is 10101111; the status code of the single key press operation of the S2 key is 11110110; the state code of the single key press operation of the S4 key is 11110101; the S1 pressing operation of the S2+ S1 combination operation indicates an operation of pressing S1 after pressing S2, and the state code of this operation is 01100010 while maintaining the pressed state at S2.
The encoder 300 is used to convert the status code into a key number. In an embodiment, there are 6 valid keyboard operations and states, including:
operation 0: a single key press operation of the key S1, the key number being 0000;
operation 1: a single key of the key S2 is pressed, and the key number is 0001;
operation 2: a single key of the key S3 is pressed, with the key number 0010;
operation 3: the key S3 is in a maintenance state after the single key is pressed, and the key number is 0011;
and operation 4: after the single key of the key S4 is pressed, the combined key of the key S2 is pressed for operation, and the key number is 0100;
operation 5: the single key release operation of the key S1 has a key number 0101.
The state code and key number obtained according to the above specification are shown in code table 2:
TABLE 2 coding table
| Keyboard operation | Status code (Address) | Key number (storage data) |
| S1 Single Key Pushing | 11111010 | 0000 |
| S2 Single Key Pushing | 11110110 | 0001 |
| S3 Single Key Pushing | 11111001 | 0010 |
| S3 Single Key Press Retention | 10011001 | 0011 |
| Combined operation of S4+ S2 | 01010100 | 0100 |
| S1 Single bond Release | 10101111 | 0101 |
| Other operations or states | ******** | 1111 |
The encoder 300 is a combinational logic circuit, and the circuit is designed to satisfy the logic relationship of table 2.
The encoder 300 of an embodiment is preferably comprised of read only memory. The ROM has 8-bit address, 284 bit binary memory cells. 6 effective keyboard operations and states are 6A valid status code corresponding to 6 valid key numbers; the state codes are written as the addresses a7 to a0 of the read only memory, and the corresponding key numbers are written as the storage data in the storage cells corresponding to the 6 valid state codes. The status codes generated by the 6 valid keyboard operations and states are invalid status codes, that is, the status codes generated by the other operations or states in table 2 are invalid status codes; in the other memory cells, an invalid key number, which is a value other than the 6 valid key numbers, is written all over, and in the embodiment, the invalid key number is 1111.
The read-only memory is always operated in a data output state. When the read-only memory has chip selection control and data output buffer control functions, the chip selection control and the data output buffer control are in an effective state.
The key number in the embodiment is a 4-bit binary code. The binary digit number of the key number can be increased or decreased according to the requirement, and at the moment, only the matched read-only memory is needed to be selected. Assuming that the number of binary digits of the key number is M, the value of M should be selected to satisfy 2MGreater than or equal to the sum of the number of valid and invalid key numbers. When the matrix keyboard circuit has N-bit keyboard state signal output, the ROM needs 2 XN-bit address input and M-bit data output.
If the key operation function needs to be increased or decreased or adjusted, the table 2 is modified as needed, and the modified content is rewritten into the storage content of the read-only memory.
An edge of the scan pulse CP3 at the time when the state code register 500 latches data is referred to as a state latch edge, in the embodiment, a rising edge of the CP 3. In the embodiment, when a matrix keyboard S1 single key is pressed, after the state latching edge of the parallel input preset and the next CP3 pulse is controlled by the CP3 pulse to latch the state code in the state code register 500, in one CP3 pulse period, the coding output ends C3-C0 output the key number 0000; when the matrix keyboard S2 single key is pressed, after the state latch edge of the parallel input preset and next CP3 pulse is controlled by CP3 pulse to latch the state code in the state code register 500, the key number 0001 is output in one CP3 pulse period; when the matrix keyboard is pressed down at S4 and then pressed down at S2, the encoder 300 is pressed down at S2 combination key, and after the state latching edge of the CP3 pulse control parallel input preset and the next CP3 pulse latches the state code in the state code register 500, a CP3 pulse period outputs the key number 0100; when the matrix keyboard S1 single key is released, after the state latching edge of parallel input preset and next CP3 pulse is controlled by CP3 pulse to latch the state code in the state code register 500, the key number 0101 is output in one CP3 pulse period; it can thus be seen that when a valid key operation of the matrix keyboard is identified, the encoder 300 outputs a valid key number having a duration of one CP3 cycle width after the valid key operation.
In one embodiment, when the matrix keyboard is pressed by a single key S3, the encoder 300 outputs key number 0010 within one CP3 pulse period after the state code is latched in the state code register 500 by the state latch edge of the CP3 pulse control input preset and next CP3 pulse in parallel at S3 single key press; after the state code is latched in the state code register 500 by the state latch edge of the CP3 pulse controlling the parallel input of preset and the next CP3 pulse after the state latch edge of the next CP3 state latch edge starts and the S3 single key press sustain state ends, the encoder 300 outputs the key number 0011; it can thus be seen that when the sustained state of the matrix keyboard is identified, the duration of the encoder 300 outputting the valid key number is adapted to the duration of the sustained state.
When the state or operation of the keyboard is outside of the 6 valid keyboard operations and states described in table 2, the encoder 300 outputs an invalid key number 1111. Whether a valid key number is output or an invalid key number is output, the timing at which the encoder 300 changes the output content is the state latch edge of CP 3; in an embodiment, the moment when the encoder 300 changes the output content is the rising edge of CP 3.
The period of CP3 is the scan period of the matrix keyboard. When the scanning period of the keyboard is more than 20ms, the influence of keyboard key jitter can be effectively avoided; when the keyboard scanning period is below 100ms, keyboard operation is not missed; therefore, the period of the CP3 should be controlled to be 20-100 ms.
Since the CP3 pulse is latched to the state code register 500 at the state latch edge and the state codes are the previous state key value and the current state key value, the current key value after the key operation needs to be delayed by one CP3 pulse period to be combined as the current state key value to become the state code, and therefore, after the key is pressed, the output key number of the encoder 300 also has a delay of one CP3 pulse period. Since the key is manually operated, a time delay of several tens ms has no influence on the operation.
Fig. 6 is a circuit diagram of a keyboard state change pulse generating unit according to an embodiment of the present invention. When a valid key operation of the matrix keyboard is recognized, the encoder 300 outputs a valid key number having a duration of one CP3 cycle width from the state latch edge of CP3 to the state latch edge of the next CP3 after the valid key operation. And the device for receiving the matrix type keyboard output needs to inquire the matrix type keyboard output all the time to acquire the key number. The periodic interval of the query must be less than the period of CP 3.
The circuit shown in fig. 6 is used for judging whether the key number output by the matrix keyboard is changed or not, when the key number output by the matrix keyboard is changed, a keyboard state change pulse is output, and the receiving device for assisting the matrix keyboard receives the key number output by the matrix keyboard, for example, the keyboard state change pulse is used as an interrupt request signal of the receiving device.
The circuit shown in fig. 6 is composed of a delay buffer 601, an xor gate 602, an xor gate 603, an xor gate 604, an xor gate 605, and an or gate 606. The delay buffer 601 is composed of 4 edge flip-flops only having a trigger function, and trigger input ends of the 4 edge flip-flops are receiving pulse input ends of the delay buffer 601 and are all connected to the CP 3; the delay buffer 601 performs data latching at the state latching edge of CP 3.
The delay buffer 601 delays the 4-bit data C3 to C0 at the encoding output terminal of the encoder 300. 4 data input ends D63-D60 of the delay buffer 601 are connected to encoding output ends C3-C0 of the encoder 300, and data correspondingly output by 4 data output ends Q63-Q60 of the delay buffer 601 are C31-C01; after the signals of C31-C01 are buffered by the first stage of the delay buffer 601, the signals are delayed by one CP3 pulse period compared with the signals of C3-C0, and FIG. 7 is a waveform diagram related to the effective operation of the keyboard according to the embodiment of the present invention. And setting the interval T1 of CP3 pulse, the matrix keyboard has one effective operation, and the effective operation of the embodiment comprises the following steps: an S1 single key press, an S2 single key press, an S3 single key press, an S1 press for the combined S4+ S1 operation, an S2 press for the combined S4+ S2 operation, and an S1 single key release. At the next state latch edge of an active operation, i.e., the rising edge after the interval of the CP3 pulse T1 in FIG. 7, the encodings C3-C0 output by the encoder 300 change; in the interval T2, the encoder 300 outputs effective codes C3-C0 with a CP3 pulse period; during the intervals T3, T4, and thereafter, the codes C3-C0 output by the encoder 300 change again and enter a hold state, which may be, for example, the S1 single key pressing the following hold state, outputting an invalid key number, or the S3 single key pressing the following hold state, outputting a valid key number, until the next valid operation.
The D6 pulse in fig. 7 schematically shows whether the codes C3 to C0 outputted from the encoder 300 are in the hold state, unchanged, or changed, and the D6 pulse does not exist in the actual circuit. As shown in fig. 7, the D6 pulse is low, which schematically shows that the codes C3 to C0 outputted from the encoder 300 are in a hold state and do not change; the D6 pulse is high, which schematically indicates that the encoder 300 outputs one cycle of valid codes C3-C0. Q6 in FIG. 7 reflects the variation of C31-C01, and it is clear that Q6 is delayed by one CP3 pulse period from D6. Also, the Q6 pulse is not present in an actual circuit.
In fig. 7, the codes C3 to C0 outputted from the encoder 300 are in a hold state, are unchanged, or are changed, and are actually completed by a logic circuit including a 4-bit delay buffer 601, an exclusive or gate 602, an exclusive or gate 603, an exclusive or gate 604, an exclusive or gate 605, and an or gate 606. The 4 exclusive or gates correspond to 1 bit of the encoding output terminals C3 to C0 of the encoder 300, and input signals of the 4-bit delay buffer 601 are input and output signals of the 4-bit delay buffer. For example, the two input signals of the xor gate 602 are C0 and C01, respectively, and C01 is delayed from C0 by one CP3 pulse period, so that when C0 changes, the xor gate 602 outputs a positive pulse of 1 CP3 pulse period width; when C0 is a CP3 pulse period width change signal, xor-gate 602 outputs a positive pulse of 2 CP3 pulse period widths. The xor gate 603, the xor gate 604, and the xor gate 605 respectively determine whether or not C1 to C3 have changed, and the principle is the same as that of determining whether or not C0 has changed. The output ends of the exclusive-or gate 602, the exclusive-or gate 603, the exclusive-or gate 604 and the exclusive-or gate 605 are respectively connected to the input end of the or gate 606, and the or gate 606 is used for comprehensively judging whether the C0-C3 change or not, so long as the C0-C3 change, the or gate 606 outputs a keyboard state change pulse F, and the pulse is a positive pulse.
In an embodiment, the delay buffer 601 selects the rising edge triggered 8D flip-flop 74HC 273.
Other schemes can be adopted for the delay buffer 601, for example, an RC circuit is adopted, and 4 RC circuits are used for respectively delaying C0-C3; if the delay time of the RC circuit is less than a CP3 pulse period, when the encoder 300 outputs effective codes C3-C0 of one period, a keyboard state change pulse is generated at the beginning of outputting the effective codes C3-C0 and at the end of outputting the effective codes C3-C0, and the width of the keyboard state change pulse is equal to the delay time of the RC circuit; if the delay time of the RC circuit is more than or equal to one CP3 pulse period, when the encoder 300 outputs the effective codes C3-C0 of one period, a keyboard state change pulse is generated at the beginning of outputting the effective codes C3-C0, and the pulse width is more than or equal to 2 CP3 pulse periods. The delay time of the RC circuit is required to not exceed 2 CP3 pulse periods in order to avoid false negatives.
In the circuit, the positioning of single key operation, combined key operation and keyboard maintenance state operation is controlled and converted into a state code with the same binary length by 2 pulses meeting specific time sequence requirements, and the state code is processed in a uniform coding mode, wherein the single key operation, the combined key operation and the keyboard maintenance state operation are only reflected on the difference of the state code; if the key operation function needs to be increased or decreased or the key operation function needs to be adjusted, the structure of the keyboard scanning circuit does not need to be modified, and the encoder 300 only needs to be updated according to the increased or decreased state code table, namely, the storage content of the read-only memory is rewritten and updated. The circuit of the invention does not use microcontrollers such as a singlechip and an ARM, does not need running programs, and has reliable work.
Claims (6)
1. A matrix keyboard inversion method scanning method is characterized in that: of said matrix keyboardXRoot and row lines andYthe root column lines are connected with pull-up resistors and are controlled by sampling pulsesXRoot and row lines andYthe root column lines are alternately in a low level state; will be provided withXWhen the root row line is at low levelYRoot column line state latch getYA bit-column status signal is generated,Ywith root line at low levelXRoot row line state latch getXA bit line status signal;Xbit line status signal andYthe bit-line state signals together constituting the outputNA keyboard status signal; the above-mentionedN＝X＋Y；
Said control being by sampling pulsesXRoot and row lines andYthe root column line is alternately in a low level state and is realized by a row tri-state buffer and a column tri-state buffer; the row lines of all the key matrixes are respectively connected to the output ends of the row tri-state buffers, and the column lines of all the key matrixes are respectively connected to the output ends of the column tri-state buffers; all input ends of the row tri-state buffer and the column tri-state buffer are connected to a low level;
the device is toXWhen the root row line is at low levelYRoot column line state latch getYA bit-column status signal is generated,Ywith root line at low levelXRoot row line state latch getXThe bit line state signal is realized by a line state register and a column state register; the row lines of all the key matrixes are respectively connected to the input end of the row state register, and the column lines of all the key matrixes are respectively connected to the input end of the column state register;
the above-mentionedNThe bit keyboard state signal is sent to a circuit consisting of a first shift register, a second shift register, a state code register and an encoder for encoding; the matrix keyboard scanning circuit consists of a matrix keyboard scanning circuit, a first shift register, a second shift register, a state code register and an encoder, and is synchronously controlled by a scanning pulse, a first shift pulse and a second shift pulse; the matrix keyboard circuit comprisesXRoot and row lines andYa key matrix of a root row line, a row three-state buffer, a column three-state buffer, a row state register and a column state register;
the first shift register hasNBit synchronous parallel input and serial output functions; the second shift register has serial input and 2 functionNA bit parallel output function; of a first shift registerNBit parallel input terminal connected toNA keyboard status signal output terminal; the serial input end of the second shift register is connected to the serial output end of the first shift register; the clock pulse input end of the first shift register is connected to a first shift pulse, the shift pulse input end of the second shift register is connected to a second shift pulse, and the parallel input control end of the first shift register is connected to a scanning pulse;
the status code register is 2NA bit binary register; 2 register of state codeN2 strap for connecting bit data input to second shift registerNA bit parallel output; the receiving pulse input end of the state code register is connected to the scanning pulse;
the encoder has 2 piecesNBit-coded input, said 2 inN2 in which the bit-encoded input is connected to the status code registerNA bit data output terminal.
2. The matrix keyboard inversion scanning method of claim 1, wherein: enabling the row tri-state buffer to be effective at the low level of the sampling pulse, and enabling the column tri-state buffer to be effective at the high level of the sampling pulse; the column state register latches data at a rising edge of the sampling pulse, and the row state register latches data at a falling edge of the sampling pulse.
3. The matrix keyboard inversion scanning method of claim 1, wherein: enabling the row tri-state buffer to be effective at the high level of the sampling pulse, and enabling the column tri-state buffer to be effective at the low level of the sampling pulse; the column state register latches data at a falling edge of the sampling pulse, and the row state register latches data at a rising edge of the sampling pulse.
4. According to any one of claims 2-3The matrix keyboard inversion method scanning method is characterized in that: the shift pulse edges of the first shift register and the second shift register are effective; of the second shift pulseNThe effective edge of each shift pulse is not later than that of the first shift pulseNThe active edge time of each shift pulse.
5. The matrix keyboard inversion scanning method of any one of claims 2-3, wherein: the time sequence of the scanning pulse, the first shift pulse and the second shift pulse meets the following requirements: every 1 constructionNThe first shift pulse is one scanning period;
in a scanning period, during the 1 st first shift pulse period, the scanning pulse enables the effective level for the parallel input of the first shift register; one scan period, 1 st first shift pulse period laterNDuring a period of the first shift pulse, the scan pulse is an enable invalid level for the parallel input of the first shift register; in one scanning period, the second shift pulse hasNA shift pulse.
6. The matrix keyboard inversion scanning method of any one of claims 2-3, wherein: 2 register of the state codeNBit data output 2 inNA status code of the bit; the state code consists of a valid state code and an invalid state code; the key number output by the encoder consists of an effective key number and an ineffective key number; the effective state codes are generated by the operation or the state of an effective keyboard, and corresponding effective key numbers are correspondingly output when the encoder inputs each effective state code; the invalid state code is generated by invalid keyboard operation or state, and when the encoder inputs all the invalid state codes, the encoder correspondingly outputs invalid key numbers;
the encoder hasMA bit key number output terminal for outputting a bit key number,Mthe value should be selected to satisfy 2 M Greater than or equal to the sum of the number of valid and invalid key numbers.
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