CN108809322B

CN108809322B - Independent keyboard scanning and coding method

Info

Publication number: CN108809322B
Application number: CN201810591960.8A
Authority: CN
Inventors: 文定都; 凌云; 王兵
Original assignee: Hunan University of Technology
Current assignee: Hunan University of Technology
Priority date: 2016-01-05
Filing date: 2016-01-05
Publication date: 2022-01-21
Anticipated expiration: 2036-01-05
Also published as: CN105471439A; CN105471439B; CN108809322A

Abstract

A stand-alone keyboard scanning and coding method comprises outputting N-bit keyboard state signals by a stand-alone keyboard with N keys; scanning pulses to carry out data latching and selection on the N-bit keyboard state signals to obtain current state key values and previous state key values; the clock pulse carries out state latching on the current state key value and the previous state key value to obtain a 2 multiplied by N state code; the state code is coded and the key number is output, and the state code is realized by a circuit consisting of an independent keyboard, a first buffer register, a second buffer register, a state code register, a coder and a data selection unit. According to the method, if the key operation function needs to be increased or decreased or adjusted, the circuit structure does not need to be modified, and the encoding content of the encoder only needs to be changed according to the corresponding relation between the increased or decreased state codes and the key numbers. The method does not need to write and run programs and works reliably.

Description

Independent keyboard scanning and coding method

The invention relates to a separated application, which has an original application number of 201610003246.3 and an application date of 2016, 1 and 5 and is named as an independent keyboard scanning and coding circuit.

Technical Field

The invention relates to a scanning and positioning method of a keyboard, in particular to a scanning and coding method of an independent keyboard.

Background

With the continuous development of embedded technology, various electronic products generally adopt a microcontroller as a control core and a keyboard as a main input device, and are widely applied.

The existing keyboard scanning is mainly controlled by a microcontroller, and is performed by running a program in the microcontroller, so that the program runs off due to interference, and the scanning program cannot work normally.

The invention patent with application number CN201010153560.2, "a method for fast scanning and positioning matrix keyboard", adopts a mode of keyboard interrupt triggering to enter the scanning and positioning process of keyboard, adopts a method of repeating the keyboard scanning step for many times to judge whether the key is valid, and makes state judgment on the obtained key value; if the multiple sampling states are the same, the key value is in a stable state and is valid; if the multiple sampling states are different, the key value is invalid. The single key operation or the combined key operation needs to be judged separately, if the single key operation is carried out, the single key processing mode is entered; if the operation is a combination key operation, a combination key processing mode is entered. The method disclosed in the patent solves the problems of wrong keys, continuous key touch and other errors caused by keyboard shaking due to the mechanical characteristics of the keyboard, and the problem of supporting combined keys and repeated keys. But the single key operation and the combined key operation of the method need to be processed respectively; a keyboard operation function of executing effective operation after a certain period of time of maintaining the keyboard state is not considered; when the key operation function is increased or decreased or adjusted, the structure of the keyboard scanning and positioning program needs to be modified.

Disclosure of Invention

In order to solve the technical problems of the existing keyboard scanning and positioning method, the invention provides a stand-alone keyboard scanning and encoding method, which comprises the steps that a stand-alone keyboard with N keys outputs N-bit keyboard state signals; scanning pulses to carry out data latching and selection on the N-bit keyboard state signals to obtain current state key values and previous state key values; the clock pulse carries out state latching on the current state key value and the previous state key value to obtain a 2 multiplied by N state code; the status code is encoded and the key number is output. The N-bit keyboard state signals and the N keys meet one-to-one correspondence. The N-bit keyboard state signal is a level signal.

The scanning pulse carries out data latch and selection on the N-bit keyboard state signals to obtain the present state key value and the previous state key value by controlling the output ends of the 2 buffer registers to alternately output the present state key value and the previous state key value by the high level and the low level of the scanning pulse; the high and low levels of the scanning pulse alternately output the present state key value and the previous state key value to the output ends of the 2 buffer registers for data selection sorting and combination, so that the present state key value is in the front and the previous state key value is in the back; or, the high and low levels of the scanning pulse alternately output the present state key value and the previous state key value to the output ends of the 2 buffer registers for data selection sorting and combination, so that the present state key value is behind the previous state key value.

The state code consists of an effective state code and an ineffective state code and is used for identifying the current state and the operation state of the independent keyboard; the key number is composed of a valid key number and an invalid key number; the effective state code is generated by the operation or the state of an effective keyboard, and a corresponding effective key number is correspondingly output; the invalid state code is generated by invalid keyboard operation or state and correspondingly outputs an invalid key number.

The effective keyboard operation comprises single-key pressing operation, single-key releasing operation, single-key pressing maintaining operation and combined key operation; the combined key operation refers to the operation that after a single key is pressed down, other keys are pressed down; the invalid keyboard operation is an operation other than the valid keyboard operation. The key number is M bits, and the selection of the M value should satisfy 2^MGreater than or equal to the sum of the number of valid and invalid key numbers.

The encoding of the state code and the output of the key number are realized by an encoder. When all invalid state codes are input by the encoder, the invalid key number is correspondingly output, and the invalid key number is a value except all valid key numbers. Further, the encoder is a read-only memory; the key operation function is increased or decreased or adjusted by modifying the storage content of the read-only memory.

The scanning pulse carries out data latching and selection on the N-bit keyboard state signal to obtain a present state key value and a previous state key value, and the present state key value and the previous state key value are realized by the first buffer register, the second buffer register and the data selection unit. The first buffer register and the second buffer register are both N-bit binary registers; the N-bit data input end of the first buffer register is sequentially connected to the N-bit keyboard state signal output end, the N-bit data input end of the second buffer register is sequentially connected to the N-bit keyboard state signal output end, and the pulse receiving input ends of the first buffer register and the second buffer register are connected to scanning pulses; the high and low levels of the scanning pulse control the N-bit data output ends of the first buffer register and the second buffer register to alternately output the appearance key value and the previous key value. The data selection unit is provided with a first path of N-bit data input end, a second path of N-bit data input end and a 2 multiplied by N-bit data output end; the first path of N-bit data input end is sequentially connected to the N-bit data output end of the first buffer register, and the second path of N-bit data input end is sequentially connected to the N-bit data output end of the second buffer register. The data selection unit is also provided with a data selection signal end; the data selection signal end is connected to the scanning pulse; in the 2 × N bit data output of the data selection unit, when the scanning pulse is at a low level, the first path of N bit data is before, and the second path of N bit data is after; when the scanning pulse is at a high level, the first path of N-bit data is behind, and the second path of N-bit data is in front; or, in the 2 × N bit data output of the data selection unit, when the scan pulse is at a low level, the first path of N bit data is behind, and the second path of N bit data is in front; when the scanning pulse is at a high level, the first path of N-bit data is in front, and the second path of N-bit data is behind. The output of the data selection unit can keep the sequence of the current state key value before and the previous state key value after constant, or the sequence of the current state key value after and the previous state key value before constant.

The clock pulse carries out state latching on the current state key value and the previous state key value to obtain a 2 multiplied by N state code which is realized by a state code register. The state code register is a 2 XN bit binary register; the 2 XN bit data input end of the state code register is connected to the 2 XN bit data output end of the data selection unit, and the receiving pulse input end is connected to the clock pulse; the status code register latches data at a status latch edge of the clock pulse. The state latching edge of the clock pulse is the rising edge of the clock pulse; the state of the clock pulse latches an edge or is the falling edge of the clock pulse. The scanning pulse is a halved frequency signal of the clock pulse; in the clock pulse, an effective trigger edge for controlling the inversion of the scan pulse is called a state scan edge, and the other edge is a state latch edge.

The first buffer register, the second buffer register and the state code register are composed of edge-triggered D triggers. The period of the clock pulse is 20-100 ms. The N bits, 2 XN bits and M bits all refer to binary bit data.

The independent keyboard scanning and encoding method is realized by an independent keyboard scanning and encoding circuit. The independent keyboard, the first buffer register, the second buffer register, the data selection unit and the encoder form an independent keyboard scanning and encoding circuit.

Further, when the output key number is changed, a keyboard state change pulse is output. The independent keyboard scanning and encoding circuit further comprises a keyboard state change pulse generating unit, wherein the keyboard state change pulse is output by the keyboard state change pulse generating unit consisting of an OR gate, an M-bit delay buffer and M exclusive-OR gates; the M-bit delay buffer is used for respectively carrying out signal delay on the M-bit key numbers output by the independent keyboard; the inputs of the M exclusive-OR gates are input signals and output signals of the M-bit delay buffer respectively; the outputs of the M exclusive-OR gates are respectively connected to the input ends of the OR gates; the output end of the OR gate outputs a keyboard state change pulse.

The independent keyboard scanning and encoding circuit further comprises an oscillator; the oscillator outputs a clock pulse and a scan pulse.

The invention has the beneficial effects that: the positioning of single key operation, combined key operation and keyboard maintenance state operation is converted into state codes with the same binary length by clock pulse and scanning pulse control, and the state codes are processed by adopting a uniform coding mode, wherein the single key operation, the combined key operation and the keyboard maintenance state operation are only reflected on the difference of the state codes; if the key operation function needs to be increased or decreased or the key operation function needs to be adjusted, the circuit structure does not need to be modified, and the encoding content of the encoder only needs to be changed according to the corresponding relation between the increased or decreased state code and the key number, namely the storage content written into the read-only memory is modified again. The method does not use microcontrollers such as a single chip microcomputer and an ARM, does not need running programs, and works reliably.

Drawings

FIG. 1 is a functional block diagram of a stand alone keyboard scanning and encoding circuit;

FIG. 2 is a circuit diagram of a stand alone keyboard according to an embodiment of the present invention;

FIG. 3 is a scan positioning circuit diagram of an embodiment of the present invention;

FIG. 4 is a circuit diagram of a data selection unit according to an embodiment of the present invention;

FIG. 5 is a waveform diagram of clock pulses and scan pulses for an embodiment of the present invention;

FIG. 6 is a circuit diagram of a keyboard state change pulse generating unit according to an embodiment of the present invention;

FIG. 7 is a waveform diagram illustrating the operation of the keyboard according to the present invention.

Detailed Description

The invention is further described below with reference to the accompanying drawings.

Fig. 1 is a schematic block diagram of a stand-alone keyboard scanning and encoding circuit, which is composed of a stand-alone keyboard 400, a first buffer register 101, a second buffer register 102, a status code register 200, an encoder 300, and a data selection unit 500.

Fig. 2 is a circuit diagram of a stand-alone keyboard 400 of an embodiment of the present invention, having 4 keys, which is composed of a key S1, a key S2, a key S3, a key S4, and a pull-up resistor R1, a pull-up resistor R2, a pull-up resistor R3, and a pull-up resistor R4 connected to a power supply + VCC. The 4 output ends of the independent keyboard 400 respectively output status signals I1, I2, I3 and I4 of a key S1, a key S2, a key S3 and a key S4 in a one-to-one correspondence mode, and when the key is pressed down, the status signal of the corresponding output end is at a low level; when the key is not pressed, the state signal of the corresponding output end is high level.

The first buffer register 101, the second buffer register 102, the status code register 200, the encoder 300, and the data selection unit 500 in fig. 1 form a scan positioning circuit, and an embodiment of the circuit diagram is shown in fig. 3. The status signal output by the independent keyboard circuit has 4 bits, therefore, the first buffer register 101 and the second buffer register 102 both require to register 4-bit binary data, the 4 data input terminals D10-D13 of the first buffer register 101 are sequentially connected to I1, I2, I3 and I4, and the 4 data input terminals D14-D17 of the second buffer register 102 are also sequentially connected to I1, I2, I3 and I4.

The data selection unit 500 is used for implementing selection, sorting and combination of two paths of input data. In the embodiment, 1 of the two input data is 4-bit data J, wherein the J comprises J3, J2, J1 and J0; the other 1 path is 4-bit data K, wherein the K comprises K3, K2, K1 and K0; the 1-way 8-bit output data is L. The data selection unit 500 has the function that 8-bit output data L has two sorting combinations, wherein one sorting combination is that 4-bit data J is in front and 4-bit data K is in back, namely output L7-L0 are sequentially J3, J2, J1, J0, K3, K2, K1 and K0; the other sort combination is that 4-bit data K is in front of the data J and 4-bit data J is behind the data J, namely the output L7-L0 is K3, K2, K1, K0, J3, J2, J1 and J0 in sequence; the two ordering combinations are controlled by a data select signal S.

The data selection unit 500 may be implemented using a data selector, a tri-state buffer, or in other ways. Fig. 4 is a schematic diagram of an embodiment of a data selecting unit 500, which is composed of 2 four-to-1-out-of-2 data selectors 501 and 502, and the data selecting signals S of the selectors 501 and 502 are both connected to the scan pulse CP 2. When the CP2 is at a low level, the four-from-1 data selectors 501 and 502 select channel 0, i.e., L7-L0 are equal to K3, K2, K1, K0, J3, J2, J1 and J0; when the CP2 is at high level, the four-from-1 data selectors 501 and 502 select channel 1, i.e., L7-L0 are equal to J3, J2, J1, J0, K3, K2, K1, and K0.

The status code register 200 is required to register 8-bit binary data, and 8-bit data input terminals D27-D20 thereof are connected to 8-bit data output terminals L7-L0 of the data selecting unit 500; the 8 inputs A7-A0 of the encoder 300 are connected to the 8 data outputs Q27-Q20 of the status code register 200. The encoder 300 outputs a 4-bit binary key number determined by the scan location.

In the embodiment of fig. 3, the first buffer register 101, the second buffer register 102 and the status code register 200 are all composed of edge flip-flops, preferably edge flip-flops, e.g., dual D flip-flops 74HC74, 4D flip-flops 74HC175 and 8D flip-flops 74HC 273. The trigger input ends of the 4 edge triggers in the first buffer register 101 are connected together to form a pulse receiving input end which is connected to the scanning pulse CP2, and the falling edge carries out data latch; the trigger input ends of the 4 edge triggers in the second buffer register 102 are connected together to form a pulse receiving input end which is connected to the scanning pulse CP2, and the rising edge latches data; the trigger inputs of the 8 edge flip-flops of the status code register 200 are connected together to form a receive pulse input, which is connected to the clock pulse CP1, and the rising edge latches the data.

In the embodiment of fig. 3, the first buffer register 101, the second buffer register 102, and the status code register 200 are all the 8D flip-flop 74HC273 triggered by the rising edge, and since the first buffer register 101 requires the falling edge for data latching, the scan pulse CP2 needs to be inverted by a not gate and then connected to the pulse receiving input terminal of the first buffer register 101; in addition, in order to disable the zero clearing function of the 74HC273, it is ensured that the first buffer register 101, the second buffer register 102, and the status code register 200 have only a trigger function.

In the embodiment of fig. 3, the encoder 300 is a read-only memory. The address input ends A7-A0 of the ROM are the input ends of the encoder 300, and the data output ends D3-D0 of the ROM are the encoding output ends C3-C0 of the encoder 300.

In the embodiment, an oscillator for generating the clock pulse CP1 and the scan pulse CP2 is not shown, the oscillator is a multivibrator and outputs the clock pulse CP1 and the scan pulse CP2, the period of the clock pulse CP1 is 20-100 ms, the scan pulse CP2 is a halved frequency signal of the clock pulse CP1, and the waveforms of the CP1 and CP2 are shown in FIG. 5. The clock pulses CP1 and the scan pulses CP2 may also be provided by circuits or devices other than the stand-alone keyboard scan and encode circuits.

The principle of the independent keyboard scanning and encoding method is as follows:

under the control of the scan pulse CP2, the first buffer register 101 and the second buffer register 102 alternately latch the data of the status signals I1, I2, I3 and I4 output by the independent keyboard; since the output of the buffer register that latches the data most recently is referred to as the current key value and the output of the buffer register that latches the data a little before is referred to as the previous key value, the first and second buffer registers 101 and 102 alternately output the current key value and the previous key value under the control of the scan pulse CP 2.

With reference to fig. 3 and 5 of the embodiment, after the scan pulse CP2 falls, in the low level state of the scan pulse CP2, the current state key values output by the first buffer register 101 are connected to the input terminals J3, J2, J1, J0 of the data selecting unit 500, the previous state key values output by the second buffer register 102 are connected to the input terminals K3, K2, K1, K0 of the data selecting unit 500, and at this time, the data selecting signal S is connected to the scan pulse CP2 and is at a low level, the outputs L7 to L0 of the data selecting unit 500 are equal to K3, K2, K1, K0, J3, J2, J1, J0, that is the previous state key value and the current state key value is at the next; after the rising edge of the scan pulse CP2, in the high state of the scan pulse CP2, the previous state key values output by the first buffer register 101 are connected to the input terminals J3, J2, J1, and J0 of the data selecting unit 500, the present state key values output by the second buffer register 102 are connected to the input terminals K3, K2, K1, and K0 of the data selecting unit 500, and at this time, the data selecting signal S is connected to the scan pulse CP2 and is at a high level, and the outputs L7 to L0 of the data selecting unit 500 are equal to J3, J2, J1, J0, K3, K2, K1, and K0, and similarly, the previous state key values are before and the present state key values are behind.

The scan pulse CP2 forms a short indeterminate state when the first buffer register 101 and the second buffer register 102 are controlled to alternately latch and output the previous-state key value and the current-state key value, and the data selection unit 500 performs data selection sorting and combining. The effect of the state code register 200 is to eliminate the effect of this indeterminate state.

The inputs of the status code register 200 are the previous-state key value and the current-state key value output by the data selecting unit 500, and the outputs are the previous-state key value and the current-state key value. An edge of the clock pulse CP1 at the time when the state code register 200 performs data latch is referred to as a state latch edge, in the embodiment, a rising edge of CP 1; the scan pulse CP2 is a divided-by-two signal of the clock pulse CP1, and an effective trigger edge of the clock pulse CP1 for controlling the inversion of the scan pulse CP2 is called a state scan edge; in the embodiment, the state scan edge is the falling edge of the clock pulse CP1, that is, the time when the first buffer register 101, the second buffer register 102, and the data selecting unit 500 latch and output the previous state key value and the current state key value is at the falling edge of the clock pulse CP1, so that the previous state key value and the current state key value output by the data selecting unit 500 have already entered a steady state at the rising edge of the clock pulse CP1, and the influence of the uncertain state is eliminated.

If the clock pulse CP1 controls the effective trigger edge turned by the scan pulse CP2 to be a falling edge, the clock pulse CP1 controls the ineffective trigger edge turned by the scan pulse CP2 to be a rising edge; if the clock CP1 controls the active edge of the scan CP2 to flip to be a rising edge, the clock CP1 controls the inactive edge of the scan CP2 to flip to be a falling edge. The invalid trigger edge of the clock pulse CP1 for controlling the scan pulse CP2 to overturn is called a state latch edge; in an embodiment, the state scan edge is the falling edge of clock pulse CP1 and the state latch edge is the rising edge of clock pulse CP 1.

The 4-bit present key value and the 4-bit previous key value output by the data output terminal of the status code register 200 together form an 8-bit status code. The 8-bit state code is used for identifying the current state and the operation state of the independent keyboard. For example, in the present embodiment, the status code of no key depression is 11111111; the status code of the single key press operation of the S1 key is 11111110; the state code of S1 key single key press and maintenance is 11101110; the state code of the S1 key single-key release operation is 11101111; the state code of the single key press operation of the S2 key is 11111101; the state code of the single key press operation of the S4 key is 11110111; the S1 pressing operation of the S2+ S1 combination operation indicates an operation of pressing S1 after pressing S2 first, and the status code of this operation is 11011100 while maintaining the pressed state at S2.

The encoder 300 is used to convert the status code into a key number. In an embodiment, there are 7 valid keyboard operations and states, including:

operation 0: a single key press operation of the key S1, the key number being 0000;

operation 1: a single key of the key S2 is pressed, and the key number is 0001;

operation 2: a single key of the key S3 is pressed, with the key number 0010;

operation 3: the key S3 is in a maintenance state after the single key is pressed, and the key number is 0011;

and operation 4: after the single key of the key S4 is pressed, the combined key of the key S1 is pressed for operation, and the key number is 0100;

operation 5: after the single key of the key S4 is pressed, the combined key of the key S2 is pressed for operation, and the key number is 0101;

operation 6: the single key release operation of the key S1 has a key number of 0110.

The state code and key number obtained according to the above specification are shown in code table 1.

The encoder 300 is a combinational logic circuit, and the circuit is designed to satisfy the logic relationship of table 1.

The encoder 300 of an embodiment is preferably comprised of read only memory. The ROM has 8-bit address, 2⁸4 bit binary memory cells. 7 effective keyboard operation and states have 7 effective state codes corresponding to 7 effective key numbers; the state codes are written as the addresses a7 to a0 of the read only memory, and the corresponding key numbers are written as the storage data in the storage cells corresponding to the 7 valid state codes. The status codes generated by the 7 valid keyboard operations and statuses are invalid status codes, that is, the status codes generated by the other operations or statuses in table 1 are invalid status codes; in the other memory cells, an invalid key number, which is a value other than 7 valid key numbers, is written all over, and in the embodiment, the invalid key number is 1111.

TABLE 1 coding table

Keyboard operation	Status code (Address)	Key number (storage data)
			S1 Single Key Pushing	11111110	0000
S2 Single Key Pushing	11111101	0001
			S3 Single Key Pushing	11111011	0010
S3 Single Key Press Retention	10111011	0011
			Combined operation of S4+ S1	01110110	0100
Combined operation of S4+ S2	01110101	0101
			S1 Single bond Release	11101111	0110
Other operations or states	********	1111

The read-only memory is always operated in a data output state. When the read-only memory has chip selection control and data output buffer control functions, the chip selection control and the data output buffer control are in an effective state.

The key number in the embodiment is a 4-bit binary code. The binary digit number of the key number can be increased or decreased according to the requirement, and at the moment, only the matched read-only memory is needed to be selected. Assuming that the number of binary digits of the key number is M, the value of M should be selected to satisfy 2^MGreater than or equal to the sum of the number of valid and invalid key numbers. When the independent keyboard has N-bit keyboard state signal output, the read-only memory needs 2 XN-bit address input and M-bit data output.

If the key operation function needs to be increased or decreased or adjusted, the table 1 is modified as needed, and the modified content is rewritten into the storage content of the read-only memory.

In the embodiment, when the single key of the independent keyboard S1 is pressed, the encoder 300 starts from the state latch edge of the clock pulse CP1 after the single key of S1 is pressed until the state latch edge of the next clock pulse CP1, and the encoding output terminals C3-C0 output the key number 0000; when the single key of the independent keyboard S2 is pressed, the encoder 300 outputs the key number 0001 from the state latch edge of the clock pulse CP1 after the single key of S2 is pressed to the state latch edge of the next clock pulse CP 1; when the independent keyboard is pressed S4 first and then S1 is pressed, the encoder 300 outputs a key number 0100 from the state latch edge of the clock pulse CP1 after the combination key is pressed S1 to the state latch edge of the next clock pulse CP 1; when the independent keyboard S1 releases the single key, the encoder 300 outputs the key number 0110 from the state latch edge of the clock pulse CP1 after the S1 single key releases to the state latch edge of the next clock pulse CP 1; therefore, it can be seen that when a valid key operation of the stand-alone keyboard is recognized, the encoder 300 outputs a valid key number having a duration of one cycle width of the clock pulse CP1 from the state latch edge of the clock pulse CP1 after the valid key operation to the state latch edge of the next clock pulse CP 1.

In the embodiment, when the single key of the independent keyboard S3 is pressed, the encoder 300 outputs the key number 0010 from the state latch edge of the clock pulse CP1 after the single key is pressed at S3 until the state latch edge of the next clock pulse CP 1; the encoder 300 outputs a key number 0011 from the state latch edge of the next clock pulse CP1 to the state latch edge of the next clock pulse CP1 after the end of the S3 single-key-press holding state; it can thus be seen that when a sustained state of the stand-alone keyboard is identified, the duration of the encoder 300 outputting a valid key number is adapted to the duration of the sustained state.

When the state or operation of the keyboard is outside the 7 valid keyboard operations and states described in table 1, the encoder 300 outputs an invalid key number 1111. Whether a valid key number is output or an invalid key number is output, the moment when the encoder 300 changes the output content is the state latch edge of the clock pulse CP 1; in an embodiment, the moment at which the encoder 300 changes the output content is the rising edge of the clock pulse CP 1.

The period of clock pulse CP1 is the scan period of the free standing keyboard. When the scanning period of the keyboard is more than 20ms, the influence of keyboard key jitter can be effectively avoided; when the keyboard scanning period is below 100ms, keyboard operation is not missed; therefore, the period of the clock pulse CP1 should be controlled to be 20-100 ms.

Fig. 6 is a circuit diagram of a keyboard state change pulse generating unit according to an embodiment of the present invention. When a valid key operation of the independent keyboard is recognized, the encoder 300 outputs a valid key number having a duration of one clock pulse CP1 cycle width from the state latch edge of the clock pulse CP1 after the valid key operation to the state latch edge of the next clock pulse CP 1. And the device for receiving the output of the independent keyboard inquires the output of the independent keyboard at any time to acquire the key number. The period interval of the inquiry must be smaller than the period of the clock pulse CP 1.

The circuit shown in fig. 6 is used for judging whether the key number output by the independent keyboard is changed or not, outputting a keyboard state change pulse when the key number output by the independent keyboard is changed, and assisting the receiving device of the independent keyboard to receive the key number output by the independent keyboard, for example, using the keyboard state change pulse as an interrupt request signal of the receiving device.

The circuit shown in fig. 6 is composed of a delay buffer 601, an xor gate 602, an xor gate 603, an xor gate 604, an xor gate 605, and an or gate 606. The delay buffer 601 is composed of 4 edge flip-flops only having a trigger function, and trigger input ends of the 4 edge flip-flops are receiving pulse input ends of the delay buffer 601 and are all connected to an output end of a clock pulse CP1 of the oscillator 500; the delay buffer 601 performs data latching at the state latching edge of the clock pulse CP 1.

The delay buffer 601 delays the 4-bit data C3 to C0 at the encoding output terminal of the encoder 300. 4 data input ends D63-D60 of the delay buffer 601 are connected to encoding output ends C3-C0 of the encoder 300, and data correspondingly output by 4 data output ends Q63-Q60 of the delay buffer 601 are C31-C01; after the signals of C31-C01 are buffered by the first stage of the delay buffer 601, the signals are delayed by one clock pulse CP1 period compared with the signals of C3-C0, and FIG. 7 is a waveform diagram related to the effective operation of the keyboard according to the embodiment of the present invention. At the T1 interval of the clock pulse CP1, there is one active operation of the standalone keyboard, and the active operations of the embodiments include: an S1 single key press, an S2 single key press, an S3 single key press, an S1 press for the combined S4+ S1 operation, an S2 press for the combined S4+ S2 operation, and an S1 single key release. At the next state latch edge of an active operation, i.e., the rising edge after the interval of the clock pulse CP1T1 in FIG. 7, the codes C3-C0 output by the encoder 300 change; in the interval T2, the encoder 300 outputs effective codes C3-C0 of one period; during the intervals T3, T4, and thereafter, the codes C3-C0 output by the encoder 300 change again and enter a hold state, which may be, for example, the S1 single key pressing the following hold state, outputting an invalid key number, or the S3 single key pressing the following hold state, outputting a valid key number, until the next valid operation.

The D6 pulse in fig. 7 schematically shows whether the codes C3 to C0 outputted from the encoder 300 are in the hold state, unchanged, or changed, and the D6 pulse does not exist in the actual circuit. As shown in fig. 7, the D6 pulse is low, which schematically shows that the codes C3 to C0 outputted from the encoder 300 are in a hold state and do not change; the D6 pulse is high, which schematically indicates that the encoder 300 outputs one cycle of valid codes C3-C0. The Q6 in fig. 7 reflects the change of C31-C01, and it is obvious that Q6 is delayed by one clock pulse CP1 period from D6. Also, the Q6 pulse is not present in an actual circuit.

In fig. 7, the codes C3 to C0 outputted from the encoder 300 are in a hold state, are unchanged, or are changed, and are actually completed by a logic circuit including a 4-bit delay buffer 601, an exclusive or gate 602, an exclusive or gate 603, an exclusive or gate 604, an exclusive or gate 605, and an or gate 606. The 4 exclusive or gates correspond to 1 bit of the encoding output terminals C3 to C0 of the encoder 300, and input signals of the 4-bit delay buffer 601 are input and output signals of the 4-bit delay buffer. For example, two input signals of the xor gate 602 are C0 and C01, respectively, and C01 is delayed from C0 by one clock pulse CP1 period, so that when C0 changes, the xor gate 602 outputs a positive pulse of 1 clock pulse CP1 period width; when C0 is a signal with a cycle width of one clock pulse CP1, the xor-gate 602 outputs a positive pulse with a cycle width of 2 clock pulses CP 1. The xor gate 603, the xor gate 604, and the xor gate 605 respectively determine whether or not C1 to C3 have changed, and the principle is the same as that of determining whether or not C0 has changed. The output ends of the exclusive-or gate 602, the exclusive-or gate 603, the exclusive-or gate 604 and the exclusive-or gate 605 are respectively connected to the input end of the or gate 606, and the or gate 606 is used for comprehensively judging whether the C0-C3 change or not, so long as the C0-C3 change, the or gate 606 outputs a keyboard state change pulse F, and the pulse is a positive pulse.

In an embodiment, the delay buffer 601 selects the rising edge triggered 8D flip-flop 74HC 273.

Other schemes can be adopted for the delay buffer 601, for example, an RC circuit is adopted, and 4 RC circuits are used for respectively delaying C0-C3; if the delay time of the RC circuit is less than one clock pulse CP1 period, when the encoder 300 outputs effective codes C3-C0 of one period, a keyboard state change pulse is generated at the beginning of outputting the effective codes C3-C0 and at the end of outputting the effective codes C3-C0, and the width of the keyboard state change pulse is equal to the delay time of the RC circuit; if the delay time of the RC circuit is more than or equal to one clock pulse CP1 cycle, when the encoder 300 outputs effective codes C3-C0 of one cycle, a keyboard state change pulse is generated at the beginning of outputting the effective codes C3-C0, and the pulse width is more than or equal to 2 clock pulse CP1 cycles. The delay time of the RC circuit is required not to exceed 2 clock pulses CP1 cycles in order to avoid false negatives.

In the embodiment, the first buffer register 101 performs data latch at the falling edge of the scan pulse CP2, and the second buffer register 102 performs data latch at the rising edge of the scan pulse CP 2. The data latch may be performed by the first buffer register 101 at the rising edge of the scan pulse CP2, and the data latch may be performed by the second buffer register 102 at the falling edge of the scan pulse CP2, in which case, the outputs of the data selecting unit 500 constitute the state code with the current key value preceding and the previous key value succeeding each other. The state code composed of the mode that the current state key value is before and the previous state key value is after is also suitable for the invention.

In an embodiment, the state code may be composed by changing the input connection mode of the data selecting unit 500 in a manner that the current state key value is before and before the current state key value.

In the inventive circuit, the positioning of single key operation, combined key operation and keyboard maintenance state operation is controlled by clock pulse CP1 and scan pulse CP2 to be converted into state code with the same binary length, and processed by adopting a uniform coding mode, and the single key operation, combined key operation and keyboard maintenance state operation are only reflected on the difference of the state code; if the key operation function needs to be increased or decreased or the key operation function needs to be adjusted, the structure of the keyboard scanning circuit does not need to be modified, and the encoding content of the encoder 300 only needs to be updated according to the increased or decreased state code table, that is, the storage content of the read-only memory is rewritten and updated. The circuit of the invention does not use microcontrollers such as a singlechip and an ARM, does not need running programs, and has reliable work.

Claims

1. A free-standing keyboard scanning and encoding method is characterized in that: comprises thatNIndependent keyboard output of individual keysNA keyboard status signal; scanning pulse pairNThe bit keyboard state signal is used for carrying out data latching and selection to obtain a current state key value and a previous state key value; the clock pulse carries out state latch on the present state key value and the previous state key value to obtain 2 dataNA status code of the bit; encoding the status code and outputting a key number; the bits are binary bits;

the scanning pulse pairNThe method for obtaining the present state key value and the previous state key value by carrying out data latch and selection on the bit keyboard state signal is that the high level and the low level of the scanning pulse control the output ends of the 2 buffer registers to alternately output the present state key value and the previous state key value;

the state code is coded and the key number is output by the coder; the scanning pulse pairNThe bit keyboard state signal is used for carrying out data latching and selection to obtain a current state key value and a previous state key value, and the current state key value and the previous state key value are realized by a first buffer register, a second buffer register and a data selection unit;

the first mentionedOne buffer register and the second buffer register are bothNA bit binary register; of said first buffer registerNThe bit data input terminal is connected toNBit keyboard status signal output, of a second buffer registerNThe bit data input terminal is connected toNThe receiving pulse input ends of the first buffer register and the second buffer register are connected to the scanning pulse;

the data selection unit is provided with a first pathNBit data input terminal, second pathNBit data input and 2 data inputNA bit data output terminal; the first path isNThe bit data input terminal being connected in turn to the first buffer registerNBit data output, second pathNThe bit data input terminal being connected in turn to a second buffer registerNA bit data output terminal;

the data selection unit is also provided with a data selection signal end; the data selection signal end is connected to the scanning pulse;

data selection unit 2NIn the bit data output, when the scanning pulse is at low level, the first pathNBit data leading, second wayNThe bit data is backward; when the scanning pulse is at high level, the first pathNBit data later, second wayNBit data is ahead; or 2 books of the data selection unitNIn the bit data output, when the scanning pulse is at low level, the first pathNBit data later, second wayNBit data is ahead; when the scanning pulse is at high level, the first pathNBit data leading, second wayNThe bit data is backward;

the clock pulse carries out state latch on the present state key value and the previous state key value to obtain 2 in a predetermined amountNThe status code of the bit is implemented by a status code register; the status code register is 2NA bit binary register; 2 register of state codeN2-element with bit data input connected to data selection unitNA bit data output end, a receiving pulse input end is connected to the clock pulse; the status code register latches data at a status latch edge of the clock pulse.

2. A method of scanning and encoding a free standing keyboard as claimed in claim 1, wherein: the state code consists of an effective state code and an ineffective state code and is used for identifying the current state and the operation state of the independent keyboard; the key number is composed of a valid key number and an invalid key number; the effective state code is generated by the operation or the state of an effective keyboard, and a corresponding effective key number is correspondingly output; the invalid state code is generated by invalid keyboard operation or state and correspondingly outputs an invalid key number.

3. A method of scanning and encoding of a free standing keyboard as claimed in claim 2, wherein: the effective keyboard operation comprises single-key pressing operation, single-key releasing operation, single-key pressing maintaining operation and combined key operation; the combined key operation refers to the operation that after a single key is pressed down, other keys are pressed down; the invalid keyboard operation is an operation other than the valid keyboard operation.

4. A method of scanning and encoding of a free standing keyboard as claimed in claim 2, wherein: the key number isMThe number of bits is,Mthe value should be selected to satisfy 2^MGreater than or equal to the sum of the number of valid and invalid key numbers.