JP3551390B2 - Semiconductor inspection equipment - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a technology that is effective when applied to a semiconductor inspection device, and further to a semiconductor device inspection device that outputs a digital signal. For example, the present invention relates to a technology that is effective for use in a bit missing inspection of an A / D converter. It is about.
[0002]
[Prior art]
2. Description of the Related Art In a semiconductor device, particularly, an A / D converter that converts an analog input signal into a digital signal and outputs the digital signal, a defect that a specific digital conversion value is not output, that is, a so-called bit missing defect may occur. Therefore, in the process of manufacturing a semiconductor device such as an A / D converter, an inspection for checking whether or not the bit is missing becomes necessary.
[0003]
In order to perform this inspection, a semiconductor inspection device as shown in FIG. 4 is provided.
[0004]
The inspection apparatus shown in FIG. 4 statistically processes the digital output Dx of the A / D converter 1 which is the device to be inspected by the data processing device 41, and as shown in FIG. Then, it is determined whether or not a bit is missing.
[0005]
FIG. 5 is a graph showing the frequency of appearance of a digital output signal obtained by inputting a sine wave analog signal to the A / D converter 1 for each output value. When the frequency drops extremely, the presence or absence of the bit missing can be determined (see, for example, “System Application Guide A / D Converter Edition” published by Analog Devices, Inc., September 1993, pp. 117-130).
[0006]
[Problems to be solved by the invention]
However, the present inventors have clarified that the above-described technique has the following problems.
[0007]
That is, in the above-described semiconductor inspection apparatus, a large amount of data is required to perform statistical processing by the histogram method, and a large amount of time is required for data collection, the statistical processing, and analysis of the statistical processing result. Occurs. This has hindered the efficiency of the inspection of the A / D converter and the like.
[0008]
SUMMARY OF THE INVENTION An object of the present invention is to provide a technique for increasing the efficiency of bit missing inspection of a semiconductor device such as an A / D converter.
[0009]
The above and other objects and features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0010]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0011]
That is, the address of the RAM is specified by the digital output value of the A / D converter formed as a semiconductor device, and the specific data “1” is written for each specified address, and then written to the RAM. While sequentially reading stored data by address scanning, it is detected whether or not different data “0” other than the specific data has appeared in the read data.
[0012]
[Action]
According to the above-described means, the presence / absence of a missing bit can be detected simply and in a short time without depending on a statistical process requiring a large amount of data collection.
[0013]
This achieves the object of increasing the efficiency of bit missing inspection of a semiconductor device such as an A / D converter.
[0014]
【Example】
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
In the drawings, the same reference numerals indicate the same or corresponding parts.
[0015]
FIG. 1 shows an embodiment of a semiconductor inspection apparatus to which the technology of the present invention is applied, wherein 1 is an A / D converter which is an apparatus to be inspected, 11 is a test signal source, 12 is a counter, 13 Is a data selection circuit, 14 is a RAM (random access memory), 15 is a data latch circuit, φ1 and φ2 are clock signals, and Vx is an analog input signal.
[0016]
The A / D converter 1 converts the analog input signal Vx supplied from the test signal source 11 into a parallel digital signal in synchronization with the sampling clock φ1. Dx is the digital output.
[0017]
The test signal source 11 outputs a sine wave having an amplitude equal to or larger than the input dynamic range of the A / D converter 1 and supplies the sine wave to the A / D converter 1. Thus, the digital output value of the A / D converter 1 as the device to be inspected is changed over the entire range from the lower limit to the upper limit of the inspection range. For example, if the range of the digital output value of the A / D converter 1 is 0 to 1023 (decimal conversion), a sine wave having an amplitude that can be changed from the lower limit (0) to the upper limit (1023) of the range. An analog signal Ain is output.
[0018]
The counter 12 outputs the count values sequentially incremented by one in response to the clock φ2 in parallel. The count output Dc is provided to the RAM 14 via the data selection circuit 13 as an address signal (Ain).
[0019]
The data selection circuit 13 switches and selects the digital output Dx of the A / D converter 1 and the count output Dc of the counter 12, and supplies the selected output (Dx / Dc) to the RAM 14 as an address. The control of the data selection circuit 13 is performed in conjunction with the write / read mode switching of the RAM 14 based on a measurement mode switching command externally given.
[0020]
The RAM 14 has an address width corresponding to the digital output value width of the A / D converter 1 and a storage data size of 1 bit, and is addressed by the digital output Dx or the count output Dc provided through the selection circuit 13. You. Ain is an address input, Din is a memory write data input, Dout is a memory read data output, and R / W is a write / read mode setting input. Din is connected to the power supply potential Vcc, and a high-level “1” is always input.
[0021]
The data latch circuit 15 includes a logic gate 151 and an RS flip-flop 152 as shown in FIG. In the data latch circuit 15 shown in FIG. 11, when the set output of the flip-flop circuit 152 is once preset to “1” and “0” appears in the read data output Dout from the RAM 14, the “0” becomes “0”. The output is reset from "1" to "0" when it appears. Thus, once the flip-flop circuit 152 is reset, this reset state is maintained even after the read data output Dout outputs "1" again. Thus, when the RAM 14 is in the read mode, it is possible to detect and hold whether or not different data “0” other than the specific data “1” appears in the read data Dout.
[0022]
As described above, in the above-described semiconductor inspection apparatus, the writing control means for writing the specific data “1” for each specified address of the RAM 14 and the counter 12 storing the stored data written at each address of the RAM 14 Read control means for sequentially reading by address scanning and data detecting means for detecting whether or not different data "0" other than the specific data "1" appears in the storage data read by the address scanning of the RAM 14. Is formed.
[0023]
Next, the operation will be described.
[0024]
FIG. 3 is a timing chart showing the operation of the main part of the semiconductor inspection apparatus shown in FIGS. 1 and 2.
[0025]
In FIGS. 1, 2, and 3, the bit missing inspection of the A / D converter 1 is performed in two steps of a measurement mode and a verification mode.
[0026]
In the measurement mode, first, all the data stored in the RAM 14 are initialized to “0”, and the selected position of the data selection circuit 13 is set so that the digital output Dx of the A / D converter 1 is given to the address input Ain of the RAM 14. (Port) is set. Further, the RAM 14 is set to the write mode.
[0027]
After the above setting, a sine wave analog input signal Ax is supplied to the A / D converter 1. At the same time, the conversion operation of the A / D converter 1 and the writing operation of the RAM 14 are performed in synchronization with each other by the sampling clock φ1.
[0028]
As a result, in the RAM 14, the 1-bit data of "1" is written only to the address (Dx) specified by the digital output value (Dx) of the A / D converter 1, and the storage data of the other addresses is "0". Will remain.
[0029]
Here, the analog input signal Ain supplied from the test signal source 11 to the A / D converter 1 changes the digital output value (Dx) of the A / D converter 1 over the entire range (full scale) from the lower limit to the upper limit. If the signal is a signal that changes continuously, the 1-bit data of “1” is written in the RAM 14 at all addresses corresponding to the digital output value (Dx) of the A / D converter 1. Should be. For example, assuming that the entire range of the digital output value (Dx) of the A / D converter 1 is 0 to 1023 (decimal number conversion), the corresponding entire address range of the RAM 14 is 0 to 1023 (decimal number conversion). , "1" should be written. In other words, "1" should be written to all addresses 0 to 1023 (decimal number conversion).
[0030]
However, if a specific data value is not output in the entire range (0 to 1023) of the digital output value (Dx), that is, if there is a missing bit, the address corresponding to the missing data value is: Writing "1" is not performed, and therefore only the storage data at the address corresponding to the bit missing data value remains "0". For example, if only data having a value of 64 (decimal number conversion) is missing from the digital output Dx of the A / D converter 1, only the storage data at the address 64 corresponding to the 64 remains "0". It becomes.
[0031]
As described above, in the measurement mode, "1" is written only to the address corresponding to the data value actually output by the A / D converter 1 as the device to be inspected. This writing of "1" is performed on the address corresponding to the entire output range of the A / D converter 1 if there is no bit missing in the output Dx of the A / D converter 1. If at least one bit is missing in the output Dx of the / D converter 1, only the address corresponding to the missing bit remains different data "0" different from the above "1". After executing such a measurement mode, a verification mode described below is performed.
[0032]
In the verification mode, first, the count content of the counter 12 is initialized, and the output of the data latch circuit 15 is preset to “1”. Further, the selection position of the data selection circuit 13 is set so that the count output Dc of the counter 12 is given to the address input Ain of the RAM 14. Then, the RAM 14 is set to the reading mode.
[0033]
After the above setting, the counter 12 is incremented by one by the clock φ2, and the reading operation of the RAM 14 is performed in synchronization with the increment operation of the counter 12. The read data output Dout of the RAM 14 is input to the data latch circuit 15 in synchronization with the clock φ2. That is, address scanning is performed by the counter 12 in the RAM 14, and stored data at an address corresponding to the count output Dc of the counter 12 is read out in synchronization with the clock φ 2 and input to the data latch circuit 15. In this case, the counting range of the counter 12 corresponds to the entire output value range of the A / D converter 1. For example, if the entire output value range of the A / D converter 1 is 0 to 1023 (decimal conversion), the counting range of the counter 12 is also set to 0 to 1023 (decimal conversion).
[0034]
Here, if the storage data sequentially read from each address of the RAM 14 is only the same specific data “1”, the output of the data latch circuit 15 continues to hold the initial preset state “1”. If the output of the data latch circuit 15 holds the initial preset state “1” at the time when reading is completed for the entire address range of the RAM 14, if the output of the RAM 14 is in the above-described measurement mode, This means that the entire range of the address has been accessed by the digital output Dx of the A / D converter 1. In other words, the A / D converter 1 has output all the address values of the RAM 14. Therefore, the held output “1” of the data latch circuit 15 indicates that the digital output Dx of the A / D converter 1 has no missing bits.
[0035]
On the other hand, if any one of the different data of “0” is mixed in the stored data sequentially read out from the RAM 14, the output of the data latch circuit 15 is determined by the different data of “0”. It is reset to "0". This reset state of "0" is maintained as it is even if "1" continues to storage data read out thereafter. Therefore, if the output of the data latch circuit 15 has changed to "0" at the time when the reading has been completed for the entire address range of the RAM 14, this means that the A / D converter 1 outputs the entire address value of the RAM 14. It was not done. That is, the held output “0” of the data latch circuit 15 indicates that the digital output Dx of the A / D converter 1 has missing bits.
[0036]
As described above, the address of the RAM is designated by the digital output value of the A / D converter 1, and the specific data "1" is written for each designated address, and then the storage written in the RAM. By sequentially reading data by address scanning and detecting whether or not different data “0” other than the specific data “1” appears in the read data, a statistical data requiring a large amount of data collection is detected. The presence / absence of missing bits can be detected simply and in a short time without depending on the processing. As a result, the efficiency of the bit missing inspection of a semiconductor device such as an A / D converter is improved.
[0037]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and it can be said that various modifications can be made without departing from the gist of the invention. Not even.
[0038]
For example, the specific data to be written to the RAM 14 may be data of a plurality of bits. In addition, each component such as a data latch circuit can be realized as software by a computer in the form of a microcircuit.
[0039]
In the above description, the case where the invention made by the present inventor is applied to an A / D converter, which is a field of application as a background, has been mainly described. However, the present invention is not limited to this case. The present invention can also be applied to the inspection of a device that continuously outputs a predetermined range of digital values, such as a sensor that measures an analog event and outputs a digital value, such as a barometer.
[0040]
【The invention's effect】
The effects of typical inventions disclosed in the present application will be briefly described as follows.
[0041]
That is, the presence / absence of a bit missing can be detected easily and in a short time without relying on a statistical process requiring a large amount of data collection. Therefore, the bit missing inspection of a semiconductor device such as an A / D converter can be performed. The effect that high efficiency can be obtained is obtained.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an embodiment of a semiconductor inspection device to which the technology of the present invention is applied. FIG. 2 is a circuit diagram showing a configuration example of a data latch circuit used in the present invention. FIG. 4 is a circuit diagram showing an outline of a conventional semiconductor inspection apparatus. FIG. 5 is a view showing an outline of a semiconductor inspection using a conventional apparatus.
1 A / D converter 11 to be inspected 11 Test signal source 12 Counter 13 Data selection circuit 14 RAM (random access memory)
15 Data latch circuits φ1, φ2 Clock signal Vx Analog input signal.
Dx Digital output Dc Count output Ain Address input Din Storage write data input Dout Storage read data output R / W Write / read mode

Claims (4)

A test signal source for supplying an input signal to a device under test that outputs a digital signal to change the digital output value over the entire range from the lower limit to the upper limit of the test range, the RAM, and the addressing of the RAM are described above. Writing control means for performing specific data at each designated address while performing the digital output value, reading control means for sequentially reading stored data written at each address of the RAM by address scanning, Data detection means for detecting whether or not different data other than the specific data has appeared in the storage data read by the address scanning of the RAM ,
The data detecting means is constituted by using a latch circuit for detecting and holding whether or not different data other than specific data appears in the read data when the RAM is in the read mode. semiconductor inspection apparatus for. 2. The test signal source according to claim 1, wherein the test signal source supplies the device under test performing the analog-digital conversion with an analog input signal that changes its digital output value over the entire range from a lower limit to an upper limit. Semiconductor inspection equipment. The write control means and the read control means have a counter whose count value is sequentially increased by a clock, and a selection circuit for switching and selecting a digital output of the device under test and a count output of the counter to give an address to the RAM. 3. The semiconductor device according to claim 1, wherein the RAM is set to a write mode when the digital output is selected, and the RAM is set to a read mode when the count output is selected. Inspection equipment. Specific data is "1" or a semiconductor inspection apparatus according to any one of is 1-bit data of "0" from claim 1, wherein up to 3.

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