CN108847435A - A kind of LED epitaxial slice and preparation method thereof - Google Patents
A kind of LED epitaxial slice and preparation method thereof Download PDFInfo
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- CN108847435A CN108847435A CN201810395861.2A CN201810395861A CN108847435A CN 108847435 A CN108847435 A CN 108847435A CN 201810395861 A CN201810395861 A CN 201810395861A CN 108847435 A CN108847435 A CN 108847435A
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- 239000012298 atmosphere Substances 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
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- 238000005229 chemical vapour deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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Abstract
The invention discloses a kind of LED epitaxial slices and preparation method thereof, belong to semiconductor light electrical domain.Setting includes the BN/B in N number of period in layer of undoped ganxGa1‑xThe stress release layer of N superlattice structure, BN/BxGa1‑xN superlattice structure can accumulate tensile stress in the epitaxial layer, and tensile stress can cancel out each other with undoped with the part compression in GaN, and then reduce by undoped with the compression bring line defect and piezoelectric polarization in GaN.The reduction of line defect can be improved the quality of epitaxial wafer in epitaxial wafer, and its reduction can also substantially reduce the formation of multi-quantum well active region non-radiative recombination center, and then improving luminous efficiency.And the reduction of piezoelectric polarization can also reduce by spontaneous polarization bring Quantum Well Stark restriction effect in piezoelectric polarization and epitaxial wafer, to improve luminous efficiency.
Description
Technical field
The present invention relates to semiconductor light electrical domain, in particular to a kind of LED epitaxial slice and preparation method thereof.
Background technique
Epitaxial wafer is the foundation structure for making light emitting diode, and the structure of epitaxial wafer includes substrate and grows on substrate
Epitaxial layer.Wherein, the structure of epitaxial layer mainly includes：Successively grow AlN buffer layer on substrate, undoped GaN layer,
N-type GaN layer, multiple quantum well active layer and p-type GaN layer.
The setting of undoped GaN layer can reduce existing lattice mismatch between N-type GaN layer and substrate, to improve not
The growth quality of the epitaxial layer grown after the GaN layer of doping.But it is undoped in the growth course of undoped GaN layer
Compression can be constantly accumulated in GaN layer, compression can form line defect in undoped GaN layer and bring piezoelectric polarization, into
And the total quality of epitaxial wafer is reduced, influence the luminous efficiency by the prepared light emitting diode of the epitaxial wafer.
Summary of the invention
To improve the quality of epitaxial wafer and improving the luminous efficiency of light emitting diode, the embodiment of the invention provides a kind of hairs
Optical diode epitaxial wafer and preparation method thereof.The technical solution is as follows：
The embodiment of the invention provides a kind of LED epitaxial slice, the epitaxial wafer includes that substrate and stacking gradually is set
Set AlN buffer layer, layer of undoped gan, stress release layer, N-type GaN layer, multiple quantum well active layer and p-type over the substrate
GaN layer, wherein stress release layer includes the BN/B in N number of periodxGa1-xN superlattice structure, 0.01<x<0.05, N is greater than 2
Integer.
Optionally, the thickness of the stress release layer is less than the thickness of the N-type GaN layer.
Optionally, the stress release layer with a thickness of 1~2 μm.
Optionally, in the BN/BxGa1-xIn N superlattice structure, BN sublayer with a thickness of 5~10nm, BxGa1-xN sublayer
With a thickness of 10~20nm.
Optionally, the stress release layer includes the BN/B in 30~40 periodsxGa1-xN superlattice structure.
The embodiment of the invention provides a kind of preparation method of LED epitaxial slice, the preparation method includes：
One substrate is provided；
Growing AIN buffer layer over the substrate；
Layer of undoped gan is grown on the AlN buffer layer；
The growth stress releasing layer in the layer of undoped gan, wherein the stress release layer includes the BN/ in N number of period
BxGa1-xN superlattice structure, 0.01<x<0.05, N is the integer greater than 2；
N-type GaN layer is grown on the stress release layer；
Multiple quantum well active layer is grown in the N-type GaN layer；
The growth P-type GaN layer in the multiple quantum well active layer.
Optionally, the growth temperature of the stress release layer is 1100~1150 DEG C.
Optionally, the growth temperature of the stress release layer is greater than the growth temperature of the N-type GaN layer.
Optionally, the preparation method further includes：
Over the substrate before grown epitaxial layer structure, anneal in a hydrogen atmosphere to the substrate.
Optionally, the preparation method further includes：
Before growing layer of undoped gan on the AlN buffer layer, in-situ annealing processing is carried out to the AlN buffer layer.
Technical solution bring beneficial effect provided in an embodiment of the present invention is：Setting includes N number of in layer of undoped gan
The BN/B in periodxGa1-xThe stress release layer of N superlattice structure, BN/BxGa1-xN superlattice structure can accumulate drawing in the epitaxial layer
Stress, tensile stress can cancel out each other with undoped with the part compression in GaN, and then reduce by answering undoped with the pressure in GaN
Power bring line defect and piezoelectric polarization.The reduction of line defect can be improved the quality of epitaxial wafer in epitaxial wafer, and it is reduced
Also the formation of multi-quantum well active region non-radiative recombination center, and then improving luminous efficiency can be substantially reduced.And piezoelectric polarization
Reduction, which can also reduce, (refers to multiple quantum wells by spontaneous polarization bring Quantum Well Stark restriction effect in piezoelectric polarization and epitaxial wafer
In structure, under the action of its built-in polarized electric field, the energy band run-off the straight of semiconductor, electron-hole pair is spatially separating,
The phenomenon that wave function amount over overlap is reduced, and caused luminous efficiency declines), to improve luminous efficiency.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of structural schematic diagram of LED epitaxial slice provided in an embodiment of the present invention；
Fig. 2 is a kind of preparation method flow chart of LED epitaxial slice provided in an embodiment of the present invention；
Fig. 3 is a kind of epitaxial slice structure flow chart of embodiment provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
Fig. 1 is a kind of structural schematic diagram of LED epitaxial slice provided in an embodiment of the present invention, as shown in Figure 1, should
Epitaxial wafer includes substrate 1 and the AlN buffer layer 2 being cascading on substrate 1, layer of undoped gan 3, stress release layer 4, N
Type GaN layer 5, multiple quantum well active layer 6 and p-type GaN layer 7, wherein stress release layer 4 includes the BN/B in N number of periodxGa1-xN is super
Lattice structure, 0.01<x<0.05, N is the integer greater than 2.
Setting includes the BN/B in N number of period in layer of undoped ganxGa1-xThe stress release layer of N superlattice structure, BN/
BxGa1-xN superlattice structure can accumulate tensile stress in the epitaxial layer, and tensile stress can be with the part compression phase in undoped GaN
It mutually offsets, and then reduces by undoped with the compression bring line defect and piezoelectric polarization in GaN.Line defect subtracts in epitaxial wafer
It can be improved the quality of epitaxial wafer less, and its reduction can also substantially reduce the shape of multi-quantum well active region non-radiative recombination center
At, and then improving luminous efficiency.And the reduction of piezoelectric polarization can also reduce and be brought by piezoelectric polarization and spontaneous polarization in epitaxial wafer
Quantum Well Stark restriction effect (refer in multi-quantum pit structure, under the action of its built-in polarized electric field, the energy band of semiconductor
The phenomenon that run-off the straight, electron-hole pair is spatially separating, wave function amount over overlap is reduced, and caused luminous efficiency declines),
To improve luminous efficiency.
Wherein, the thickness of AlN buffer layer 2 can be 20~40nm.Can effectively play within this range reduce N-type GaN layer with
Lattice mismatch issue between substrate.
Further, the thickness of layer of undoped gan 3 can be 1 μm.Reduction can be more efficiently played under this thickness condition
The problem of lattice mismatch between N-type GaN layer and substrate.
Optionally, stress release layer 4 with a thickness of 1~2 μm.The thickness of stress release layer is arranged can in range above
So that stress release layer is released effectively the compression accumulated in layer of undoped gan, guarantee the total quality of epitaxial wafer.
Wherein, BN/BxGa1-xIn N superlattice structure, BN sublayer 41 with a thickness of 5~10nm, BxGa1-xThe thickness of N sublayer 42
Degree is 10~20nm.BN sublayer and BxGa1-xN sublayer thickness setting range above can in its general construction preferable landform
At tensile stress, preferably to discharge the compression in layer of undoped gan, guarantee the quality and its illumination effect of light emitting diode.
Optionally, BN/BxGa1-xThe period of N superlattice structure is 30~40.By BN/BxGa1-xThe period of N superlattice structure
It is set as 30~40 and enables to BN/BxGa1-xThe effect that N superlattice structure discharges stress is preferable, advantageously ensures that epitaxial wafer
Total quality.
In the present embodiment, the thickness of N-type GaN layer 5 can be 2~3 μm.So that N-type GaN layer can effectively provide it is enough
Carrier.
Further, the thickness of stress release layer 4 is smaller than the thickness of N-type GaN layer 5.The thickness of stress release layer is set
It is set to the thickness less than N-type GaN layer, is released effectively the same of the compression accumulated in layer of undoped gan in proof stress releasing layer
When, the growth cost of epitaxial wafer entirety can be reduced.
Optionally, the thickness of multi-quantum well active region 6 can be 100~150nm.
Wherein, multiple quantum well active layer may include alternately stacked InaGa1-aN well layer 61 and GaN barrier layer 62, wherein 0<a<
1。
Optionally, in other embodiments of the invention, lnGaAs well layer and GaAs can also be used in multiple quantum well active layer
The structure or other structures of barrier layer alternating growth, the present invention are without limitation.
As described in Figure 1, the present invention may also include electronic barrier layer 8, high temperature p-type GaN layer 9 and p-type contact layer 10.
Electronic barrier layer 8 can stop electronics to enter p-type GaN layer 7 by multi-quantum well active region 6, be conducive to limit electronics
System carries out recombination luminescence in multiple quantum well active layer 7.It improves by the epitaxial wafer in the embodiment of the present invention prepared luminous two
The luminous efficiency of the chip of pole pipe.
In the present embodiment, the thickness of electronic barrier layer 8 can be 200~300nm.
In the present embodiment, the setting of high temperature p-type GaN layer 9 can provide more holes enter multiple quantum well active layer 7 into
Row is compound, is conducive to the luminous effect of the chip of the prepared light emitting diode of the epitaxial wafer improved by the embodiment of the present invention
Rate.
In the present embodiment, the thickness of high temperature p-type GaN layer 9 can be 100~200nm.
In the present embodiment, the subsequent production of p-type contact layer 10 being provided with conducive to epitaxial wafer.Its thickness can for 500~
100nm。
Fig. 2 is a kind of preparation method flow chart of LED epitaxial slice provided in an embodiment of the present invention, such as Fig. 2 institute
Show, which includes：
S1：One substrate is provided.
Wherein, Sapphire Substrate can be used in substrate.
Optionally, this preparation method may also include, and make annealing treatment to substrate.To obtain surface quality preferably more
Clean substrate advantageously ensures that the quality of the epitaxial layer grown on substrate.
Wherein, carrying out annealing to substrate may include：It anneals in a hydrogen atmosphere to substrate, annealing temperature 1000
DEG C -1100 DEG C, annealing pressure 200Torr-500Torr.
Further, after substrate completes annealing operation, can also nitrogen treatment be carried out to substrate, i.e., grown on substrate
AlN buffer layer.
S2：Growing AIN buffer layer on substrate.
Wherein, the growth temperature of AlN buffer layer can be 400 DEG C -600 DEG C, and the growth pressure of AlN buffer layer can be
400Torr-600Torr.The quality of the AlN buffer layer obtained at this temperature is preferable, can effectively play reduction N-type ALN layer and
Lattice mismatch issue between substrate.
Wherein, the thickness of AlN buffer layer can be 20~40nm.It can effectively play within this range and reduce N-type GaN layer and lining
Lattice mismatch issue between bottom.
Optionally, which may also include：
It is grown on AlN buffer layer undoped with before AlN layers, in-situ annealing processing is carried out to AlN buffer layer.
The dislocation that can be reduced in AlN buffer layer is made annealing treatment to AlN buffer layer, guarantees the quality of AlN buffer layer, has
Conducive to the growth of subsequent epitaxial layer.
Wherein, carrying out annealing to AlN buffer layer includes：
Under conditions of annealing temperature is 1000 DEG C -1200 DEG C, annealing pressure is 400Torr-600Torr, AlN is buffered
Layer carries out in-situ annealing processing, anneal duration 5-10min.
S3：Layer of undoped gan is grown on AlN buffer layer.
Wherein, the growth temperature of layer of undoped gan can be 1000 DEG C -1100 DEG C, growth pressure can for 100Torr~
200Torr.The quality of the layer of undoped gan grown with this condition is preferable.
Further, the thickness of layer of undoped gan can be 1 μm.It can more efficiently be played under this thickness condition and reduce N
The problem of lattice mismatch between type GaN layer and substrate.
S4：The growth stress releasing layer in layer of undoped gan.Wherein, stress release layer includes the BN/ in N number of period
BxGa1-xN superlattice structure, 0.01<x<0.05, N is the integer greater than 2.
Wherein, the growth temperature of stress release layer can be 1100~1150 DEG C.The growth temperature of stress release layer is arranged
For range above, it can guarantee the quality for the stress release layer that growth obtains, and then proof stress releasing layer is discharged undoped with GaN
The effect of compression in layer.
The growth pressure of stress release layer can be 100Torr~200Torr.
Optionally, the growth time of BN sublayer is 25s, BxGa1-xThe growth time of N sublayer is 15s.By BN sublayer with
BxGa1-xThe growth time of N sublayer is set as range above, can guarantee the quality for the stress release layer that growth obtains, Jin Erbao
Demonstrate,prove the effect of compression in stress release layer release layer of undoped gan.
Optionally, stress release layer with a thickness of 1~2 μm.The thickness of stress release layer is arranged can in range above
So that stress release layer is released effectively the compression accumulated in layer of undoped gan, guarantee the total quality of epitaxial wafer.
Wherein, BN/BxGa1-xIn N superlattice structure comprising BN sublayer with a thickness of 5~10nm, BxGa1-xN sublayer
With a thickness of 10~20nm.BN sublayer and BxGa1-xThe thickness setting of N sublayer can be in its general construction preferably in range above
Ground forms tensile stress, preferably to discharge the compression in layer of undoped gan, guarantees the quality of light emitting diode and its effect that shines
Fruit.
Optionally, BN/BxGa1-xThe period of N superlattice structure is 30~40.By BN/BxGa1-xThe period of N superlattice structure
It is set as 30~40 and enables to BN/BxGa1-xThe effect that N superlattice structure discharges stress is preferable, advantageously ensures that epitaxial wafer
Total quality.
Specifically, BN/B is grownxGa1-xThe process of N superlattice structure can be：In 1100~1150 DEG C of temperature conditions and
Under the conditions of the growth pressure of 100Torr~200Torr, TMB and suitable NH are passed through into reaction chamber3, BN is grown from layer, growth
After the BN sublayer of 25s, TMGa and TMB and appropriate NH are passed through into reaction chamber3, grow the B of 15sxGa1-xN sublayer.More than repeating
Process is to obtain BN/BxGa1-xN superlattice structure.
The epitaxial slice structure figure executed the step after S4 can be as shown in figure 3, its structure includes substrate 1 and stacks gradually
AlN buffer layer 2, layer of undoped gan 3, stress release layer 4 on substrate 1, stress release layer 4 include the BN/ in N number of period
BxGa1-xN superlattice structure, BN/BxGa1-xN superlattice structure includes BN sublayer 41 and BxGa1-xN sublayer 42.
S5：N-type GaN layer is grown on stress release layer.
Wherein, the growth temperature of N-type GaN layer can be 1100 DEG C -1150 DEG C, and growth pressure can be 200Torr.
Optionally, the doped chemical of N-type GaN layer is Si element, and the doping concentration of Si element is 1018cm-3-1019cm-3。
In the present embodiment, the thickness of N-type GaN layer can be 2~3 μm.So that N-type GaN layer can effectively provide it is enough
Carrier.
Optionally, the growth temperature of stress release layer is greater than the growth temperature of N-type GaN layer.By the growth of stress release layer
Temperature setting is the growth temperature greater than N-type GaN layer, can be N-type GaN while the growth quality of proof stress releasing layer
The growth of layer is prepared.
S6：Multiple quantum well active layer is grown in N-type GaN layer.
Optionally, the growth temperature of multiple quantum well active layer can be 700~900 DEG C.To guarantee to grow obtained Multiple-quantum
The quality of trap active layer.
Optionally, the thickness of multi-quantum well active region can be 100~150nm.
Illustratively, multiple quantum well active layer can be multiple quantum well layer, and multiple quantum well active layer includes alternately stacked
InaGa1-aN well layer and GaN barrier layer, wherein 0<a<1.
S7：The growth P-type GaN layer in multiple quantum well active layer.
Optionally, the growth temperature of p-type GaN layer can be 700~800 DEG C, and growth pressure can be 100Torr-300Torr.
Further, this preparation method may also include：
Electronic barrier layer, high temperature p-type GaN layer and p-type contact layer are successively grown in p-type GaN layer.
Wherein, the growth temperature of electronic barrier layer, high temperature p-type GaN layer and p-type contact layer can be 950~1000 DEG C,
Growth pressure can be 200Torr.
In the present embodiment, the thickness of electronic barrier layer can be 200~300nm, and the thickness of high temperature p-type GaN layer 9 can be
100~200nm, the thickness of p-type contact layer 10 can be 500~100nm.
Having executed the epitaxial slice structure schematic diagram after above step can be as shown in Figure 1, its structure includes substrate 1 and successively
It is active to be stacked AlN buffer layer 2 on substrate 1, layer of undoped gan 3, stress release layer 4, N-type GaN layer 5, multiple quantum wells
Layer 6, p-type GaN layer 7, electronic barrier layer 8, high temperature p-type GaN layer 9 and p-type contact layer 10.
Setting includes the BN/B in N number of period in layer of undoped ganxGa1-xThe stress release layer of N superlattice structure, BN/
BxGa1-xN superlattice structure can accumulate tensile stress in the epitaxial layer, and tensile stress can be with the part compression phase in undoped GaN
It mutually offsets, and then reduces by undoped with the compression bring line defect and piezoelectric polarization in GaN.Line defect subtracts in epitaxial wafer
It can be improved the quality of epitaxial wafer less, and its reduction can also substantially reduce the shape of multi-quantum well active region non-radiative recombination center
At, and then improving luminous efficiency.And the reduction of piezoelectric polarization can also reduce and be brought by piezoelectric polarization and spontaneous polarization in epitaxial wafer
Quantum Well Stark restriction effect (refer in multi-quantum pit structure, under the action of its built-in polarized electric field, the energy band of semiconductor
The phenomenon that run-off the straight, electron-hole pair is spatially separating, wave function amount over overlap is reduced, and caused luminous efficiency declines),
To improve luminous efficiency.
Optionally, this preparation method may also include：
It after epitaxial wafer growth terminates, anneals under nitrogen atmosphere to epitaxial wafer, annealing temperature is 650 DEG C -850
DEG C, anneal duration is 5 to 15min.Epitaxial wafer growth, which anneals to it after terminating, can activate p-type GaN layer and high temperature p-type
Mg atom in GaN layer improves the hole concentration in p-type GaN layer and high temperature p-type GaN layer, is conducive to improve light emitting diode
Luminous efficiency.
Optionally, the growth of the epitaxial layer in the embodiment of the present invention is all made of Metallo-Organic Chemical Vapor deposition and realizes.But
In other embodiments of the invention, the methods of physical vapour deposition (PVD) can also be used in the growth of the epitaxial layer in the embodiment of the present invention
It realizes, the invention is not limited in this regard.
Specifically, realize epitaxial wafer practical growth when, can place the substrate on graphite pallet be sent into reaction chamber in into
The growth of row epitaxial material.
And trimethyl gallium or trimethyl second in an embodiment of the present invention, can be used as gallium source, high pure nitrogen conduct
Nitrogen source, trimethyl indium is as indium source, and trimethyl aluminium is as silicon source, and trimethyl borine is as the source B；N type dopant selects silane, P
Type dopant selects two luxuriant magnesium.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of LED epitaxial slice, which is characterized in that the epitaxial wafer includes substrate and is cascading described
AlN buffer layer, layer of undoped gan, stress release layer, N-type GaN layer, multiple quantum well active layer and p-type GaN layer on substrate,
In, stress release layer includes the BN/B in N number of periodxGa1-xN superlattice structure, 0.01<x<0.05, N is the integer greater than 2.
2. epitaxial wafer according to claim 1, which is characterized in that the thickness of the stress release layer is less than the N-type GaN
The thickness of layer.
3. epitaxial wafer according to claim 2, which is characterized in that the stress release layer with a thickness of 1~2 μm.
4. described in any item epitaxial wafers according to claim 1~3, which is characterized in that in the BN/BxGa1-xN superlattice structure
In, BN sublayer with a thickness of 5~10nm, BxGa1-xN sublayer with a thickness of 10~20nm.
5. described in any item epitaxial wafers according to claim 1~3, which is characterized in that the stress release layer includes 30~40
The BN/B in a periodxGa1-xN superlattice structure.
6. a kind of preparation method of LED epitaxial slice, which is characterized in that the preparation method includes：
One substrate is provided；
Growing AIN buffer layer over the substrate；
Layer of undoped gan is grown on the AlN buffer layer；
The growth stress releasing layer in the layer of undoped gan, wherein the stress release layer includes the BN/ in N number of period
BxGa1-xN superlattice structure, 0.01<x<0.05, N is the integer greater than 2；
N-type GaN layer is grown on the stress release layer；
Multiple quantum well active layer is grown in the N-type GaN layer；
The growth P-type GaN layer in the multiple quantum well active layer.
7. preparation method according to claim 6, which is characterized in that the growth temperature of the stress release layer be 1100~
1150℃。
8. preparation method according to claim 6, which is characterized in that the growth temperature of the stress release layer is greater than described
The growth temperature of N-type GaN layer.
9. according to the described in any item preparation methods of claim 6~8, which is characterized in that the preparation method further includes：
Over the substrate before grown epitaxial layer structure, anneal in a hydrogen atmosphere to the substrate.
10. according to the described in any item preparation methods of claim 6~8, which is characterized in that the preparation method further includes：
Before growing layer of undoped gan on the AlN buffer layer, in-situ annealing processing is carried out to the AlN buffer layer.
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