CN108847435B - Light emitting diode epitaxial wafer and preparation method thereof - Google Patents

Light emitting diode epitaxial wafer and preparation method thereof Download PDF

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CN108847435B
CN108847435B CN201810395861.2A CN201810395861A CN108847435B CN 108847435 B CN108847435 B CN 108847435B CN 201810395861 A CN201810395861 A CN 201810395861A CN 108847435 B CN108847435 B CN 108847435B
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epitaxial wafer
gan layer
type gan
stress release
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CN108847435A (en
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陶章峰
乔楠
余雪平
程金连
胡加辉
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HC Semitek Suzhou Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer

Abstract

The invention discloses a light emitting diodeAn epitaxial wafer and a preparation method thereof belong to the field of semiconductor photoelectricity. Setting BN/B including N periods on an undoped GaN layerxGa1‑xStress relief layer of N-superlattice structure, BN/BxGa1‑xThe N superlattice structure accumulates tensile stress in the epitaxial layer, which can counteract partial compressive stress in the undoped GaN, thereby reducing linear defects and piezoelectric polarization caused by the compressive stress in the undoped GaN. The reduction of line defects in the epitaxial wafer can improve the quality of the epitaxial wafer, and the reduction of line defects can also greatly reduce the formation of non-radiative recombination centers of a multi-quantum well active region, so that the luminous efficiency is improved. The reduction of the piezoelectric polarization can also reduce the quantum well Stark limiting effect brought by the piezoelectric polarization and the spontaneous polarization in the epitaxial wafer, thereby improving the luminous efficiency.

Description

Light emitting diode epitaxial wafer and preparation method thereof
Technical Field
The invention relates to the field of semiconductor photoelectricity, in particular to a light emitting diode epitaxial wafer and a preparation method thereof.
Background
The epitaxial wafer is a basic structure for manufacturing the light emitting diode, and the structure of the epitaxial wafer comprises a substrate and an epitaxial layer grown on the substrate. Wherein, the structure of epitaxial layer mainly includes: an AlN buffer layer, an undoped GaN layer, an N-type GaN layer, a multi-quantum well active layer and a P-type GaN layer which are sequentially grown on the substrate.
The undoped GaN layer is arranged to reduce lattice mismatch existing between the N-type GaN layer and the substrate, so that the growth quality of an epitaxial layer grown after the undoped GaN layer is improved. However, in the growth process of the undoped GaN layer, compressive stress is continuously accumulated in the undoped GaN layer, and the compressive stress forms linear defects in the undoped GaN layer and brings piezoelectric polarization, thereby reducing the overall quality of the epitaxial wafer and affecting the light emitting efficiency of the light emitting diode manufactured by the epitaxial wafer.
Disclosure of Invention
In order to improve the quality of an epitaxial wafer and improve the light emitting efficiency of a light emitting diode, the embodiment of the invention provides a light emitting diode epitaxial wafer and a preparation method thereof. The technical scheme is as follows:
the embodiment of the invention provides a light emitting diode epitaxial wafer, which comprises a substrate, and an AlN buffer layer, an undoped GaN layer, a stress release layer, an N-type GaN layer, a multi-quantum well active layer and a P-type GaN layer which are sequentially stacked on the substrate, wherein the stress release layer comprises N periods of BN/BxGa1-xN superlattice structure, 0.01<x<0.05, and N is an integer more than 2.
Optionally, the thickness of the stress release layer is smaller than that of the N-type GaN layer.
Optionally, the thickness of the stress release layer is 1-2 μm.
Optionally, in the BN/BxGa1-xIn the N superlattice structure, the thickness of BN sublayer is 5-10 nm, and BxGa1-xThe thickness of the N sublayer is 10-20 nm.
Optionally, the stress release layer comprises 30-40 cycles of BN/BxGa1-xAn N superlattice structure.
The embodiment of the invention provides a preparation method of a light-emitting diode epitaxial wafer, which comprises the following steps:
providing a substrate;
growing an AlN buffer layer on the substrate;
growing an undoped GaN layer on the AlN buffer layer;
growing a stress release layer on the undoped GaN layer, wherein the stress release layer comprises N periods of BN/BxGa1-xN superlattice structure, 0.01<x<0.05, N is an integer greater than 2;
growing an N-type GaN layer on the stress release layer;
growing a multi-quantum well active layer on the N-type GaN layer;
and growing a P-type GaN layer on the multiple quantum well active layer.
Optionally, the growth temperature of the stress release layer is 1100-1150 ℃.
Optionally, the growth temperature of the stress release layer is greater than the growth temperature of the N-type GaN layer.
Optionally, the preparation method further comprises:
and before the epitaxial layer structure grows on the substrate, annealing the substrate in a hydrogen atmosphere.
Optionally, the preparation method further comprises:
and before growing an undoped GaN layer on the AlN buffer layer, carrying out in-situ annealing treatment on the AlN buffer layer.
The technical scheme provided by the embodiment of the invention has the following beneficial effects: setting BN/B including N periods on an undoped GaN layerxGa1-xStress relief layer of N-superlattice structure, BN/BxGa1-xThe N superlattice structure accumulates tensile stress in the epitaxial layer, which can counteract partial compressive stress in the undoped GaN, thereby reducing linear defects and piezoelectric polarization caused by the compressive stress in the undoped GaN. The reduction of line defects in the epitaxial wafer can improve the quality of the epitaxial wafer, and the reduction of line defects can also greatly reduce the formation of non-radiative recombination centers of a multi-quantum well active region, so that the luminous efficiency is improved. The reduction of the piezoelectric polarization can also reduce the quantum well stark limiting effect (in a multi-quantum well structure, under the action of a built-in polarization electric field, the energy band of a semiconductor is inclined, and the luminous efficiency is reduced due to the spatial separation of electron-hole pairs and the reduction of the overlapping amount of wave functions) caused by the piezoelectric polarization and the spontaneous polarization in the epitaxial wafer, so that the luminous efficiency is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention;
fig. 3 is a flowchart of an epitaxial wafer structure according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention, as shown in fig. 1, the epitaxial wafer includes a substrate 1, and an AlN buffer layer 2, an undoped GaN layer 3, a stress release layer 4, an N-type GaN layer 5, a multiple quantum well active layer 6, and a P-type GaN layer 7 sequentially stacked on the substrate 1, where the stress release layer 4 includes N periods of BN/BxGa1-xN superlattice structure, 0.01<x<0.05, and N is an integer more than 2.
Setting BN/B including N periods on an undoped GaN layerxGa1-xStress relief layer of N-superlattice structure, BN/BxGa1-xThe N superlattice structure accumulates tensile stress in the epitaxial layer, which can counteract partial compressive stress in the undoped GaN, thereby reducing linear defects and piezoelectric polarization caused by the compressive stress in the undoped GaN. The reduction of line defects in the epitaxial wafer can improve the quality of the epitaxial wafer, and the reduction of line defects can also greatly reduce the formation of non-radiative recombination centers of a multi-quantum well active region, so that the luminous efficiency is improved. The reduction of the piezoelectric polarization can also reduce the quantum well stark limiting effect (in a multi-quantum well structure, under the action of a built-in polarization electric field, the energy band of a semiconductor is inclined, and the luminous efficiency is reduced due to the spatial separation of electron-hole pairs and the reduction of the overlapping amount of wave functions) caused by the piezoelectric polarization and the spontaneous polarization in the epitaxial wafer, so that the luminous efficiency is improved.
Wherein, the AlN buffer layer 2 may have a thickness of 20 to 40 nm. In this range, the problem of lattice mismatch between the N-type GaN layer and the substrate can be effectively reduced.
Further, the thickness of the undoped GaN layer 3 may be 1 μm. Under the condition of the thickness, the problem of lattice mismatch between the N-type GaN layer and the substrate can be effectively reduced.
Optionally, the thickness of the stress release layer 4 is 1-2 μm. The thickness of the stress release layer is set in the range, so that the stress release layer can effectively release compressive stress accumulated in the undoped GaN layer, and the overall quality of the epitaxial wafer is ensured.
Wherein BN/BxGa1-xIn the N superlattice structure, the thickness of the BN sublayer 41 is 5-10 nm, and BxGa1-xThe thickness of the N sub-layer 42 is 10-20 nm. BN sublayer and BxGa1-xThe thickness of the N sublayer is set in the range, so that tensile stress can be well formed in the total structure of the N sublayer, the compressive stress in the undoped GaN layer can be well released, and the quality and the light emitting effect of the light emitting diode are guaranteed.
Alternatively, BN/BxGa1-xThe period of the N superlattice structure is 30-40. Mixing BN/BxGa1-xThe period of the N superlattice structure is set to be 30-40 so that BN/B can be formedxGa1-xThe N superlattice structure has a good stress releasing effect, and the overall quality of the epitaxial wafer is guaranteed.
In the present embodiment, the thickness of the N-type GaN layer 5 may be 2 to 3 μm. So that the N-type GaN layer can effectively provide sufficient carriers.
Further, the thickness of the stress relaxation layer 4 may be smaller than that of the N-type GaN layer 5. The thickness of the stress release layer is set to be smaller than that of the N-type GaN layer, so that the stress release layer is guaranteed to effectively release compressive stress accumulated in the undoped GaN layer, and meanwhile, the overall growth cost of the epitaxial wafer can be reduced.
Alternatively, the thickness of the multiple quantum well active region 6 may be 100to 150 nm.
Wherein the multiple quantum well active layer may include alternately stacked InaGa1-aAn N-well layer 61 and a GaN barrier layer 62 of which 0<a<1。
Alternatively, in other embodiments of the present invention, the multiple quantum well active layer may also adopt a structure in which an lnGaAs well layer and a GaAs barrier layer are alternately grown, or other structures, which is not limited in the present invention.
As shown in fig. 1, the present invention may further include an electron blocking layer 8, a high temperature P-type GaN layer 9, and a P-type contact layer 10.
The electron blocking layer 8 can block electrons from entering the P-type GaN layer 7 from the multi-quantum well active region 6, and is beneficial to limiting the electrons in the multi-quantum well active layer 7 to perform composite luminescence. The light emitting efficiency of the chip of the light emitting diode manufactured by the epitaxial wafer in the embodiment of the invention is improved.
In the present embodiment, the thickness of the electron blocking layer 8 may be 200to 300 nm.
In this embodiment, the high-temperature P-type GaN layer 9 may provide more holes into the multiple quantum well active layer 7 for recombination, which is beneficial to improving the light emitting efficiency of the chip of the light emitting diode manufactured by the epitaxial wafer in the embodiment of the present invention.
In the present embodiment, the thickness of the high temperature P-type GaN layer 9 may be 100-200 nm.
In the present embodiment, the P-type contact layer 10 is provided to facilitate the subsequent fabrication of the epitaxial wafer. The thickness of the film can be 500to 100 nm.
Fig. 2 is a flowchart of a method for manufacturing an led epitaxial wafer according to an embodiment of the present invention, and as shown in fig. 2, the method includes:
s1: a substrate is provided.
Among them, a sapphire substrate may be used as the substrate.
Optionally, the preparation method may further include annealing the substrate. So as to obtain a cleaner substrate with better surface quality, and is beneficial to ensuring the quality of an epitaxial layer grown on the substrate.
Wherein annealing the substrate may include: annealing the substrate in a hydrogen atmosphere at a temperature of 1000 ℃ to 1100 ℃ under a pressure of 200Torr to 500 Torr.
Further, after the substrate is subjected to the annealing process, the substrate may be subjected to a nitriding process, that is, an AlN buffer layer may be grown on the substrate.
S2: an AlN buffer layer is grown on the substrate.
Wherein the growth temperature of the AlN buffer layer can be 400-600 ℃, and the growth pressure of the AlN buffer layer can be 400-600 Torr. The AlN buffer layer obtained at the temperature has good quality, and the problem of lattice mismatch between the N-type ALN layer and the substrate can be effectively solved.
Wherein, the AlN buffer layer can be 20-40 nm thick. In this range, the problem of lattice mismatch between the N-type GaN layer and the substrate can be effectively reduced.
Optionally, the preparation method may further include:
and before growing the undoped AlN layer on the AlN buffer layer, carrying out in-situ annealing treatment on the AlN buffer layer.
And annealing the AlN buffer layer can reduce dislocation in the AlN buffer layer, ensure the quality of the AlN buffer layer and be beneficial to the growth of a subsequent epitaxial layer.
Wherein annealing the AlN buffer layer comprises:
and carrying out in-situ annealing treatment on the AlN buffer layer under the conditions that the annealing temperature is 1000-1200 ℃ and the annealing pressure is 400-600 Torr, wherein the annealing time is 5-10 min.
S3: an undoped GaN layer is grown on the AlN buffer layer.
Wherein the growth temperature of the undoped GaN layer can be 1000-1100 ℃, and the growth pressure can be 100-200 Torr. The quality of the undoped GaN layer grown under the condition is better.
Further, the thickness of the undoped GaN layer may be 1 μm. Under the condition of the thickness, the problem of lattice mismatch between the N-type GaN layer and the substrate can be effectively reduced.
S4: and growing a stress release layer on the undoped GaN layer. Wherein the stress release layer comprises N periods of BN/BxGa1-xN superlattice structure, 0.01<x<0.05, and N is an integer more than 2.
Wherein the growth temperature of the stress release layer can be 1100-1150 ℃. The growth temperature of the stress release layer is set to be in the range, so that the quality of the grown stress release layer can be ensured, and the effect of releasing the compressive stress in the undoped GaN layer by the stress release layer is further ensured.
The growth pressure of the stress relieving layer may be 100Torr to 200 Torr.
Optionally, the growth time of the BN sublayer is 25s, BxGa1-xThe growth time of the N sublayer was 15 s. A BN sublayer with BxGa1-xThe growth time of the N sublayer is set to be in the range, so that the quality of the grown stress release layer can be ensured, and the effect of releasing the compressive stress in the undoped GaN layer by the stress release layer is further ensured.
Optionally, the thickness of the stress release layer is 1-2 μm. The thickness of the stress release layer is set in the range, so that the stress release layer can effectively release compressive stress accumulated in the undoped GaN layer, and the overall quality of the epitaxial wafer is ensured.
Wherein BN/BxGa1-xIn the N superlattice structure, the thickness of the BN sublayer contained in the N superlattice structure is 5-10 nm, and BxGa1-xThe thickness of the N sublayer is 10-20 nm. BN sublayer and BxGa1-xThe thickness of the N sublayer is set in the range, so that tensile stress can be well formed in the total structure of the N sublayer, the compressive stress in the undoped GaN layer can be well released, and the quality and the light emitting effect of the light emitting diode are guaranteed.
Alternatively, BN/BxGa1-xThe period of the N superlattice structure is 30-40. Mixing BN/BxGa1-xThe period of the N superlattice structure is set to be 30-40 so that BN/B can be formedxGa1-xThe N superlattice structure has a good stress releasing effect, and the overall quality of the epitaxial wafer is guaranteed.
In particular, BN/B is grownxGa1-xThe process of the N superlattice structure may be: introducing TMB and a proper amount of NH into the reaction chamber under the conditions of 1100-1150 ℃ temperature and 100-200 Torr growth pressure3Growing BN self-layer, growing 25s BN sub-layer, introducing TMGa and TMB and appropriate amount of NH into the reaction chamber3Growth of 15s of BxGa1-xAnd N sublayers. Repeating the above process to obtain BN/BxGa1-xAn N superlattice structure.
The structure of the epitaxial wafer after the step S4 is completed may be as shown in fig. 3, and the structure includes a substrate 1, and an AlN buffer layer 2, an undoped GaN layer 3, and a stress relief layer sequentially stacked on the substrate 14, the stress release layer 4 comprises N periods of BN/BxGa1-xN superlattice structure, BN/BxGa1-xThe N-superlattice structure comprises a BN sublayer 41 and BxGa1-x An N sublayer 42.
S5: and growing an N-type GaN layer on the stress release layer.
Wherein the growth temperature of the N-type GaN layer can be 1100-1150 deg.C, and the growth pressure can be 200 Torr.
Optionally, the doping element of the N-type GaN layer is a Si element, and the doping concentration of the Si element is 1018cm-3-1019cm-3。
In the present embodiment, the thickness of the N-type GaN layer can be 2 to 3 μm. So that the N-type GaN layer can effectively provide sufficient carriers.
Optionally, the growth temperature of the stress release layer is greater than the growth temperature of the N-type GaN layer. The growth temperature of the stress release layer is set to be higher than that of the N-type GaN layer, so that preparation can be made for growth of the N-type GaN layer while growth quality of the stress release layer is guaranteed.
S6: and growing a multi-quantum well active layer on the N-type GaN layer.
Alternatively, the growth temperature of the multiple quantum well active layer may be 700 to 900 ℃. So as to ensure the quality of the grown multiple quantum well active layer.
Alternatively, the thickness of the multi-quantum well active region may be 100to 150 nm.
Illustratively, the multiple quantum well active layer may be a multiple quantum well layer including In alternately stackedaGa1-aAn N well layer and a GaN barrier layer of 0<a<1。
S7: and growing a P-type GaN layer on the multiple quantum well active layer.
Alternatively, the growth temperature of the P-type GaN layer can be 700-800 ℃, and the growth pressure can be 100Torr-300 Torr.
Further, the preparation method can also comprise the following steps:
and sequentially growing an electron blocking layer, a high-temperature P-type GaN layer and a P-type contact layer on the P-type GaN layer.
Wherein, the growth temperature of the electron blocking layer, the high-temperature P-type GaN layer and the P-type contact layer can be 950-1000 ℃, and the growth pressure can be 200 Torr.
In the present embodiment, the thickness of the electron blocking layer may be 200to 300nm, the thickness of the high temperature P-type GaN layer 9 may be 100to 200nm, and the thickness of the P-type contact layer 10 may be 500to 100 nm.
The schematic structural diagram of the epitaxial wafer after the above steps are performed can be shown in fig. 1, and the structure of the epitaxial wafer includes a substrate 1, and an AlN buffer layer 2, an undoped GaN layer 3, a stress release layer 4, an N-type GaN layer 5, a multiple quantum well active layer 6, a P-type GaN layer 7, an electron blocking layer 8, a high-temperature P-type GaN layer 9, and a P-type contact layer 10, which are sequentially stacked on the substrate 1.
Setting BN/B including N periods on an undoped GaN layerxGa1-xStress relief layer of N-superlattice structure, BN/BxGa1-xThe N superlattice structure accumulates tensile stress in the epitaxial layer, which can counteract partial compressive stress in the undoped GaN, thereby reducing linear defects and piezoelectric polarization caused by the compressive stress in the undoped GaN. The reduction of line defects in the epitaxial wafer can improve the quality of the epitaxial wafer, and the reduction of line defects can also greatly reduce the formation of non-radiative recombination centers of a multi-quantum well active region, so that the luminous efficiency is improved. The reduction of the piezoelectric polarization can also reduce the quantum well stark limiting effect (in a multi-quantum well structure, under the action of a built-in polarization electric field, the energy band of a semiconductor is inclined, and the luminous efficiency is reduced due to the spatial separation of electron-hole pairs and the reduction of the overlapping amount of wave functions) caused by the piezoelectric polarization and the spontaneous polarization in the epitaxial wafer, so that the luminous efficiency is improved.
Optionally, the preparation method can further comprise:
and after the growth of the epitaxial wafer is finished, annealing the epitaxial wafer in a nitrogen atmosphere, wherein the annealing temperature is 650-850 ℃, and the annealing time is 5-15 min. After the epitaxial wafer is grown, the epitaxial wafer is annealed, so that Mg atoms in the P-type GaN layer and the high-temperature P-type GaN layer can be activated, the hole concentration in the P-type GaN layer and the high-temperature P-type GaN layer is improved, and the luminous efficiency of the light-emitting diode is improved.
Optionally, the growth of the epitaxial layer in the embodiment of the present invention is implemented by metal organic chemical vapor deposition. However, in other embodiments of the present invention, the growth of the epitaxial layer in the embodiments of the present invention may also be implemented by using a method such as physical vapor deposition, which is not limited by the present invention.
Specifically, when the actual growth of the epitaxial wafer is realized, the substrate may be placed on a graphite tray and fed into the reaction chamber for the growth of the epitaxial material.
In the embodiment of the invention, trimethyl gallium or trimethyl ethylene can be used as a gallium source, high-purity nitrogen is used as a nitrogen source, trimethyl indium is used as an indium source, trimethyl aluminum is used as an aluminum source, and trimethyl borane is used as a B source; the N-type dopant is silane, and the P-type dopant is magnesium metallocene.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (8)

1. The light-emitting diode epitaxial wafer is characterized by comprising a substrate, and an AlN buffer layer, an undoped GaN layer, a stress release layer, an N-type GaN layer, a multi-quantum well active layer and a P-type GaN layer which are sequentially stacked on the substrate, wherein the stress release layer comprises N periods of BN/BxGa1-xN superlattice structure, 0.01<x<0.05, wherein N is an integer larger than 2, the thickness of the stress release layer is smaller than that of the N-type GaN layer, the thickness of the undoped GaN layer is 1 mu m, and the thickness of the stress release layer is 1-2 mu m.
2. Epitaxial wafer according to claim 1, characterized in that the BN/B is the one in whichxGa1-xIn the N superlattice structure, the thickness of BN sublayer is 5-10 nm, and BxGa1-xThe thickness of the N sublayer is 10-20 nm.
3. The epitaxial wafer of claim 1, wherein the stress relief layer comprises 30-40 cycles of BN/BxGa1-xAn N superlattice structure.
4. A preparation method of a light emitting diode epitaxial wafer is characterized by comprising the following steps:
providing a substrate;
growing an AlN buffer layer on the substrate;
growing an undoped GaN layer on the AlN buffer layer;
growing a stress release layer on the undoped GaN layer, wherein the stress release layer comprises N periods of BN/BxGa1-xN superlattice structure, 0.01<x<0.05, N is an integer greater than 2;
growing an N-type GaN layer on the stress release layer;
growing a multi-quantum well active layer on the N-type GaN layer;
and growing a P-type GaN layer on the multiple quantum well active layer.
5. The method according to claim 4, wherein the growth temperature of the stress release layer is 1100-1150 ℃.
6. The method according to claim 4, wherein a growth temperature of the stress release layer is higher than a growth temperature of the N-type GaN layer.
7. The method according to any one of claims 4 to 6, further comprising:
and before the epitaxial layer structure grows on the substrate, annealing the substrate in a hydrogen atmosphere.
8. The method according to any one of claims 4 to 6, further comprising:
and before growing an undoped GaN layer on the AlN buffer layer, carrying out in-situ annealing treatment on the AlN buffer layer.
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CN107046087B (en) * 2017-04-27 2019-06-11 华灿光电（浙江）有限公司 A kind of epitaxial wafer of light emitting diode and preparation method thereof

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