CN108807274A - 在共同衬底上具有不同功函数的非平面i/o和逻辑半导体器件 - Google Patents

在共同衬底上具有不同功函数的非平面i/o和逻辑半导体器件 Download PDF

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CN108807274A
CN108807274A CN201811024602.5A CN201811024602A CN108807274A CN 108807274 A CN108807274 A CN 108807274A CN 201811024602 A CN201811024602 A CN 201811024602A CN 108807274 A CN108807274 A CN 108807274A
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gate electrode
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CN108807274B (zh
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R·W·奥拉-沃
W·M·哈菲兹
C-H·简
P-C·刘
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Intel Corp
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Abstract

说明了在共同衬底上具有不同功函数的非平面I/O和逻辑半导体器件及制造在共同衬底上具有不同功函数的非平面I/O和逻辑半导体器件的方法。例如，一种半导体结构包括布置在衬底上的第一半导体器件。第一半导体器件具有导电类型，并包括具有第一功函数的栅极电极。半导体结构还包括布置在衬底上的第二半导体器件。第二半导体器件具有所述导电类型，并包括具有不同的第二功函数的栅极电极。

Description

在共同衬底上具有不同功函数的非平面I/O和逻辑半导体 器件
本申请为分案申请，其原申请是2016年2月22日进入中国国家阶段、国际申请日为2013年9月27日的国际专利申请PCT/US2013/062308，该原申请的中国国家申请号是201380079015.5，发明名称为“在共同衬底上具有不同功函数的非平面I/O和逻辑半导体器件”。
技术领域
本发明的实施例属于半导体器件和工艺领域，具体而言，属于在共同衬底上具有不同功函数的非平面I/O和逻辑半导体器件及在共同衬底上制造具有不同功函数的非平面I/O和逻辑半导体器件的方法。
背景技术
过去几十年中，集成电路中部件的规模缩小是日益增长的半导体工业背后的驱动力。到越来越小的部件的规模缩小实现了功能单元在半导体芯片的有限基板面上增大的密度。例如，收缩晶体管尺寸允许在芯片上包含增大数量的存储或逻辑器件，导致制造出具有增大容量的产品。但对于更大容量的驱策并非没有问题。优化每一个器件的性能的必要性变得日益显著。
在集成电路器件的制造中，随着器件尺寸不断缩小，诸如鳍式场效应晶体管(fin-FET)的多栅晶体管已经变得更为普遍。在传统工艺中，通常在大块硅衬底或绝缘体上硅结构衬底上制造fin-FET。在一些实例中，由于其较低的成本和与现有高产量大块硅衬底基础结构的兼容性，大块硅衬底是优选的。
但多栅晶体管的规模缩小并非没有后果。随着微电子电路的这些基本结构单元的尺寸减小，并且随着在给定区域中制造的基本结构单元的绝对数量增大，对用于制造这些结构单元的半导体工艺的约束变得令人难以应对。
附图说明
图1A示出了具有布置在共同衬底上的I/O晶体管和逻辑晶体管的半导体结构的非完整部分的横截面图。
图1B示出了根据本发明实施例的具有布置在共同衬底上的I/O晶体管和逻辑晶体管的半导体结构的非完整部分的横截面图。
图2A-2F示出了根据本发明实施例的在共同衬底上制造I/O晶体管和逻辑晶体管的方法中的多个操作的横截面图，其中：
图2A示出了具有在逻辑晶体管的栅极电极区中、但不在I/O晶体管的栅极电极区中形成的硬掩模的不完整半导体结构；
图2B示出了去除了功函数金属层在I/O晶体管的栅极电极区的部分的图2A的结构；
图2C示出了具有形成于其上的第二功函数金属层和第二硬掩模层的图2B的结构；
图2D示出了在凹陷第二硬掩模层后的图2C的结构；
图2E示出了在去除第二功函数层的露出部分后的图2D的结构；及
图2F示出了在去除硬掩模的剩余部分和第二硬掩模层后的图2E的结构。
图3A示出了根据本发明实施例的非平面半导体器件的横截面图。
图3B示出了根据本发明实施例的沿图3A的半导体器件的a-a’轴的平面图。
图4示出了根据本发明一个实现方式的计算设备。
具体实施方式
说明了在共同衬底上具有不同功函数的非平面I/O和逻辑半导体器件及在共同衬底上制造具有不同功函数的非平面I/O和逻辑半导体器件的方法。在以下说明中，阐述了多个特定细节，例如特定集成和材料状况，以便提供对本发明的实施例的透彻理解。对于本领域技术人员来说，显然，本发明的实施例的实践可以无需这些特定细节。在其他实例中，没有详细说明诸如集成电路设计布局的公知的特征，以免不必要地使得本发明的实施例模糊不清。而且，会理解，附图中所示的不同实施例是说明性表示，不一定按照比例绘制。
本文所述的一个或多个实施例针对为在共同衬底上制造的半导体器件的不同间距制造多个功函数(WF)的方案。可以应用于制造金属氧化物半导体(MOS)与具有由在共同衬底上公用工艺方案制造的I/O晶体管(例如驱动晶体管)和逻辑晶体管(例如运算晶体管)的结构。在一个示例中，与相应的逻辑晶体管相比，制造I/O晶体管以具有较大栅极长度和不同功函数。
为了提供背景，当前，在片上系统(SoC)集成电路中的不同器件的性能由不同间距、临界尺寸(CD)和注入调整控制。但相同导电类型(例如N型和P型)的所有器件具有相同的功函数(WF)。相反，本文所述的一个或多个实施例提供了为不同器件形成不同功函数图案的方案，实现了每一个器件类型的独立控制性能。
具体而言，一个或多个实施例利用在具有不同CD的不同结构之间碳硬掩模(CHM)的蚀刻速率相关性(例如较宽CD具有比较窄CD更快的蚀刻速率)。因而，可以为不同器件(例如I/O相对于逻辑器件)形成不同功函数层(例如金属栅极层)图案。于是，一个或多个实施例提供了为具有不同功能，例如I/O器件与逻辑器件，的相似器件(例如N型器件)实现不同实际栅极功函数的机会。通过区分器件之间的功函数，在不使用任何额外掩模操作的情况下，可以将每一个器件的性能独立地作为目标。
用于为具有不同功能的相似器件(例如N型器件)，例如I/O器件与逻辑器件，提供不同有效栅极功函数的以前方案包括使用衬底注入区别来控制不同器件的性能。示例性地，图1A示出了具有布置在共同衬底101A上并由层间电介质区103A分隔的I/O晶体管102A和逻辑晶体管104A的半导体结构100A的非完整部分的横截面图。参考图1A，I/O晶体管102A形成于第一鳍状物106A上，逻辑晶体管104A形成于第二鳍状物108A上。在所示的具体示例中，I/O晶体管102A具有三个相对较宽的栅极电极区110A、112A和114A(横截面图显示了在源/漏区之间得到的栅极长度111A)。下层鳍状物106A可以包括外延源/漏区116A，如所示的。同时，逻辑晶体管104A具有三个相对较窄的栅极电极区120A、122A和124A(横截面图显示了在源/漏区之间得到的栅极长度121A)。下层鳍状物108A还可以包括外延源/漏区126A，如所示的。
再次参考图1A，在所示的处理点，执行了取代栅极工艺，其中，在栅极电极区110A、112A、114A、120A、122A和124A以功函数金属层118A取代虚拟栅极材料。但功函数金属层118A对于I/O晶体管102A和逻辑晶体管104A的栅极电极区是相同的。因此，为了区分I/O晶体管102A和逻辑晶体管104A的有效功函数，使用了诸如鳍状物掺杂区别的方案。会理解，随后可以执行额外的处理以完成图1A的器件，例如栅极填充、触点形成和后端工艺(BEOL)互连制造。
与相关于图1A所述的布置相反，图1B示出了根据本发明实施例的具有布置在共同衬底101B上并由层间电介质区103B分隔的I/O晶体管102B和逻辑晶体管104B的半导体结构100B的非完整部分的横截面图。参考图1B，I/O晶体管102B形成于第一鳍状物106B上，逻辑晶体管104B形成于第二鳍状物108B上。在所示的具体示例中，I/O晶体管102B具有三个相对较宽的栅极电极区110B、112B和114B(横截面图显示了在源/漏区之间得到的栅极长度111B)。下层鳍状物106B可以包括外延源/漏区116B，如所示的。同时，逻辑晶体管104B具有三个相对较窄的栅极电极区120B、122B和124B(横截面图显示了在源/漏区之间得到的栅极长度121B)。下层鳍状物108B还可以包括外延源/漏区126B，如所示的。
再次参考图1B，在所示的处理点，执行了取代栅极工艺，其中，在逻辑晶体管104B的栅极电极区120B、122B和124B以功函数金属层118B取代虚拟栅极材料。但在实施例中，I/O晶体管102B的栅极电极区110B、112B和114B包括不同功函数金属层119，甚至对于相同导电类型器件(即在I/O晶体管102B和逻辑晶体管104B都是N型，或者I/O晶体管102B和逻辑晶体管104B都是P型的情况下)。在实施例中，功函数金属层119具有的实际功函数与功函数金属层118B的实际功函数不同。在一个此类实施例中，功函数金属层119具有的厚度与功函数金属层118B的厚度不同(如所示的)。在另一个此类实施例中，功函数金属层119具有的总材料成分与功函数金属层118B的总材料成分不同。在再另一个实施例中，功函数金属层119在厚度和总材料成分方面都与功函数金属层118B不同。在一个具体实施例中，I/O晶体管102B和逻辑晶体管104B都是N型器件，功函数金属层119由与功函数金属层118B基本上相同的材料组成，比功函数金属层118B更厚；与功函数金属层118B的实际功函数相比，功函数金属层119的实际功函数从N型向带隙中值(mid-gap)移动约在50-80毫伏范围中的量。会理解，随后可以执行额外的处理以完成图1B的器件，例如栅极填充、触点形成和后端工艺(BEOL)互连制造。还会理解，尽管未示出，但栅极电介质层可以分别布置在功函数金属层118B和119及鳍状物108B和106B之间。
在一个方面，半导体制造方案可以包括为相似导电类型的不同功能器件制造不同功函数层。示例性地，图2A-2F示出了根据本发明实施例的在共同衬底上制造I/O晶体管和逻辑晶体管的方法中的多个操作的横截面图。
参考图2A，半导体结构的非完整部分200包括布置在共同衬底201上的I/O晶体管202和逻辑晶体管204。I/O晶体管202形成于第一鳍状物206上，逻辑晶体管204形成于第二鳍状物208上。在所示的具体示例中，I/O晶体管202具有三个相对较宽的栅极电极区210、212和214(横截面图显示了在源/漏区之间得到的栅极长度211)。下层鳍状物206可以包括外延源/漏区216，如所示的。同时，逻辑晶体管204具有三个相对较窄的栅极电极区220、222和224(横截面图显示了在源/漏区之间得到的栅极长度221)。下层鳍状物208还可以包括外延源/漏区226，同样如所示的。
再次参考图2A，在所示的处理点，执行了取代栅极工艺，其中，在栅极电极区210、212、214、220、222和224以功函数金属层218取代虚拟栅极材料。会理解，在这个阶段，功函数金属层218的实际功函数对于I/O晶体管202和逻辑晶体管204的栅极电极区是相同的。具体而言，对于I/O晶体管202和逻辑晶体管204，在同时并在相同的过程操作中形成功函数金属层218。还会理解，尽管未示出，但栅极电介质层可以布置在功函数层218与鳍状物208和206B之间。图2A中还显示了栅极电极分隔区228和层间电介质区229。
再次参考图2A，硬掩模层230形成于不完整的半导体结构200的部分上。具体而言，硬掩模层230形成于I/O晶体管202和逻辑晶体管204之间，更重要的，在逻辑晶体管204的栅极电极位置220、222和224内。但硬掩模层230没有形成在I/O晶体管202的栅极电极位置210、212和214中(或者去除了)，如所示的。根据本发明的实施例，首先全面形成硬掩模层，即首先在I/O晶体管202与逻辑晶体管204之间、在逻辑晶体管204的栅极电极位置220、222和224内、及在I/O晶体管202的栅极电极位置210、212和214内形成硬掩模层230。随后去除硬掩模层230在I/O晶体管202的栅极电极位置210、212和214内的部分。在一个此类实施例中，首先借助旋涂工艺全面地形成硬掩模层230。随后对于其他存在的材料和部件有选择性地蚀刻旋涂层以减小层的高度。在一个示例中，在不同部件位置的蚀刻速率可以不同。因而，在一个实施例中，硬掩模层从较宽部件210、212和214比从相对较窄部件220、222和224蚀刻得更快。因此，可以从较宽部件210、212和214完全去除旋涂层，而在较窄部件220、222和224中保留一部分旋涂层，如所示的。会理解，在蚀刻过程中可以去除旋涂层在器件202与204之间的部分，而不是保留。在实施例中，硬掩模层230基本上由碳组成，称为碳硬掩模(CHM)层。
参考图2B，去除功函数金属层218在栅极电极区210、212和214(即在I/O晶体管202)的部分。在实施例中，对于硬掩模层230有选择性地去除功函数金属层218在栅极电极区210、212和214的部分。在一个此类实施例中，在逻辑晶体管204，同样去除了功函数金属层218没有由硬掩模层230保护的上部，如所示的。而且，如果栅极电介质层存在于鳍状物206上，可以在此时去除它，或者可以保留它。在实施例中，借助选择性蚀刻工艺去除功函数金属层218露出的部分，例如湿法蚀刻工艺、干法蚀刻工艺或其组合。
参考图2C，第二功函数层240形成于图2B的结构上。具体而言，第二功函数层240形成于I/O晶体管202的栅极电极位置210、212和214中。另外，第二功函数金属层240可以形成于在逻辑晶体管的栅极电极位置220、222和224中剩余的功函数金属层218和硬掩模层230露出的部分上，如图2C所示的。在实施例中，第二功函数金属层240具有的实际功函数与功函数金属层218的实际功函数不同。在一个此类实施例中，第二功函数金属层240具有的厚度与功函数金属层218的厚度不同(如所示的)。在另一个此类实施例中，第二功函数金属层240具有的总材料成分与功函数金属层218的总材料成分不同。在再另一个实施例中，第二功函数金属层240在厚度和总材料成分方面都与功函数金属层218不同。在一个具体实施例中，I/O晶体管202和逻辑晶体管204都是N型器件，第二功函数金属层240由与功函数金属层218基本上相同的材料组成，但比功函数金属层118B更厚；与功函数金属层218的实际功函数相比，第二功函数金属层240的实际功函数从N型向带隙中值移动约在50-80毫伏范围中的量。
会理解，在从图2B的I/O晶体管去除了栅极电介质层的情况下，可以就在形成第二功函数金属层240之前形成栅极电介质层。再次参考图2C，随后在第二功函数金属层240上形成第二硬掩模层242。在一个此类实施例中，第二硬掩模层242由与硬掩模层230相同的材料或基本上相同的材料组成。例如，在一个此类实施例中，第二硬掩模层242是碳硬掩模层。
参考图2D，蚀刻第二硬掩模层242以使得I/O晶体管202的栅极电极区210、212和214中的部分凹陷。在逻辑晶体管204的情况下，蚀刻从逻辑晶体管204的栅极电极区220、222和224去除第二硬掩模层242。而且，第二硬掩模层242的凹陷露出了第二功函数金属层240在I/O晶体管202和逻辑晶体管204的部分。在实施例中，借助选择性蚀刻工艺使得第二硬掩模层242凹陷，例如湿法蚀刻工艺、干法蚀刻工艺或其组合。
参考图2E，从I/O晶体管202和逻辑晶体管204去除第二功函数金属层240在使得第二硬掩模层242凹陷后露出的部分。在实施例中，借助选择性蚀刻工艺去除第二硬掩模层242露出的部分，例如湿法蚀刻工艺、干法蚀刻工艺或其组合。
参考图2F，去除硬掩模层230和第二硬掩模层242剩余的部分。这个去除在I/O晶体管202的栅极电极区210、212和214中露出了形成并图案化的第二功函数金属层240，还在逻辑晶体管204的栅极电极区220、222和224中露出了形成并图案化的功函数金属层218。在实施例中，借助选择性蚀刻工艺去除硬掩模层230和第二硬掩模层242剩余的部分，例如湿法蚀刻工艺、干法蚀刻工艺或其组合。再次参考图2F，在晶体管之间显示了电介质区230’。尽管区230’可以是保留的硬掩模区，但也可以去除这个区，随后以层间电介质材料代替。还会理解，随后可以执行额外的处理以完成图2F的器件，例如栅极填充、触点形成和后端工艺(BEOL)互连制造。
总体上，再次参考图2A-2F，在实施例中，所述的方案可以用于N型(例如NMOS)或P型(例如PMOS)或二者器件制造。会理解，从以上示例性处理方案得到的结构，例如得自图2F的结构，可以以相同或相似的形式用于随后的处理操作，以完成器件制造，例如PMOS和NMOS器件制造。作为完成的器件的示例，图3A和3B分别示出了根据本发明实施例的非平面半导体器件的横截面图和平面图(沿横截面图的半导体器件得到的)，例如完成形式的I/O器件202或逻辑器件204。会注意到，图3A的横截面图是垂直于图2F的横截面图得到的，沿栅极线210、212、214、220、222或224任意之一得到。而且，在图3A和3B中所示的示例中，栅极线覆盖三个不同半导体鳍状物。
参考图3A，例如完成形式的I/O晶体管202或逻辑晶体管204的半导体结构或器件300包括非平面有源区(例如鳍状物结构，包括突出鳍状物部分304和鳍状物下区域305)，从衬底302形成并在隔离306内。
再次参考图3A，栅极线308布置在非平面有源区的突出鳍状物部分304上以及一部分隔离区306上。如所示的，栅极线308包括栅极电极350和栅极电介质层352。在一个实施例中，栅极线308还可以包括电介质端盖层354。还可以从这个透视图中见到栅极触点314和上覆栅极触点通孔316，连同上覆金属互连360，它们全都布置在层间电介质叠层或层370中。由图3A的透视图同样见到，在一个实施例中，栅极触点314布置在隔离区360上，但没有在非平面有源区上。如所示的，将鳍状物304认为是大块鳍状物，因为它们从下层衬底302延伸。在其他实施例中，从绝缘体上硅结构(SOI)型衬底形成鳍状物，从而布置在全部绝缘体层上。
参考图3B，将栅极线308显示为布置在突出鳍状物部分304上。可以从这个透视图见到突出鳍状物部分304的源极和漏极区304A和304B。在一个实施例中，源极和漏极区304A和304B是突出鳍状物部分304的原始材料的掺杂部分。在另一个实施例中，例如借助外延沉积去除了突出鳍状物部分304的材料，并代之以另一个半导体材料。在任一情况下，源极和漏极区304A和304B都可以在电介质层306的高度下延伸，即在大块型器件的情况下进入鳍状物下区域305中。可替换地，源极和漏极区304A和304B没有在电介质层306的高度下延伸，或者在电介质层306的高度上或者与之共面。
在一个实施例中，半导体结构或器件300是非平面器件，例如但不限于fin-FET或三栅或类似地器件。在这个实施例中，相应的半导体沟道区由三维基体组成或在其中形成。在一个此类实施例中，栅极线308的栅极电极叠层至少围绕三维基体的顶面和一对侧壁，如图3A所示的。
结合图2A-2F及3A所述的衬底201和302分别可以由半导体材料组成，其可以经受制造过程，并且电荷可以在其中迁移。在一个实施例中，衬底201和302是大块衬底，由以电荷载流子掺杂的晶体硅、硅/锗或锗层组成，电荷载流子例如但不限于，磷、砷、硼或其组合。在一个实施例中，大块衬底201或302中硅原子的浓度大于97％。在另一个实施例中，大块衬底201或302由在不同晶体衬底顶上生长的外延层组成，例如在硼掺杂的大块硅单晶衬底顶上生长的硅外延层。大块衬底201或302可以可替换地由III-V族材料组成，例如但不限于，氮化镓、磷化镓、砷化镓、磷化铟、锑化铟、砷化镓铟、砷化镓铝、磷化镓铟或其组合。在一个实施例中，大块衬底201或302由III-V族材料组成，电荷载流子掺杂剂杂质原子是例如但不限于，碳、硅、锗、氧、硫、硒或碲。可替换地，代替大块衬底，可以使用绝缘体上硅结构(SOI)衬底。在此情况下，图2A-2F中所示的区域201是全局隔离层。
隔离区306可以由适合于最终将永久栅极结构的部分与下层大块衬底电隔离或有助于隔离的，或者隔离在下层大块衬底内形成的有源区，例如隔离鳍状物有源区，的材料组成。例如，在一个实施例中，隔离区306由电介质材料组成，例如但不限于，二氧化硅、氮氧化硅、氮化硅、或碳掺杂的氮化硅。
栅极线308可以由栅极电极叠层组成，其包括栅极电介质层352和栅极电极层350(例如功函数金属层218或240)。在一个实施例中，栅极电极叠层的栅极电极由金属栅极组成，栅极电介质由高K材料组成。例如，在一个实施例中，栅极电介质层由诸如但不限于氧化铪、氮氧化铪、硅酸铪、氧化镧、氧化锆、硅酸锆、氧化钽、钛酸锶钡、钛酸钡、钛酸锶、氧化钇、氧化铝、钽酸钪铅、和铌酸锌铅或其组合组成。而且，一部分栅极电介质层可以包括一层的本征氧化物，其由覆层302的顶部几层形成。在一个实施例中，栅极电介质层由高-k上部和下部组成，下部由半导体材料的氧化物组成。在一个实施例中，栅极电介质层由氧化铪的上部和氧化硅或氮氧化硅的下部组成。
在一个实施例中，栅极电极层250(例如功函数金属层218或240)由金属层组成，例如但不限于，金属氮化物、金属碳化物、金属硅化物、金属铝化物、铪、锆、钛、钽、铝、钌、钯、铂、钴、镍、或导电金属氧化物。在一个特定实施例中，栅极电极由在金属功函数设定层上形成的非功函数设定填充材料组成。
与栅极电极叠层相关的分隔区(图2A-2F中显示为228)可以由适合于最终将永久栅极结构与诸如自对准触点的相邻导电触点电隔离或者有助于隔离的材料组成。例如，在一个实施例中，分隔区由电介质材料组成，例如但不限于氧化硅、氮氧化硅、氮化硅或硼掺杂的氮化硅。
栅极触点314和上覆栅极触点通孔316可以由导电材料组成。在一个实施例中，一个或多个触点或通孔由金属类组成。金属类可以是诸如钨、镍或钴的纯金属，或者可以是合金，例如金属-金属合金或者金属-半导体合金(例如硅化物材料)。
在一个实施例中，栅极线308(或线210、212、214、220、222或224)首先借助多晶硅栅极图案化形成，包括多晶硅光刻以借助随后的SiN硬掩模和多晶硅的蚀刻来限定多晶硅栅极。在一个实施例中，掩模形成于硬掩模层上，掩模由形貌遮掩部分和抗反射涂层(ARC)组成。在一个此类特定实施例中，形貌遮掩部分是碳硬掩模(CHM)层，抗反射涂层是硅ARC层。形貌遮掩部分和ARC层可以借助传统光刻和蚀刻工艺技术来形成图案。在一个实施例中，掩模还包括最上面的光致抗蚀剂层，如本领域中已知的，并可以借助传统光刻和显影工艺来形成图案。在一个特定实施例中，光致抗蚀剂层暴露于光源的部分在显影光致抗蚀剂层后被去除。因而，形成图案的光致抗蚀剂层由正性光致抗蚀剂材料组成。在一个特定实施例中，光致抗蚀剂层由正性光致抗蚀剂材料组成，例如但不限于，248nm抗蚀剂，193nm抗蚀剂，157nm抗蚀剂，极远紫外(EUV)抗蚀剂、e-束印记层和具有邻叠氮萘醌敏化剂的酚醛树脂基体。在另一个特定实施例中，光致抗蚀剂层暴露于光源的部分在显影光致抗蚀剂层后保留。因而，光致抗蚀剂层由负性光致抗蚀剂材料组成。在一个特定实施例中，光致抗蚀剂层由负性光致抗蚀剂材料组成，例如但不限于，由聚－顺式－异戊二烯或聚－乙烯基－肉桂酸组成。
而且，如简要结合图2A提及的，栅极叠层结构308(和栅极电极位置210、212、214、220、222和224)可以由取代栅极工艺制造。在这个方案中，可以去除诸如多晶硅或氮化硅支柱材料的虚拟栅材料，并以永久栅极电极材料代替。在一个此类实施例中，在这个过程中还形成永久栅极电介质层，与通过较早处理完成相反。在一个实施例中，借助干法蚀刻或湿法蚀刻工艺去除虚拟栅。在一个实施例中，虚拟栅由多晶硅或非晶硅组成，借助包括使用SF6的干法蚀刻工艺去除。在另一个实施例中，虚拟栅由多晶硅或非晶硅组成，借助包括使用NH4OH水溶液或氢氧化四甲铵的湿法蚀刻工艺去除。在一个实施例中，虚拟栅由氮化硅组成，借助包括磷酸水溶液的湿法蚀刻去除。
在一个实施例中，本文所述的一个或多个方案实质上设想了虚拟和取代栅极工艺结合虚拟和取代触点工艺。在一个此类实施例中，在取代栅极工艺之后执行取代触点工艺，以允许至少一部分永久栅极叠层的高温退火。例如，在一个此类具体实施例中，例如在形成栅极电介质层之后，以大于约600摄氏度的温度执行至少一部分永久栅极结构的退火。
再次参考图3A，半导体结构或器件300的布置将栅极触点设置在隔离区上。这个布置可以视为布局空间的无效使用。但在另一个实施例中，半导体器件具有接触栅极电极形成于有源区上的部分的触点结构。
通常，在栅极的有源部分上并与沟槽触点通孔在同一层中形成栅极触点结构(例如通孔)之前(例如除此之外)，本发明的一个或多个实施例包括首先使用栅极对准沟槽触点工艺。可以实施这个工艺来为半导体结构制造，例如集成电路制造，形成沟槽触点结构。在一个实施例中，将沟槽触点图案形成为与现有栅极图案对准。相反，传统方案典型地包括额外的光刻工艺，借助光刻触点图案与现有栅极图案的严格配准，并结合选择性触点蚀刻。例如，传统工艺可以包括多(栅极)栅的图案化与触点部件的单独图案化。
会理解，并非需要实践上述工艺的全部方案以属于本发明的实施例的精神和范围内。例如，在一个实施例中，在栅极叠层的有源部分上制造栅极触点之前不必形成虚拟栅。上述的栅极叠层实际上可以是初始形成的永久栅极叠层。此外，本文所述的工艺可以用于制造一个和多个半导体器件。半导体器件可以是晶体管或类似器件。
例如，在一个实施例中，半导体器件是金属氧化物半导体场效应晶体管(MOS)晶体管，用于逻辑器件或存储器，或者是双极型晶体管。此外，在一个实施例中，半导体器件具有三维架构，例如fin-FET器件、三栅器件或独立访问的双栅极器件。一个或多个实施例尤其可以用于包括在片上系统(SoC)产品中的器件。另外，会理解，结合图2A-2F所述的处理方案也可以适用于平面器件制造。
总体上，本文所述的实施例提供了用于为不同器件制造不同功函数的方案。一个或多个实施例增强了能力，独立地将每一个器件的虚拟作为目标，无需其他掩模操作的额外成本。
图4示出了根据本发明一个实现方式的计算设备400。计算设备400容纳板402。板402可以包括多个组件，包括但不限于，处理器404和至少一个通信芯片406。处理器404物理且电耦合到板402。在一些实现方式中，至少一个通信芯片406也物理且电耦合到板402。在进一步的实现方式中，通信芯片406是处理器404的一部分。
取决于其应用，计算设备400可以包括其他组件，其会或不会物理且电耦合到板402。这些其他组件包括但不限于，易失性存储器(例如，DRAM)、非易失性存储器(例如ROM)、闪存、图形处理器、数字信号处理器、加密处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编码解码器、视频编码解码器、功率放大器、全球定位系统(GPS)设备、指南针、加速度计、陀螺仪、扬声器、相机和大容量储存设备(例如，硬盘驱动器、光盘(CD)、数字多用途盘(DVD)等等)。
通信芯片406实现了无线通信，用于往来于计算设备400传送数据。术语“无线”及其派生词可以用于描述可以例如通过非固态介质借助使用调制电磁辐射传送数据的电路、设备、系统、方法、技术、通信信道等。该术语并非暗示相关设备不包含任何导线，尽管在一些实施例中它们可以不包含。通信芯片406可以实施多个无线标准或协议中的任意一个，包括但不限于，Wi-Fi(IEEE 802.11族)、WiMAX(IEEE 802.16族)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其派生物，以及被指定为3G、4G、5G及之后的任何其他无线协议。计算设备400可以包括多个通信芯片406。
例如，第一通信芯片406可以专用于近距离无线通信，例如Wi-Fi和蓝牙，第二通信芯片406可以专用于远距离无线通信，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等。
计算设备400的处理器404包括封装在处理器404内的集成电路晶片。在本发明的实施例的一些实现方式中，处理器的集成电路晶片包括一个或多个器件，例如根据本发明的实现方式构成的MOS-FET晶体管。术语“处理器”可以指代任何设备或设备的部分，其处理来自寄存器和/或存储器的电子数据，将该电子数据转变为可以存储在寄存器和/或存储器中的其他电子数据。
通信芯片406也包括封装在通信芯片406内的集成电路晶片。根据本发明的另一个实现方式，通信芯片的集成电路晶片包括一个或多个器件，例如根据本发明的实现方式构成的MOS-FET晶体管。
在进一步的实现方式中，容纳在计算设备400中的另一个组件可以包含集成电路晶片，其包括一个或多个器件，例如根据本发明的实现方式构成的MOS-FET晶体管。
在多个实施例中，计算设备400可以是膝上型电脑、上网本电脑、笔记本电脑、超级本电脑、智能电话、平板电脑、个人数字助理(PDA)、超移动PC、移动电话、台式计算机、服务器、打印机、扫描器、监视器、机顶盒、娱乐控制单元、数码相机、便携式音乐播放器、或数码摄像机。在进一步的实现方式中，计算设备400可以是处理数据的任何其他电子设备。
因而，本发明的实施例包括在共同衬底上具有不同功函数的非平面I/O和逻辑半导体器件及制造在共同衬底上具有不同功函数的非平面I/O和逻辑半导体器件的方法。
在一个实施例中，一种半导体结构包括第一半导体器件，所述第一半导体器件布置在衬底上。第一半导体器件具有导电类型，并包括具有第一功函数的栅极电极。半导体结构还包括第二半导体器件，所述第二半导体器件布置在衬底上。第二半导体器件具有导电类型，并包括具有不同的第二功函数的栅极电极。
在一个实施例中，所述第一半导体器件是I/O晶体管，所述第二半导体器件是逻辑晶体管。
在一个实施例中，具有第一功函数的栅极电极包括具有厚度的第一功函数金属层，具有第二功函数的栅极电极包括具有厚度的第二功函数金属层，第一功函数金属层的厚度与第二功函数金属层的厚度不同。
在一个实施例中，具有第一功函数的栅极电极包括具有总材料成分的第一功函数金属层，具有第二功函数的栅极电极包括具有总材料成分的第二功函数金属层，第一功函数金属层的总材料成分与第二功函数金属层的总材料成分不同。
在一个实施例中，具有第一功函数的栅极电极包括具有总材料成分和厚度的第一功函数金属层，具有第二功函数的栅极电极包括具有总材料成分和厚度的第二功函数金属层，第一功函数金属层的总材料成分和厚度与第二功函数金属层的总材料成分和厚度不同。
在一个实施例中，所述导电类型是N型。
在一个实施例中，具有第一功函数的栅极电极包括具有厚度的第一功函数金属层，具有第二功函数的栅极电极包括具有厚度的第二功函数金属层。第一功函数金属层的厚度大于第二功函数金属层的厚度，第一功函数比第二功函数更靠近带隙中值约在50-80毫伏范围中的量。
在一个实施例中，第一半导体器件的栅极电极具有的栅极长度与第二半导体器件的栅极电极的栅极长度不同。
在一个实施例中，第一半导体器件和第二半导体器件都是fin-FET或三栅器件。
在一个实施例中，一种片上系统(SoC)集成电路包括N型I/O晶体管，所述N型I/O晶体管布置在衬底上，所述N型I/O晶体管包括具有第一功函数和第一栅极长度的栅极电极。N型逻辑晶体管布置在衬底上，所述N型逻辑晶体管包括具有第二较低功函数和小于第一栅极长度的第二栅极长度的栅极电极。
在一个实施例中，具有第一功函数的栅极电极包括具有厚度的第一功函数金属层，具有第二功函数的栅极电极包括具有厚度的第二功函数金属层，第一功函数金属层的厚度大于第二功函数金属层的厚度。
在一个实施例中，具有第一功函数的栅极电极包括具有总材料成分的第一功函数金属层，具有第二功函数的栅极电极包括具有总材料成分的第二功函数金属层，第一功函数金属层的总材料成分与第二功函数金属层的总材料成分不同。
在一个实施例中，具有第一功函数的栅极电极包括具有总材料成分和厚度的第一功函数金属层，具有第二功函数的栅极电极包括具有总材料成分和厚度的第二功函数金属层，第一功函数金属层的总材料成分和厚度与第二功函数金属层的总材料成分和厚度不同。
在一个实施例中，第一功函数比第二功函数更靠近带隙中值约在50-80毫伏范围中的量。
在一个实施例中，第一半导体器件和第二半导体器件都是fin-FET或三栅器件。
在一个实施例中，一种制造半导体结构的方法包括在衬底上形成第一半导体鳍状物和第二半导体鳍状物。所述方法还包括在所述第一半导体鳍状物上形成具有第一间距的第一多条栅极线，在所述第二半导体鳍状物上形成具有第二较窄间距的第二多条栅极线，第一多条栅极线和第二多条栅极线都包括一个导电类型的第一功函数金属层。所述方法还包括在所述第一多条栅极线中，但不在所述第二多条栅极线中，以所述导电类型的第二功函数金属层取代所述导电类型的第一功函数金属层。
在一个实施例中，形成第一多条栅极线和第二多条栅极线包括使用取代栅极技术(replacement gate technique)。
在一个实施例中，以所述导电类型的第二功函数金属层取代所述导电类型的第一功函数金属层包括在所述第二多条栅极线中，但不在所述第一多条栅极线中，遮掩所述导电类型的一部分第一功函数金属层。
在一个实施例中，在所述第二多条栅极线中遮掩所述导电类型的一部分第一功函数金属层包括形成并蚀刻碳硬掩模。在所述第二多条栅极线中的碳硬掩模的蚀刻速率比在所述第一多条栅极线中的碳硬掩模的蚀刻速率慢。
在一个实施例中，以所述导电类型的第二功函数金属层取代所述导电类型的第一功函数金属层包括蚀刻所述导电类型的第一功函数金属层，形成所述导电类型的第二功函数金属层，所述第二功函数金属层的厚度大于所述导电类型的第一功函数金属层的厚度。
在一个实施例中，所述方法进一步包括由所述第一半导体鳍状物和第一多条栅极线形成I/O晶体管。所述方法还包括由所述第二半导体器件和第二多条栅极线形成逻辑晶体管。
在一个实施例中，形成I/O晶体管包括形成N型I/O晶体管，形成逻辑晶体管包括形成N型逻辑晶体管。

Claims (7)

1.一种集成电路结构，包括：
具有第一鳍状物的第一N型fin-FET器件，所述第一N型fin-FET器件包括具有第一层的第一栅极电极，所述第一层具有成分，所述第一层具有第一厚度；以及
具有第二鳍状物的第二N型fin-FET器件，所述第二N型fin-FET器件包括具有第二层的第二栅极电极，所述第二层具有所述成分，所述第二层具有大于所述第一厚度的第二厚度，其中，所述第二N型fin-FET器件的所述第二栅极电极的栅极长度大于所述第一N型fin-FET器件的所述第一栅极电极的栅极长度。
2.根据权利要求1所述的集成电路结构，其中，所述第一N型fin-FET器件是逻辑晶体管，并且所述第二N型fin-FET器件是I/O晶体管。
3.根据权利要求1所述的集成电路结构，还包括：
位于所述第一鳍状物与所述第一栅极电极之间的第一栅极电介质；以及
位于所述第二鳍状物与所述第二栅极电极之间的第二栅极电介质。
4.根据权利要求1所述的集成电路结构，其中，所述第一栅极电介质和所述第二栅极电介质包括铪和氧。
5.根据权利要求1所述的集成电路结构，其中，所述第一层和所述第二层包括铝。
6.根据权利要求1所述的集成电路结构，其中，所述第一层和所述第二层包括钛。
7.根据权利要求1所述的集成电路结构，其中，所述第一层和所述第二层包括金属碳化物。
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