CN108807271A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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Publication number
CN108807271A
CN108807271A CN201810234683.5A CN201810234683A CN108807271A CN 108807271 A CN108807271 A CN 108807271A CN 201810234683 A CN201810234683 A CN 201810234683A CN 108807271 A CN108807271 A CN 108807271A
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China
Prior art keywords
layer
film
fin structure
insulating film
semiconductor device
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CN201810234683.5A
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庄国胜
周友华
鬼木悠丞
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体装置的制造方法，包含形成第一绝缘膜在第一鳍结构上及形成第二绝缘膜在第二鳍结构上，涂布保护层在第二绝缘膜上，去除第一绝缘膜以暴露一部分的第一鳍结构，以及使用非水溶剂基化学品形成第一氧化物膜在第一鳍结构的暴露部分上。

Description

半导体装置的制造方法
技术领域
本揭露是有关于一种半导体装置的制造方法及一种半导体集成电路。
背景技术
当半导体装置，例如金属-氧化物-半导体场效晶体管(MOSFET)或金属氧化物半导体(MOS)电容器透过各种技术节点缩小时，使用高介电常数κ(高-κ)介电质(与二氧化硅相比)及导电材料来形成栅极结构。在栅极结构中，使用介面层来改善基板表面和高-κ介电质之间的介面以减少损伤和缺陷。介面层还被设置以抑制半导体装置中通道载流子的迁移率下降且有助于提升装置性能的稳定性。
发明内容
根据本揭露的一实施方式，提供一种半导体装置的制造方法，包含形成第一绝缘膜在第一鳍结构上及形成第二绝缘膜在第二鳍结构上，涂布保护层在第二绝缘膜上，去除第一绝缘膜以暴露一部分的第一鳍结构，以及使用非水溶剂基化学品形成第一氧化物膜在第一鳍结构的暴露部分上。
附图说明
当读到随附的附图时，从以下详细的叙述可充分了解本揭露的各方面。值得注意的是，根据工业上的标准实务，各种特征不是按比例绘制。事实上，为了清楚的讨论，各种特征的尺寸可任意增加或减少。
图1为根据本揭露的各种实施方式绘示的半导体装置截面图；
图2为根据本揭露的各种实施方式绘示的半导体装置的制造方法流程图；
图3A-3H为根据本揭露的各种实施方式绘示的半导体装置的制程各步骤截面图；
图4为根据本揭露的各种实施方式绘示的半导体装置截面图。
具体实施方式
以下将以附图揭露本揭露的多个实施方式，为明确说明起见，许多实务上的细节将在以下叙述中一并说明。然而，应了解到，这些实务上的细节不应用以限制本揭露。也就是说，在本揭露部分实施方式中，这些实务上的细节是非必要的。此外，为简化图示起见，一些已知惯用的结构与元件在图示中将以简单示意的方式绘示之。
在本文中使用空间相对用语，例如“下方”、“之下”、“上方”、“之上”等，这是为了便于叙述一元件或特征与另一元件或特征之间的相对关系，如图中所绘示。这些空间上的相对用语的真实意义包含其他的方位。例如，当图示上下翻转180度时，一元件与另一元件之间的关系，可能从“下方”、“之下”变成“上方”、“之上”。此外，本文中所使用的空间上的相对叙述也应作同样的解释。
数十年来，二氧化硅(SiO2)已被用作金氧半场效晶体管(MOSFET)中的栅极介电膜。由于装置特征(例如通道长度及装置之间的间距)的尺寸减少，为了维持栅极电容及临界电压(Vt)，栅极介电膜的厚度也已减少。由于上述的一或多个特征尺寸的减少，漏电流急遽增加，导致更多的功率消耗及装置可靠性(例如，时间相关介电层崩溃(time dependentdielectric breakdown；TDDB)下降。为了提供在物理上较厚，具有与二氧化硅相同等效氧化物厚度(EOT)及电容等效厚度(CET)的栅极介电膜，以高k介电膜取代二氧化硅。形成介面层(IL)在高k介电膜及基板之间以钝化基板表面处的悬键(dangling bonds)并且提供低介面缺陷密度(interface trap density；Dit)的介面。介面层也用于形成阻挡介面反应及扩散到装置的通道区域中的屏障。然而，当介面层包含水溶性(即可被水去除)材料时，涉及湿式氧化制程和/或光阻剥除制程的水溶液将导致介面层的损耗，从而不利地影响装置性能和/或增加掺杂剂及杂质通过高k介电膜扩散的可能性。
在一些实施方式中，在湿式氧化制程中使用非水溶剂基化学品(non-aqueoussolvent-based chemical)以帮助避免介电层损耗。与其他方法相比，介面层损耗的减少在介面处的高K介电膜中具有更少的电荷/陷阱(charges/traps)、更平滑的表面及更小的临界电压偏移(Vt shift)。在一些实施方式中，同时在湿式氧化制程及光阻剥除制程中使用非水溶剂基化学品，与其他方法相比，导致制造成本和/或处理时间的减少。
图1为根据本揭露的各种实施方式绘示的半导体装置100截面图。半导体装置100包含分成第一操作区120A及第二操作区120B的基板110、多个鳍结构111a、111b、111c及111d(统称为鳍结构111)以及栅极结构122a、122b、122c及122d(统称为栅极结构122)。在互补式金属氧化物半导体(COMS)电路设计中，使用n型晶体管及p型晶体管来构建记忆体结构中的逻辑装置或位单元(bit cell)。在至少一实施方式中，栅极结构122a、122c表示n型晶体管并且栅极结构122b、122d表示p型晶体管。根据各种电路设计，栅极结构122中的至少一个被设置为主动元件(例如晶体管)的电极或为被动元件(例如电阻器或电容器)。
在一些实施方式中，基板110包含块状半导体材料，例如硅、锗、硅锗、碳化硅、III-V族化合物或其他合适的材料。在一些实施方式中，基板110为绝缘层上硅(SOI)基板或蓝宝石上硅(SOS)基板。鳍结构111从基板110延伸。在一些实施方式中，鳍结构111具有成角度的或渐缩的侧壁。或者，鳍结构111具有实质上笔直的侧壁。在一些实施方式中，鳍结构111具有与基板110相同的材料。在一些实施方式中，鳍结构111具有与基板110不同的材料。
设置多个隔离特征112以将一个主动区与另一个主动区分隔和/或分隔相邻的鳍结构111。也就是说，鳍结构111沿着第一方向平行排列，并且隔离特征112位于鳍结构111之间且在基板110上。鳍结构111的顶表面在隔离特征112的顶表面之上。隔离特征112包含介电材料，例如，氧化硅、氮化硅或其他合适的材料。本领域具通常知识者应理解，在至少一实施方式中，半导体装置100不具有鳍结构111，并且栅极结构122位于基板110上且与基板110直接接触，基板110具有实质上平坦的表面。以此方式，隔离特征112位于基板110中且被称为浅沟槽隔离(STI)特征。
第一操作区120A及第二操作区120B具有不同的操作电压。在至少一实施方式中，第一操作区120A被定义为核心区域且栅极结构122a、112b被用于核心电路，并且第二操作区120B被定义为输入/输出(I/O)区域且栅极结构122c、112d被用于输入/输出(I/O)电路。核心电路被设置为执行将逻辑功能耦合到外部电路的逻辑功能及外围电路，并且输入/输出电路作为高电压信号传送到低电压装置而没有组件损坏的介面。在一些实施方式中，在外围电路中具有相对较厚的栅极介电膜的晶体管被设置以维持更大施加到外围电路的临界电压。因此，栅极结构122c、112d具有比栅极结构122a、112b更厚的栅极介电膜。
每个栅极结构122具有介面层150a、150b、150c及150d(统称为介面层150)、栅极介电膜152a、152b、152c、152d(统称为栅极介电膜152)、功函数层154a、154b、154c、154d(统称为功函数层154)及导电层156a、156b、156c、156d(统称为导电层156)。介面层150位于鳍结构111及功函数层154之间。此外，介面层150包含具有厚度约至约的氧化物。在一些情况下，较大厚度的介面层150不利地影响晶体管的等效氧化物厚度(EOT)。等效氧化物厚度决定了与使用的栅极介电膜引起相同效果的一层氧化硅将有多厚。在一些情况下，较小厚度的介面层150增加了鳍结构111与栅极介电膜152之间的介面缺陷密度(Dit)。介面层150b、150d包含水溶性氧化物，例如二氧化锗或氧化镧。在一些实施方式中，介面层150a、150c包含与介面层150b、150d不同的氧化物。在一些实施方式中，介面层150a、150c包含与介面层150b、150d相同的氧化物。
栅极介电膜152位于介面层150及功函数层154之间。栅极介电膜152包含介电常数高于二氧化硅的高κ介电质(二氧化硅介电常数为约3.9)。在一些实施方式中，栅极介电膜152包含氧化铪，其具有介电常数为约18至约40。在其他实施方式中，栅极介电膜152包含二氧化锆、氧化钇、氧化镧、氧化钆、二氧化钛、锆酸铪或其他合适的材料中的一种。在一些实施方式中，栅极介电膜152具有厚度为约至约
功函数层154位于栅极介电膜152及导电层156之间且位于由栅极介电膜152限定的空腔内。另外，功函数层154包含用于调整每个栅极结构122的功函数以实现期望临界电压的材料，例如，栅极结构122a、122c包含n型功函数材料且栅极结构122b、122d包含p型功函数材料。
在一些实施方式中，覆盖层位于栅极介电膜152与功函数层154之间。覆盖层还被配置以调整晶体管的临界电压。在一些实施方式中，覆盖层选择性地位于p型晶体管中。在一些实施方式中，覆盖层具有厚度为约至约在一些情况下，较厚的覆盖层厚度增加了制造功函数层154的难度。在一些实施方式中，覆盖层包含氮化钛或氮化钽。
导电层156位于由栅极介电膜152限定的空腔内。在一些实施方式中，湿润层(例如钛)和/或阻挡层(例如氮化钛)位于功函数层154与导电层156之间。导电层156被配置为用作栅极结构122的主要导电部分。在一些实施方式中，导电层156包含铝、铜、钛、钨或其他合适的材料中的至少一种。
半导体装置100还包含在第一操作区120A及第二操作区120B中的水溶性介面层150b、150d之下的通道层114。在至少一实施方式中，通道层114包含锗，例如硅锗，其具有约15％至约95％的锗浓度及约4nm至约40nm的厚度。在一些实施方式中，通道层114在鳍结构111的顶表面上。因此，介面层150b、150d的底表面高于介面层150a、150c的底表面。在一些实施方式中，通道层114位于鳍结构111中，介面层150b、150d的底表面与介面层150a、150c的底表面实质上共平面。在一些实施方式中，介面层150b、150d的底表面低于介面层150a、150c的底表面，例如，当鳍结构111包含锗且栅极结构122a、122c的通道层由硅制成并沉积在鳍结构111的顶表面上方时。在一些实施方式中，通道层114包含与鳍结构111相同的材料；在一些实施方式中，通道层114包含与鳍结构111不同的材料。本领域具通常知识者应理解，在半导体装置100没有鳍结构111的一些实施方式中，通道层114位于基板110中，或位于基板110上并与基板110直接接触。
半导体装置100还包含间隔物130及层间电介层(ILD)140。间隔物130沿着栅极结构122的侧壁且位于鳍结构111上。在一些实施方式中，间隔物130具有非等向性蚀刻的形状，例如D型(圆形)或L型(具有垂直部分及水平部分)以限定轻微掺杂漏极(lightly dopeddrain；LDD)区116以帮助避免热载流子注入(hot carrier injection；HCI)。在一些实施方式中，间隔物130包含单一介电层，例如，二氧化硅、氮化硅、氮氧化硅、碳氮化硅或其他合适的材料。在一些实施方式中，间隔物130包含复合介电层，例如，氧化物-氮化物-氧化物(ONO)结构。基于轻微掺杂漏极(LDD)区域的各种要求，间隔物130的厚度为约至约在一些情况下，较大的厚度导致漏电流增加。在一些情况下，较小的厚度增加热载流子注入(HCI)的风险。
另外，源极/漏极特征118的至少一部分在鳍结构111中，且在栅极结构122的相对两侧。在一些实施方式中，源极/漏极特征118是鳍结构111中的n型掺杂区域或p型掺杂区域。在一些实施方式中，源极/漏极特征118为生长在鳍结构111凹槽中的磊晶材料，例如硅锗或碳化硅。因此，源极/漏极特征118突出于鳍结构111的顶表面之上。磊晶材料被设置为向晶体管的通道区域施加压缩/拉伸应力以提高载流子迁移率(carrier mobility)。在一些实施方式中，源极/漏极特征118为掺杂的磊晶材料。
层间电介层140位于间隔物130上并环绕栅极结构122。层间电介层(ILD)140也被称为层间电介层0(ILD0)。在一些实施方式中，层间电介层140包含单一介电层，例如，氧化硅、氮化硅、未掺杂硅酸盐玻璃(USG)、硼硅酸盐玻璃(BSG)、磷硅酸盐玻璃(PSG)、掺硼磷硅酸盐玻璃(BPSG)、氟硅玻璃(FSG)、四乙氧基硅烷(TEOS)或其他合适的介电材料。在一些实施方式中，层间电介层140包含低介电常数(低-κ)材料，例如，介电常数低于氧化硅。在一些实施方式中，层间电介层140包含极低κ(ELK)材料，例如，介电常数低于2.6。在一些实施方式中，层间电介层140包含复合介电层，例如，未掺杂硅酸盐玻璃及硼硅酸盐玻璃。
图2为根据本揭露的各种实施方式绘示的半导体装置的制造方法200流程图。本领域具通常知识者应理解，在一些实施方式中，可以在图2所示的方法200之前、期间和/或之后执行额外的操作。根据一些实施方式，以下叙述的其他制程细节请参考图3A-3H。
方法200包含操作210，形成第一绝缘膜在第一鳍结构(即图1中的鳍结构111b)之上，并且形成第二绝缘膜在第二鳍结构(即图1中的鳍结构111a)之上。第一绝缘膜对应核心电路区，并且第二绝缘膜对应输入/输出(I/O)电路区。尽管后续的输入/输出栅极介电膜实质上较核心栅极介电膜厚，但在一些情况下，第一绝缘膜与第二绝缘膜具有相同的厚度。例如，第一绝缘膜与第二绝缘膜都具有与输入/输出(I/O)栅极介电膜相同的厚度。在一些实施方式中，第一绝缘膜及第二绝缘膜为利用原位硅生长(in-situ silicon grown；ISSG)、快速热氧化(rapid thermal oxidation；RTO)或其他合适的方法选择性形成在第一鳍结构及第二鳍结构顶表面的热生长氧化物。在一些实施方式中，通过原子层沉积(ALD)、化学气相沉积(CVD)、物理气相沉积(PVD)或其他合适的制程毯覆沉积第一绝缘膜及第二绝缘膜。在一些实施方式中，第一绝缘膜及第二绝缘膜在单一步骤中形成，例如，热氧化制程。在一些实施方式中，第一绝缘膜及第二绝缘膜是以连续的步骤形成，例如，在第一绝缘膜及第二绝缘膜的热氧化制程之后，通过酸去除第一绝缘膜，接着执行另一热氧化制程或沉积制程。在半导体装置不具鳍结构的一些实施方式中，第一绝缘膜及第二绝缘膜直接形成在基板的顶表面上。第一鳍结构或第二鳍结构的至少一个包含水溶性通道层。在第一鳍结构及第二鳍结构包含硅的一些实施方式中，至少在第一鳍结构上沉积含锗通道层。在至少一实施方式中，在沉积含锗通道层之前，去除第一鳍结构的顶部部分。在第一鳍结构及第二鳍结构上都沉积含锗通道层的一些实施方式中，沉积额外的硅通道层在第二鳍结构的含锗通道层上。在第一鳍结构及第二鳍结构包含锗或硅锗的一些实施方式中，沉积硅通道层在第二鳍结构之上。在至少一实施方式中，在沉积硅通道层之前，去除第二鳍结构的顶部部分。
方法200继续进行至操作220，沉积牺牲膜在第一绝缘膜及第二绝缘膜上。在一些情况下，牺牲膜也被称为虚拟多晶硅(dummy poly)。在一些实施方式中，牺牲膜包含多晶、非晶硅或其组合。在一些实施方式中，牺牲膜通过原子层沉积(ALD)、化学气相沉积(CVD)、物理气相沉积(PVD)、磊晶生长或其他合适的制程沉积。在一些实施方式中，牺牲膜具有约至约的厚度。在一些情况下，较大的厚度增加制造成本且没有显著的益处。在一些情况下，较小的厚度增加了后续平坦化制程的难度。在一些实施方式中，牺牲膜是以共形的方法形成。也就是说，在鳍结构之上、沿着鳍结构的侧壁及在隔离特征之上的牺牲膜具有实质上均匀的厚度。在至少一实施方式中，在形成牺牲膜之后，沉积牺牲膜在硬掩膜之上。硬掩膜包含氮化硅、氧化硅、氮氧化硅或其他合适的材料。在一些实施方式中，硬掩膜的厚度为约至约硬掩膜通过原子层沉积、化学气相沉积、物理气相沉积或其他合适的制程形成。此外，在一些情况下，形成抗反射涂层(ARC)或底抗反射涂层(BARC)在硬掩膜之上以增强后续的微影制程。
方法200继续进行至操作230，通过蚀刻制程形成第一栅极堆叠及第二栅极堆叠。光阻通过旋转涂布制程、浸涂法或气刀涂布法涂覆在硬掩膜或牺牲膜上。接着，使用能量源(例如，波长从约10nm至约1000nm的微影曝光)来图案化光阻。图案化光阻定义了用于n型装置的栅极堆叠及用于p型装置的栅极堆叠。在一些实施方式中，用于n型装置的栅极堆叠及用于p型装置的栅极堆叠在单一步骤中被图案化。在一些实施方式中，用于n型装置的栅极堆叠及用于p型装置的栅极堆叠在连续的步骤中被图案化。接着，执行蚀刻制程从鳍结构去除未被图案化的硬掩膜、牺牲膜、第一绝缘膜及第二绝缘膜以形成第一栅极堆叠及第二栅极堆叠。在蚀刻制程之后，沿着第一栅极堆叠及第二栅极堆叠的侧壁形成间隔物。在一些实施方式中，第一栅极堆叠及第二栅极堆叠的源极/漏极特征形成在第一鳍结构及第二鳍结构中。示例性的源极/漏极特征通过植入法(implantation method)或在凹槽中磊晶生长应变材料而形成。通过蚀刻制程去除一部分的鳍结构来形成凹槽。
方法200继续进行至操作240，沉积层间电介层(例如图1中的层间电介层130)在第一栅极堆叠及第二栅极堆叠上。在一些实施方式中，在形成层间电介层之前，共形地形成蚀刻停止层在第一栅极堆叠、第二栅极堆叠、源极/漏极特征及鳍结构之上。蚀刻停止层提供相对于层间电介层充足的蚀刻选择性，以降低蚀刻制程在层间电介层中形成接触插塞而损坏源极/漏极特征的风险。蚀刻停止层用以在形成接触开口期间保护其下的栅极堆叠及源极/漏极特征。蚀刻停止层的形成包含沉积制程，例如原子层沉积、化学气相沉积、物理气相沉积或其他合适的制程。蚀刻停止层包含介电材料，例如氮化硅、氮氧化硅、碳氮化硅或其他合适的材料。在一些实施方式中，蚀刻停止层通过使用应变材料将应力施加到晶体管的通道区域。
之后，形成层间电介层在蚀刻停止层上以及在第一栅极堆叠及第二栅极堆叠之间。层间电介层的形成包含沉积制程，例如，化学气相沉积、物理气相沉积、高密度电浆(HDP)、旋转沉积(SOD)、原子层沉积或其他合适的制程。考量栅极堆叠的栅极高度，层间电介层的厚度为约90nm至约500nm。在一些情况下，较大的厚度增加了制造成本及处理时间。较小的厚度导致层间电介层下的栅极堆叠覆盖不足。形成层间电介层后进行平坦化制程(例如，化学机械平坦化(CMP)、蚀刻制程或其他合适的制程)去除多余的层间电介层以产生实质上平坦的栅极堆叠顶表面。在第一栅极堆叠及第二栅极堆叠包含硬掩膜的一些实施方式中，在平坦化制程期间去除整个硬掩膜和间隔物的顶部部分。在一些实施方式中，牺牲膜作为平坦化停止层。平坦的顶表面有助于提高后续微影制程的精密度。
方法200继续进行至操作250，去除牺牲膜以在层间电介层中形成第一沟槽及第二沟槽。通过蚀刻溶液去除牺牲膜，蚀刻溶液例如为氢氧化铵溶液(ammonium hydroxidesolution)、稀氢氟酸和/或其他合适的蚀刻剂。在一些实施方式中，通过干蚀刻制程去除牺牲膜。蚀刻剂的实例包含氟和/或氯基的蚀刻剂。去除制程导致第一沟槽及第二沟槽被其中填充如金属的导电层的间隔物限定，如同通常在栅极替换制程中所执行的，也被称为后栅极技术(gate last technique)。在一些实施方式中，执行去除制程直到第一绝缘膜及第二绝缘膜暴露。在一些实施方式中，去除制程包含同时去除第一绝缘膜及第二绝缘膜。在一些实施方式中，去除第一绝缘膜及第二绝缘膜包含连续的步骤。在一些实施方式中，去除第一绝缘膜及第二绝缘膜包含液相或气相稀释的氢氟酸。
方法200继续进行至操作260，涂布保护层以填充第二沟槽。在一些实施方式中，保护层为光阻。在第一绝缘膜及第二绝缘膜被暴露且第二绝缘膜的厚度等于输入/输出栅极介电膜的厚度的一些实施方式中，保护层选择性地涂布第二沟槽。在去除牺牲膜期间去除第一绝缘膜及第二绝缘膜的一些实施方式中，形成输入/输出栅极介电膜在第一沟槽和第二沟槽中，并且形成保护层在第二沟槽上。
方法200继续进行至操作270，从第一沟槽去除第一绝缘膜。在一些实施方式中，通过蚀刻溶液如氢氧化铵溶液和氢氟酸的组合和/或其他合适的蚀刻剂去除第一绝缘膜。在一些实施方式中，通过干蚀刻制程去除第一绝缘膜。蚀刻剂的实例包含氯基蚀刻剂。
方法200继续进行至操作280，使用非水溶剂基化学品(non-aqueous solvent-based chemical)形成第一氧化物膜(如图1中的介面层150b)在第一沟槽中。非水溶剂基化学品包含浓度小于8％的非水溶剂基化学品的水溶液，以帮助减少水溶性通道层的损失。在一些实施方式中，非水溶剂基化学品为有机非质子溶剂。非质子溶剂为不含不稳定氢的溶剂。非水溶剂基化学品的实例包含碳酸丙烯酯、乙醇胺、环丁砜、N-甲基吡咯烷酮、二甲基亚砜、二甲基乙酰胺或其他合适的化学品。为了在涉及化学反应时帮助提高溶剂的稳定性，非水溶剂基化学品的电位窗口(potential window，也被称为电化学窗口)为约-4伏特至约+4伏特。此外，为了在湿氧化制程期间以酸和碱取代水，非水溶剂基化学品的介电常数大于20。在一些实施方式中，非水溶剂基化学品为无水的(即，0％水)。非水溶剂基化学品混和但不限于氧化剂，例如过氧化氢、臭氧、硫酸、硝酸、过二硫酸(peroxydisulfuric acid)、过一硫酸(peroxymonosulfuric acid)和介面活性剂，以和其下的通道层执行湿氧化制程。在一些实施方式中，非水溶剂基化学品具有大于60℃的闪点。闪点是挥发性物质暴露于火源时点燃的最低温度。在一些情况下，较低的闪点在制造过程中增加了点燃的可能性。
在一些实施方式中，第一氧化物膜的厚度为约至约在一些情况下，较大的厚度增加了制造成本和时间，且没有显著的益处。在一些实施方式中，较小的厚度增加了介面缺陷密度。在至少一实施方式中，第一氧化物膜的生长速率为约至约本领域具通常知识者应理解，即使通道层为非水溶性(例如硅通道层)，第一氧化物膜的湿氧化也会发生。
在一些实施方式中，为了去除污染物如颗粒和离子，非水溶剂基化学品与氢氧化铵溶液、氯化氢和/或氟化氢混和。和其他方法相比，由于使用非水溶剂基化学品，通道层和第一氧化物膜的损失相对地轻微。在一些实施方式中，第一氧化物膜的底表面与间隔物的底表面之间的高度差为约至约也就是说，和其他方法相比，氧化物和/或通道层的体积损失小于约2至3个数量级。和使用其他方法形成氧化物膜相比，使用非水溶剂基化学品还在第一氧化物膜与通道层之间的介面处以及第一氧化物膜与栅极介电膜之间的介面处提供更平滑的表面。在一些实施方式中，每平方微米面积的粗粗糙度均方根(RMS)为约至约氧化物和通道层损失的减少及更平滑的表面有助于保持稳定的饱和电流(IdsatIsat)、持久的时间相关介电层崩溃(TBBDTDDB)以及更小的临界电压(Vt)偏移。因此，与使用其他制程形成的半导体装置相比，此半导体装置的实际性能更接近设计性能。在一些实施方式中，考量第一氧化物膜的预定厚度，湿氧化的处理时间持续约10秒至约15分钟，并且处理温度为约25℃至约65℃。
在一些实施方式中，在形成第一氧化物膜的期间同时去除被涂布以填充第二沟槽的保护层。在一些实施方式中，去除保护层之后形成第一氧化物膜。在一些实施方式中，例如使用氢氟酸或氢氧化铵-过氧化氢-水混和物(APM)的清洗制程于第一沟槽中形成第一氧化物膜之前执行。
在一些实施方式中，在操作250中不形成第二沟槽，并且省略操作260。在操作250中不形成第二沟槽的一些实施方式中，以单独的操作形成第二沟槽，例如在第一沟槽形成第一氧化物膜之后。在一些实施方式中，由于方法200中包含额外的图案化及蚀刻操作，在与形成第一沟槽分开的操作中形成第二沟槽增加了方法200的复杂性。
图3A-3H为根据本揭露的各种实施方式绘示的半导体装置300的制程各步骤截面图。半导体装置300包含与半导体装置100相似的元件，并且相似元件的编号最后两位数字相同。图3A为操作210之后的半导体装置300截面图。半导体装置300包含基板310、多个鳍结构311以及多个隔离特征312。半导体装置300还包含第一操作区320A和第二操作区320B。在一些实施方式中，第一操作区320A表示核心电路区并且第二操作区320B表示输入/输出(I/O)电路区。第一操作区320A具有第一绝缘膜316A并且第二操作区320B具有第二绝缘膜316B。在一些实施方式中，第一绝缘膜316A和第二绝缘膜316B选择性的形成在鳍结构111的主动区上。在一些实施方式中，第一绝缘膜316A和第二绝缘膜316B覆盖隔离特征312。第一操作区320A和第二操作区320B中的每一个都包含通道层314。在一些实施方式中，通道层314占据第一操作区320A和第二操作区320B的一部分主动区。在此种方式中，每个操作区具有至少两种类型的通道区域。在一些实施方式中，通道层314占据第一操作区320A或第二操作区320B中的至少一个的整个主动区。
在一些实施方式中，通道层314包含用于提高性能的含锗材料，例如锗或硅锗，特别是在p型装置中。在鳍结构111包含晶体中的硅、多晶或非晶结构的一些实施方式中，通过磊晶生长或沉积制程在鳍结构111的顶表面形成通道层314。在一些实施方式中，去除一部分的鳍结构111以形成凹槽，并且形成通道层314以填充凹槽。也就是说，通道层314的顶表面在鳍结构111的原始顶表面的上表面之上、共平面或之下。在鳍结构111包含锗的一些实施方式中，通过与上述类似的方法形成通道层以区别通道层314。
图3B为操作220之后的半导体装置300截面图。通过沉积制程形成牺牲膜317及硬掩膜319在第一绝缘膜316A、第二绝缘膜316B及隔离特征112上。在一些实施方式中，沉积牺牲膜317是通过与硬掩膜319相同的方法。在一些实施方式中，沉积牺牲膜317是通过与硬掩膜319不同的方法。牺牲膜317具有与硬掩膜319不同的蚀刻选择性。
图3C为操作230之后的半导体装置300截面图。通过使用微影制程和蚀刻制程来图案化及形成多个栅极堆叠322a’、322b’、322c’及322d’。在蚀刻制程之后，分离第一绝缘膜316A和第二绝缘膜316B以定义介面层350a’、350b’、350c及350d。在至少一实施方式中，栅极堆叠322a’为n型核心装置，栅极堆叠322b’为p型核心装置，栅极堆叠322c’为n型输入/输出装置以及栅极堆叠322d’为p型输入/输出装置。
图3D为操作240之后的半导体装置300截面图。形成轻微掺杂漏极(LDD)区316在栅极堆叠322a’、332b’、322c’及322d’的相对两侧。形成轻微掺杂漏极(LDD)区316包含一或多个植入制程。每个轻微掺杂漏极(LDD)区316包含基于导电类型的各种掺杂剂。接着，沿着栅极堆叠322a’、332b’、322c’、322d’的侧壁形成间隔物330，并限定源极/漏极特征318的位置。类似地，每个源极/漏极区包含基于导电类型的各种掺杂剂。半导体装置300还包含沉积在栅极堆叠322a’、332b’、322c’、322d’及鳍结构111上的层间电介层340。
图3E为操作250之后的半导体装置300截面图。在一些实施方式中，使用平坦化制程以暴露牺牲膜317并去除间隔物330的顶部部分。接着，去除牺牲膜317以暴露介面层350a’、350b’、350c及350d。在层间电介层340中形成沟槽321、323、325及327。在一些实施方式中，在层间电介层340中形成接触开口，然后填充导电材料以形成接触插塞与源极/漏极特征318电性连接。
图3F为操作260之后的半导体装置300截面图。在介面层350c及350d的厚度满足输入/输出装置的厚度的一些实施方式中，保护层360覆盖并填充沟槽325及327。在一些实施方式中，保护层360包含光阻。在一些实施方式中，保护层360覆盖整个第二操作区320B。
图3G为操作270之后的半导体装置300截面图。通过湿蚀刻制程、干蚀刻制程或其组合去除介面层350a’及350b’。在一些实施方式中，在单一步骤中去除介面层350a’及350b’。在一些实施方式中，在连续的步骤中去除介面层350a’及350b’。
图3H为操作280之后的半导体装置300截面图。在由通道层314生长的氧化物为水溶性(例如二氧化锗或二氧化硅锗)的一些实施方式中，使用非水溶剂基化学品在鳍结构311的暴露部分上同时形成介面层350a和介面层350b。在通道层314由硅锗制成的一些实施方式中，介面层350b中二氧化锗的百分比与通道层340中锗的百分比成比例。在一些实施方式中，介面层350a包含与介面层350b相同的氧化物。在通道层314包含锗且鳍结构311a包含硅的一些实施方式中，介面层350a包含与介面层350b不同的氧化物，例如介面层350a包含氧化硅，介面层350b包含氧化锗。
图4为根据本揭露的各种实施方式绘示的半导体装置400截面图。半导体装置400包含元件与半导体装置100类似的元件，并且相似元件的编号中的最后两位数字相同。半导体装置400在由鳍结构411和间隔物430限定的空腔中具有U型介面层450b。介面层450b包含和通道层414平行的第一部分451以及垂直于通道层414的第二部分453。在一些实施方式中，在介面层450b的形成期间，沿着间隔物430的侧壁发生氧化过程。在间隔物430包含硅原子(例如氮化硅或碳氮化硅)的一些情况下，当形成第一部分451时，第二部分453同时包含二氧化硅。因此，在一些实施方式中，当间隔物430包含锗原子时，第一部分451包含与第二部分453相同的材料；在一些实施方式中，当间隔物430包含硅原子时，第一部分451包含与第二部分453不同的材料。
本揭露的一态样是关于一种制造半导体结构的方法。此方法包含在第一鳍结构上形成第一绝缘膜及在第二鳍结构上形成第二绝缘膜；在第二绝缘膜上涂布保护层；去除第一绝缘膜以暴露第一鳍结构的一部分；以及使用非水溶剂基化学品在第一鳍结构的暴露部分上形成第一氧化物膜。在一些实施方式中，形成第一氧化物膜包含使用有机非质子溶剂。在一些实施方式中，形成第一氧化物膜包含使用浓度小于8％的非水溶剂基化学品水溶液。在一些实施方式中，形成第一氧化物膜包含使用非水溶剂基化学品。在一些实施方式中，形成第一氧化物膜包含使用碳酸丙烯酯、乙醇胺、环丁砜、N-甲基吡咯烷酮、二甲基亚砜或二甲基乙酰胺。在一些实施方式中，形成第一氧化物膜包含使用过氧化氢、氢氧化铵溶液、氯化氢、氟化氢、臭氧、硫酸、硝酸、过二硫酸或过一硫酸。在一些实施方式中，此方法还包含去除保护层以暴露第二绝缘膜。在一些实施方式中，去除保护层包含在单一步骤中形成第一氧化物膜及去除保护层。在一些实施方式中，去除保护层包含在连续的步骤中形成第一氧化物膜以及去除保护层。在一些实施方式中，形成第一氧化物膜包含形成第一氧化物膜以包含至少两种氧化物材料。
本揭露的另一态样是关于一种制造半导体装置的方法。此方法包含在第一鳍结构上形成第一绝缘膜以及在第二鳍结构上形成第二绝缘膜；在第一绝缘膜及第二绝缘膜上沉积牺牲膜；使用蚀刻制程形成第一栅极堆叠及第二栅极堆叠；在第一栅极堆叠及第二栅极堆叠上沉积层间电介层；去除牺牲膜以在层间电介层中形成第一沟槽及第二沟槽；涂布保护层以填充第二沟槽；从第一沟槽去除第一绝缘膜；以及使用非水溶剂基化学品在第一沟槽中形成第一氧化物膜。在一些实施方式中，此方法还包含在第一鳍结构上形成通道层，其中通道层为水溶性的。在一些实施方式中，形成第一氧化物膜包含以每秒约至每秒约的生长速率生长第一氧化物膜。在一些实施方式中，形成第一氧化物膜包含在温度为约25℃至约65℃生长第一氧化物膜。在一些实施方式中，形成第一氧化物膜包含形成第一氧化物膜以与第二绝缘膜具有相同的化合物。在一些实施方式中，形成第一氧化物膜包含形成第一氧化物膜以与第二绝缘膜具有不同的化合物。在一些实施方式中，此方法还包含在第三鳍结构上形成第三绝缘膜；使用蚀刻制程形成第三栅极堆叠；在第三栅极堆叠上沉积层间电介层；去除牺牲膜以在层间电介层中形成第三沟槽；从第三沟槽中去除第三绝缘膜；以及使用非水溶剂基化学品在第三沟槽中形成第三氧化物膜。第三氧化物膜包含与第一氧化物膜不同的材料。
本揭露的又一态样是关于一种半导体集成电路。此半导体集成电路包含具有水溶性通道层的鳍结构以及在水溶性通道层上的栅极结构。栅极结构包含氧化物膜、栅极介电膜以及栅极电极。半导体集成电路还包含沿着栅极结构的间隔物。间隔物和水溶性通道层之间的介面比氧化物膜和水溶性通道层之间的介面高约至约在一些实施方式中，氧化物膜具有实质上垂直于水溶性通道层的第一部分以及实质上平行于水溶性通道层的第二部分。第一部分包含与第二部分不同的氧化物。
虽然本揭露已以实施方式揭露如上，然其并非用以限定本揭露，任何熟悉此技艺者，在不脱离本揭露的精神和范围内，当可作各种的更动与润饰，因此本揭露的保护范围当视所附的权利要求书所界定的范围为准。

Claims (1)

1.一种半导体装置的制造方法，其特征在于，包含：
形成一第一绝缘膜在一第一鳍结构上，以及形成一第二绝缘膜在一第二鳍结构上；
涂布一保护层在该第二绝缘膜上；
去除该第一绝缘膜以暴露该第一鳍结构的一部分；以及
使用非水溶剂基化学品形成一第一氧化物膜在该第一鳍结构的暴露部分上。
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