TW201839823A - 半導體裝置的製造方法 - Google Patents
半導體裝置的製造方法 Download PDFInfo
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- TW201839823A TW201839823A TW107109322A TW107109322A TW201839823A TW 201839823 A TW201839823 A TW 201839823A TW 107109322 A TW107109322 A TW 107109322A TW 107109322 A TW107109322 A TW 107109322A TW 201839823 A TW201839823 A TW 201839823A
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Classifications
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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Abstract
一種半導體裝置的製造方法,包含形成第一絕緣膜在第一鰭結構上及形成第二絕緣膜在第二鰭結構上,塗佈保護層在第二絕緣膜上,去除第一絕緣膜以暴露一部分的第一鰭結構,以及使用非水溶劑基化學品形成第一氧化物膜在第一鰭結構的暴露部分上。
Description
本揭露是有關於一種半導體裝置的製造方法及一種半導體積體電路。
當半導體裝置,例如金屬-氧化物-半導體場效電晶體(MOSFET)或金屬氧化物半導體(MOS)電容器透過各種技術節點縮小時,使用高介電常數κ(高-κ)介電質(與二氧化矽相比)及導電材料來形成閘極結構。在閘極結構中,使用介面層來改善基板表面和高-κ介電質之間的介面以減少損傷和缺陷。介面層還被設置以抑制半導體裝置中通道載流子的遷移率下降且有助於提升裝置性能的穩定性。
根據本揭露之一實施方式,提供一種半導體裝置的製造方法,包含形成第一絕緣膜在第一鰭結構上及形成第二絕緣膜在第二鰭結構上,塗佈保護層在第二絕緣膜上,去除第一絕緣膜以暴露一部分的第一鰭結構,以及使用非水溶劑基化學品形成第一氧化物膜在第一鰭結構的暴露部分上。
100、300、400‧‧‧半導體裝置
110、310、410‧‧‧基板
111、111a、111b、111c、111d、311、311a、311b、311c、311d、411‧‧‧鰭結構
112、312‧‧‧隔離特徵
114、314、414‧‧‧通道層
116、316‧‧‧輕微摻雜汲極(LDD)區
118‧‧‧源極/汲極特徵
120A、320A‧‧‧第一操作區
120B、320B‧‧‧第二操作區
122、122a、122b、122c、122d‧‧‧閘極結構
130、330、430‧‧‧間隔物
140、340‧‧‧層間電介層
150、150a、150b、150c、150d、350a、350b、350c、350d、350a’、350b’、450b‧‧‧介面層
152、152a、152b、152c、152d‧‧‧閘極介電膜
154、154a、154b、154c、154d‧‧‧功函數層
156、156a、156b、156c、156d‧‧‧導電層
200‧‧‧方法
210、220、230、240、250、260、270、280‧‧‧操作
316A‧‧‧第一絕緣膜
316B‧‧‧第二絕緣膜
317‧‧‧犧牲膜
318‧‧‧源極/汲極特徵
319‧‧‧硬掩膜
321、323、325、327‧‧‧溝槽
322a’、322b’、322c’、322d’‧‧‧閘極堆疊
360‧‧‧保護層
451‧‧‧第一部分
453‧‧‧第二部分
當讀到隨附的圖式時,從以下詳細的敘述可充分瞭解本揭露的各方面。值得注意的是,根據工業上的標準實務,各種特徵不是按比例繪製。事實上,為了清楚的討論,各種特徵的尺寸可任意增加或減少。
第1圖為根據本揭露之各種實施方式繪示的半導體裝置截面圖。
第2圖為根據本揭露之各種實施方式繪示的半導體裝置的製造方法流程圖。
第3A-3H圖為根據本揭露之各種實施方式繪示的半導體裝置的製程各步驟截面圖。
第4圖為根據本揭露之各種實施方式繪示的半導體裝置截面圖。
以下將以圖式揭露本揭露之複數個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本揭露。也就是說,在本揭露部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖示起見,一些習知慣用的結構與元件在圖示中將以簡單示意的方式繪示之。
在本文中使用空間相對用語,例如「下方」、「之下」、「上方」、「之上」等,這是為了便於敘述一元 件或特徵與另一元件或特徵之間的相對關係,如圖中所繪示。這些空間上的相對用語的真實意義包含其他的方位。例如,當圖示上下翻轉180度時,一元件與另一元件之間的關係,可能從「下方」、「之下」變成「上方」、「之上」。此外,本文中所使用的空間上的相對敘述也應作同樣的解釋。
數十年來,二氧化矽(SiO2)已被用作金氧半場效電晶體(MOSFET)中的閘極介電膜。由於裝置特徵(例如通道長度及裝置之間的間距)的尺寸減少,為了維持閘極電容及臨界電壓(Vt),閘極介電膜的厚度也已減少。由於上述之一或多個特徵尺寸的減少,漏電流急遽增加,導致更多的功率消耗及裝置可靠性(例如,時間相關介電層崩潰(time dependent dielectric breakdown;TDDB)下降。為了提供在物理上較厚,具有與二氧化矽相同等效氧化物厚度(EOT)及電容等效厚度(CET)的閘極介電膜,以高k介電膜取代二氧化矽。形成介面層(IL)在高k介電膜及基板之間以鈍化基板表面處的懸鍵(dangling bonds)並且提供低介面缺陷密度(interface trap density;Dit)的介面。介面層也用於形成阻擋介面反應及擴散到裝置的通道區域中的屏障。然而,當介面層包含水溶性(即可被水去除)材料時,涉及濕式氧化製程和/或光阻剝除製程的水溶液將導致介面層的損耗,從而不利地影響裝置性能和/或增加摻雜劑及雜質通過高k介電膜擴散的可能性。
在一些實施方式中,在濕式氧化製程中使用非 水溶劑基化學品(non-aqueous solvent-based chemical)以幫助避免介電層損耗。與其他方法相比,介面層損耗的減少在介面處的高K介電膜中具有更少的電荷/陷阱(charges/traps)、更平滑的表面及更小的臨界電壓偏移(Vt shift)。在一些實施方式中,同時在濕式氧化製程及光阻剝除製程中使用非水溶劑基化學品,與其他方法相比,導致製造成本和/或處理時間的減少。
第1圖為根據本揭露之各種實施方式繪示的半導體裝置100截面圖。半導體裝置100包含分成第一操作區120A及第二操作區120B的基板110、複數個鰭結構111a、111b、111c及111d(統稱為鰭結構111)以及閘極結構122a、122b、122c及122d(統稱為閘極結構122)。在互補式金屬氧化物半導體(COMS)電路設計中,使用n型電晶體及p型電晶體來構建記憶體結構中的邏輯裝置或位單元(bit cell)。在至少一實施方式中,閘極結構122a、122c表示n型電晶體並且閘極結構122b、122d表示p型電晶體。根據各種電路設計,閘極結構122中的至少一個被設置為主動元件(例如電晶體)的電極或為被動元件(例如電阻器或電容器)。
在一些實施方式中,基板110包含塊狀半導體材料,例如矽、鍺、矽鍺、碳化矽、III-V族化合物或其他合適的材料。在一些實施方式中,基板110為絕緣層上矽(SOI)基板或藍寶石上矽(SOS)基板。鰭結構111從基板110延伸。在一些實施方式中,鰭結構111具有成角度的或漸縮 的側壁。或者,鰭結構111具有實質上筆直的側壁。在一些實施方式中,鰭結構111具有與基板110相同的材料。在一些實施方式中,鰭結構111具有與基板110不同的材料。
設置複數個隔離特徵112以將一個主動區與另一個主動區分隔和/或分隔相鄰的鰭結構111。也就是說,鰭結構111沿著第一方向平行排列,並且隔離特徵112位於鰭結構111之間且在基板110上。鰭結構111的頂表面在隔離特徵112的頂表面之上。隔離特徵112包含介電材料,例如,氧化矽、氮化矽或其他合適的材料。本領域具通常知識者應理解,在至少一實施方式中,半導體裝置100不具有鰭結構111,並且閘極結構122位於基板110上且與基板110直接接觸,基板110具有實質上平坦的表面。以此方式,隔離特徵112位於基板110中且被稱為淺溝槽隔離(STI)特徵。
第一操作區120A及第二操作區120B具有不同的操作電壓。在至少一實施方式中,第一操作區120A被定義為核心區域且閘極結構122a、112b被用於核心電路,並且第二操作區120B被定義為輸入/輸出(I/O)區域且閘極結構122c、112d被用於輸入/輸出(I/O)電路。核心電路被設置為執行將邏輯功能耦合到外部電路的邏輯功能及外圍電路,並且輸入/輸出電路作為高電壓信號傳送到低電壓裝置而沒有組件損壞的介面。在一些實施方式中,在外圍電路中具有相對較厚的閘極介電膜的電晶體被設置以維持更大施加到外圍電路的臨界電壓。因此,閘極結構122c、112d具有比閘極結構122a、112b更厚的閘極介電膜。
每個閘極結構122具有介面層150a、150b、150c及150d(統稱為介面層150)、閘極介電膜152a、152b、152c、152d(統稱為閘極介電膜152)、功函數層154a、154b、154c、154d(統稱為功函數層154)及導電層156a、156b、156c、156d(統稱為導電層156)。介面層150位於鰭結構111及功函數層154之間。此外,介面層150包含具有厚度約5Å至約15Å的氧化物。在一些情況下,較大厚度的介面層150不利地影響電晶體的等效氧化物厚度(EOT)。等效氧化物厚度決定了與使用之閘極介電膜引起相同效果的一層氧化矽將有多厚。在一些情況下,較小厚度的介面層150增加了鰭結構111與閘極介電膜152之間的介面缺陷密度(Dit)。介面層150b、150d包含水溶性氧化物,例如二氧化鍺或氧化鑭。在一些實施方式中,介面層150a、150c包含與介面層150b、150d不同的氧化物。在一些實施方式中,介面層150a、150c包含與介面層150b、150d相同的氧化物。
閘極介電膜152位於介面層150及功函數層154之間。閘極介電膜152包含介電常數高於二氧化矽的高κ介電質(二氧化矽介電常數為約3.9)。在一些實施方式中,閘極介電膜152包含氧化鉿,其具有介電常數為約18至約40。在其他實施方式中,閘極介電膜152包含二氧化鋯、氧化釔、氧化鑭、氧化釓、二氧化鈦、鋯酸鉿或其他合適的材料中的一種。在一些實施方式中,閘極介電膜152具有厚度為約5Å至約50Å。
功函數層154位於閘極介電膜152及導電層156之間且位於由閘極介電膜152限定的空腔內。另外,功函數層154包含用於調整每個閘極結構122的功函數以實現期望臨界電壓的材料,例如,閘極結構122a、122c包含n型功函數材料且閘極結構122b、122d包含p型功函數材料。
在一些實施方式中,覆蓋層位於閘極介電膜152與功函數層154之間。覆蓋層還被配置以調整電晶體的臨界電壓。在一些實施方式中,覆蓋層選擇性地位於p型電晶體中。在一些實施方式中,覆蓋層具有厚度為約5Å至約50Å。在一些情況下,較厚的覆蓋層厚度增加了製造功函數層154的難度。在一些實施方式中,覆蓋層包含氮化鈦或氮化鉭。
導電層156位於由閘極介電膜152限定的空腔內。在一些實施方式中,濕潤層(例如鈦)和/或阻擋層(例如氮化鈦)位於功函數層154與導電層156之間。導電層156被配置為用作閘極結構122的主要導電部分。在一些實施方式中,導電層156包含鋁、銅、鈦、鎢或其他合適的材料中的至少一種。
半導體裝置100還包含在第一操作區120A及第二操作區120B中的水溶性介面層150b、150d之下的通道層114。在至少一實施方式中,通道層114包含鍺,例如矽鍺,其具有約15%至約95%的鍺濃度及約4nm至約40nm的厚度。在一些實施方式中,通道層114在鰭結構111的頂表面上。因此,介面層150b、150d的底表面高於介面層 150a、150c的底表面。在一些實施方式中,通道層114位於鰭結構111中,介面層150b、150d的底表面與介面層150a、150c的底表面實質上共平面。在一些實施方式中,介面層150b、150d的底表面低於介面層150a、150c的底表面,例如,當鰭結構111包含鍺且閘極結構122a、122c的的通道層由矽製成並沉積在鰭結構111的頂表面上方時。在一些實施方式中,通道層114包含與鰭結構111相同的材料;在一些實施方式中,通道層114包含與鰭結構111不同的材料。本領域具通常知識者應理解,在半導體裝置100沒有鰭結構111的一些實施方式中,通道層114位於基板110中,或位於基板110上並與基板110直接接觸。
半導體裝置100還包含間隔物130及層間電介層(ILD)140。間隔物130沿著閘極結構122的側壁且位於鰭結構111上。在一些實施方式中,間隔物130具有非等向性蝕刻的形狀,例如D型(圓形)或L型(具有垂直部分及水平部分)以限定輕微摻雜汲極(lightly doped drain;LDD)區116以幫助避免熱載流子注入(hot carrier injection;HCI)。在一些實施方式中,間隔物130包含單一介電層,例如,二氧化矽、氮化矽、氮氧化矽、碳氮化矽或其他合適的材料。在一些實施方式中,間隔物130包含複合介電層,例如,氧化物-氮化物-氧化物(ONO)結構。基於輕微摻雜汲極(LDD)區域的各種要求,間隔物130的厚度為約100Å至約600Å。在一些情況下,較大的厚度導致漏電流增加。在一些情況下,較小的厚度增加熱載流子注入(HCI)的風險。
另外,源極/汲極特徵118的至少一部分在鰭結構111中,且在閘極結構122的相對兩側。在一些實施方式中,源極/汲極特徵118是鰭結構111中的n型摻雜區域或p型摻雜區域。在一些實施方式中,源極/汲極特徵118為生長在鰭結構111凹槽中的磊晶材料,例如矽鍺或碳化矽。因此,源極/汲極特徵118突出於鰭結構111的頂表面之上。磊晶材料被設置為向電晶體的通道區域施加壓縮/拉伸應力以提高載流子遷移率(carrier mobility)。在一些實施方式中,源極/汲極特徵118為摻雜的磊晶材料。
層間電介層140位於間隔物130上並環繞閘極結構122。層間電介層(ILD)140也被稱為層間電介層0(ILD0)。在一些實施方式中,層間電介層140包含單一介電層,例如,氧化矽、氮化矽、未掺雜矽酸鹽玻璃(USG)、硼矽酸鹽玻璃(BSG)、磷矽酸鹽玻璃(PSG)、掺硼磷矽酸鹽玻璃(BPSG)、氟矽玻璃(FSG)、四乙氧基矽烷(TEOS)或其他合適的介電材料。在一些實施方式中,層間電介層140包含低介電常數(低-κ)材料,例如,介電常數低於氧化矽。在一些實施方式中,層間電介層140包含極低κ(ELK)材料,例如,介電常數低於2.6。在一些實施方式中,層間電介層140包含複合介電層,例如,未掺雜矽酸鹽玻璃及硼矽酸鹽玻璃。
第2圖為根據本揭露之各種實施方式繪示的半導體裝置的製造方法200流程圖。本領域具通常知識者應理解,在一些實施方式中,可以在第2圖所示的方法200之前、 期間和/或之後執行額外的操作。根據一些實施方式,以下敘述的其他製程細節請參考第3A-3H圖。
方法200包含操作210,形成第一絕緣膜在第一鰭結構(即第1圖中的鰭結構111b)之上,並且形成第二絕緣膜在第二鰭結構(即第1圖中的鰭結構111a)之上。第一絕緣膜對應核心電路區,並且第二絕緣膜對應輸入/輸出(I/O)電路區。儘管後續的輸入/輸出閘極介電膜實質上較核心閘極介電膜厚,但在一些情況下,第一絕緣膜與第二絕緣膜具有相同的厚度。例如,第一絕緣膜與第二絕緣膜都具有與輸入/輸出(I/O)閘極介電膜相同的厚度。在一些實施方式中,第一絕緣膜及第二絕緣膜為利用原位矽生長(in-situ silicon grown;ISSG)、快速熱氧化(rapid thermal oxidation;RTO)或其他合適的方法選擇性形成在第一鰭結構及第二鰭結構頂表面的熱生長氧化物。在一些實施方式中,藉由原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)或其他合適的製程毯覆沉積第一絕緣膜及第二絕緣膜。在一些實施方式中,第一絕緣膜及第二絕緣膜在單一步驟中形成,例如,熱氧化製程。在一些實施方式中,第一絕緣膜及第二絕緣膜是以連續的步驟形成,例如,在第一絕緣膜及第二絕緣膜的熱氧化製程之後,藉由酸去除第一絕緣膜,接著執行另一熱氧化製程或沉積製程。在半導體裝置不具鰭結構的一些實施方式中,第一絕緣膜及第二絕緣膜直接形成在基板的頂表面上。第一鰭結構或第二鰭結構的至少一個包含水溶性通道層。在第一鰭結構及第二鰭結構包含 矽的一些實施方式中,至少在第一鰭結構上沉積含鍺通道層。在至少一實施方式中,在沉積含鍺通道層之前,去除第一鰭結構的頂部部分。在第一鰭結構及第二鰭結構上都沉積含鍺通道層的一些實施方式中,沉積額外的矽通道層在第二鰭結構的含鍺通道層上。在第一鰭結構及第二鰭結構包含鍺或矽鍺的一些實施方式中,沉積矽通道層在第二鰭結構之上。在至少一實施方式中,在沉積矽通道層之前,去除第二鰭結構的頂部部分。
方法200繼續進行至操作220,沉積犧牲膜在第一絕緣膜及第二絕緣膜上。在一些情況下,犧牲膜也被稱為虛擬多晶矽(dummy poly)。在一些實施方式中,犧牲膜包含多晶、非晶矽或其組合。在一些實施方式中,犧牲膜藉由原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、磊晶生長或其他合適的製程沉積。在一些實施方式中,犧牲膜具有約50Å至約400Å的厚度。在一些情況下,較大的厚度增加製造成本且沒有顯著的益處。在一些情況下,較小的厚度增加了後續平坦化製程的難度。在一些實施方式中,犧牲膜是以共形的方法形成。也就是說,在鰭結構之上、沿著鰭結構的側壁及在隔離特徵之上的犧牲膜具有實質上均勻的厚度。在至少一實施方式中,在形成犧牲膜之後,沉積犧牲膜在硬掩膜之上。硬掩膜包含氮化矽、氧化矽、氮氧化矽或其他合適的材料。在一些實施方式中,硬掩膜的厚度為約100Å至約500Å。硬掩膜藉由原子層沉積、化學氣相沉積、物理氣相沉積或其他合適的製程形成。此外,在 一些情況下,形成抗反射塗層(ARC)或底抗反射塗層(BARC)在硬掩膜之上以增強後續的微影製程。
方法200繼續進行至操作230,藉由蝕刻製程形成第一閘極堆疊及第二閘極堆疊。光阻藉由旋轉塗佈製程、浸塗法或氣刀塗佈法塗覆在硬掩膜或犧牲膜上。接著,使用能量源(例如,波長從約10nm至約1000nm的微影曝光)來圖案化光阻。圖案化光阻定義了用於n型裝置的閘極堆疊及用於p型裝置的閘極堆疊。在一些實施方式中,用於n型裝置的閘極堆疊及用於p型裝置的閘極堆疊在單一步驟中被圖案化。在一些實施方式中,用於n型裝置的閘極堆疊及用於p型裝置的閘極堆疊在連續的步驟中被圖案化。接著,執行蝕刻製程從鰭結構去除未被圖案化的硬掩膜、犧牲膜、第一絕緣膜及第二絕緣膜以形成第一閘極堆疊及第二閘極堆疊。在蝕刻製程之後,沿著第一閘極堆疊及第二閘極堆疊的側壁形成間隔物。在一些實施方式中,第一閘極堆疊及第二閘極堆疊的源極/汲極特徵形成在第一鰭結構及第二鰭結構中。示例性的源極/汲極特徵藉由植入法(implantation method)或在凹槽中磊晶生長應變材料而形成。藉由蝕刻製程去除一部分的鰭結構來形成凹槽。
方法200繼續進行至操作240,沉積層間電介層(例如第1圖中的層間電介層130)在第一閘極堆疊及第二閘極堆疊上。在一些實施方式中,在形成層間電介層之前,共形地形成蝕刻停止層在第一閘極堆疊、第二閘極堆疊、源極/汲極特徵及鰭結構之上。蝕刻停止層提供相對於層間電介 層充足的蝕刻選擇性,以降低蝕刻製程在層間電介層中形成接觸插塞而損壞源極/汲極特徵的風險。蝕刻停止層用以在形成接觸開口期間保護其下的閘極堆疊及源極/汲極特徵。蝕刻停止層的形成包含沉積製程,例如原子層沉積、化學氣相沉積、物理氣相沉積或其他合適的製程。蝕刻停止層包含介電材料,例如氮化矽、氮氧化矽、碳氮化矽或其他合適的材料。在一些實施方式中,蝕刻停止層藉由使用應變材料將應力施加到電晶體的通道區域。
之後,形成層間電介層在蝕刻停止層上以及在第一閘極堆疊及第二閘極堆疊之間。層間電介層的形成包含沉積製程,例如,化學氣相沉積、物理氣相沉積、高密度電漿(HDP)、旋轉沉積(SOD)、原子層沉積或其他合適的製程。考量閘極堆疊的閘極高度,層間電介層的厚度為約90nm至約500nm。在一些情況下,較大的厚度增加了製造成本及處理時間。較小的厚度導致層間電介層下的閘極堆疊覆蓋不足。形成層間電介層後進行平坦化製程(例如,化學機械平坦化(CMP)、蝕刻製程或其他合適的製程)去除多餘的層間電介層以產生實質上平坦的閘極堆疊頂表面。在第一閘極堆疊及第二閘極堆疊包含硬掩膜的一些實施方式中,在平坦化製程期間去除整個硬掩膜和間隔物的頂部部分。在一些實施方式中,犧牲膜作為平坦化停止層。平坦的頂表面有助於提高後續微影製程的精密度。
方法200繼續進行至操作250,去除犧牲膜以在層間電介層中形成第一溝槽及第二溝槽。藉由蝕刻溶液去除 犧牲膜,蝕刻溶液例如為氫氧化銨溶液(ammonium hydroxide solution)、稀氫氟酸和/或其他合適的蝕刻劑。在一些實施方式中,藉由乾蝕刻製程去除犧牲膜。蝕刻劑的實例包含氟和/或氯基的蝕刻劑。去除製程導致第一溝槽及第二溝槽被其中填充如金屬的導電層的間隔物限定,如同通常在閘極替換製程中所執行的,也被稱為後閘極技術(gate last technique)。在一些實施方式中,執行去除製程直到第一絕緣膜及第二絕緣膜暴露。在一些實施方式中,去除製程包含同時去除第一絕緣膜及第二絕緣膜。在一些實施方式中,去除第一絕緣膜及第二絕緣膜包含連續的步驟。在一些實施方式中,去除第一絕緣膜及第二絕緣膜包含液相或氣相稀釋的氫氟酸。
方法200繼續進行至操作260,塗佈保護層以填充第二溝槽。在一些實施方式中,保護層為光阻。在第一絕緣膜及第二絕緣膜被暴露且第二絕緣膜的厚度等於輸入/輸出閘極介電膜的厚度的一些實施方式中,保護層選擇性地塗佈第二溝槽。在去除犧牲膜期間去除第一絕緣膜及第二絕緣膜的一些實施方式中,形成輸入/輸出閘極介電膜在第一溝槽和第二溝槽中,並且形成保護層在第二溝槽上。
方法200繼續進行至操作270,從第一溝槽去除第一絕緣膜。在一些實施方式中,藉由蝕刻溶液如氫氧化銨溶液和氫氟酸的組合和/或其他合適的蝕刻劑去除第一絕緣膜。在一些實施方式中,藉由乾蝕刻製程去除第一絕緣膜。蝕刻劑的實例包含氯基蝕刻劑。
方法200繼續進行至操作280,使用非水溶劑基化學品(non-aqueous solvent-based chemical)形成第一氧化物膜(如第1圖中的介面層150b)在第一溝槽中。非水溶劑基化學品包含濃度小於8%的非水溶劑基化學品的水溶液,以幫助減少水溶性通道層的損失。在一些實施方式中,非水溶劑基化學品為有機非質子溶劑。非質子溶劑為不含不穩定氫的溶劑。非水溶劑基化學品的實例包含碳酸丙烯酯、乙醇胺、環丁碸、N-甲基吡咯烷酮、二甲基亞碸、二甲基乙醯胺或其他合適的化學品。為了在涉及化學反應時幫助提高溶劑的穩定性,非水溶劑基化學品的電位窗口(potential window,也被稱為電化學窗口)為約-4伏特至約+4伏特。此外,為了在濕氧化製程期間以酸和鹼取代水,非水溶劑基化學品的介電常數大於20。在一些實施方式中,非水溶劑基化學品為無水的(即,0%水)。非水溶劑基化學品混和但不限於氧化劑,例如過氧化氫、臭氧、硫酸、硝酸、過二硫酸(peroxydisulfuric acid)、過一硫酸(peroxymonosulfuric acid)和介面活性劑,以和其下的通道層執行濕氧化製程。在一些實施方式中,非水溶劑基化學品具有大於60℃的閃點。閃點是揮發性物質暴露於火源時點燃的最低溫度。在一些情況下,較低的閃點在製造過程中增加了點燃的可能性。
在一些實施方式中,第一氧化物膜的厚度為約5Å至約10Å。在一些情況下,較大的厚度增加了製造成本和時間,且沒有顯著的益處。在一些實施方式中,較小的厚 度增加了介面缺陷密度。在至少一實施方式中,第一氧化物膜的生長速率為約0.5Å/秒至約10Å/秒。本領域具通常知識者應理解,即使通道層為非水溶性(例如矽通道層),第一氧化物膜的濕氧化也會發生。
在一些實施方式中,為了去除汙染物如顆粒和離子,非水溶劑基化學品與氫氧化銨溶液、氯化氫和/或氟化氫混和。和其他方法相比,由於使用非水溶劑基化學品,通道層和第一氧化物膜的損失相對地輕微。在一些實施方式中,第一氧化物膜的底表面與間隔物的底表面之間的高度差為約0Å至約6Å。也就是說,和其他方法相比,氧化物和/或通道層的體積損失小於約2至3個數量級。和使用其他方法形成氧化物膜相比,使用非水溶劑基化學品還在第一氧化物膜與通道層之間的介面處以及第一氧化物膜與閘極介電膜之間的介面處提供更平滑的表面。在一些實施方式中,每平方微米面積的粗粗糙度均方根(RMS)為約1Å至約3Å。氧化物和通道層損失的減少及更平滑的表面有助於保持穩定的飽和電流(Isat)、持久的時間相關介電層崩潰(TDDB)以及更小的臨界電壓(Vt)偏移。因此,與使用其他製程形成的半導體裝置相比,此半導體裝置的實際性能更接近設計性能。在一些實施方式中,考量第一氧化物膜的預定厚度,濕氧化的處理時間持續約10秒至約15分鐘,並且處理溫度為約25℃至約65℃。
在一些實施方式中,在形成第一氧化物膜的期間同時去除被塗佈以填充第二溝槽的保護層。在一些實施方 式中,去除保護層之後形成第一氧化物膜。在一些實施方式中,例如使用氫氟酸或氫氧化銨-過氧化氫-水混和物(APM)的清洗製程於第一溝槽中形成第一氧化物膜之前執行。
在一些實施方式中,在操作250中不形成第二溝槽,並且省略操作260。在操作250中不形成第二溝槽的一些實施方式中,以單獨的操作形成第二溝槽,例如在第一溝槽形成第一氧化物膜之後。在一些實施方式中,由於方法200中包含額外的圖案化及蝕刻操作,在與形成第一溝槽分開的操作中形成第二溝槽增加了方法200的複雜性。
第3A-3H圖為根據本揭露之各種實施方式繪示的半導體裝置300的製程各步驟截面圖。半導體裝置300包含與半導體裝置100相似的元件,並且相似元件的編號最後兩位數字相同。第3A圖為操作210之後的半導體裝置300截面圖。半導體裝置300包含基板310、複數個鰭結構311以及複數個隔離特徵312。半導體裝置300還包含第一操作區320A和第二操作區320B。在一些實施方式中,第一操作區320A表示核心電路區並且第二操作區320B表示輸入/輸出(I/O)電路區。第一操作區320A具有第一絕緣膜316A並且第二操作區320B具有第二絕緣膜316B。在一些實施方式中,第一絕緣膜316A和第二絕緣膜316B選擇性的形成在鰭結構111的主動區上。在一些實施方式中,第一絕緣膜316A和第二絕緣膜316B覆蓋隔離特徵312。第一操作區320A和第二操作區320B中的每一個都包含通道層314。在一些實施方式中,通道層314佔據第一操作區320A和第二操作區 320B的一部分主動區。在此種方式中,每個操作區具有至少兩種類型的通道區域。在一些實施方式中,通道層314佔據第一操作區320A或第二操作區320B中的至少一個的整個主動區。
在一些實施方式中,通道層314包含用於提高性能的含鍺材料,例如鍺或矽鍺,特別是在p型裝置中。在鰭結構111包含晶體中的矽、多晶或非晶結構的一些實施方式中,藉由磊晶生長或沉積製程在鰭結構111的頂表面形成通道層314。在一些實施方式中,去除一部分的鰭結構111以形成凹槽,並且形成通道層314以填充凹槽。也就是說,通道層314的頂表面在鰭結構111的原始頂表面的上表面之上、共平面或之下。在鰭結構111包含鍺的一些實施方式中,藉由與上述類似的方法形成通道層以區別通道層314。
第3B圖為操作220之後的半導體裝置300截面圖。藉由沉積製程形成犧牲膜317及硬掩膜319在第一絕緣膜316A、第二絕緣膜316B及隔離特徵112上。在一些實施方式中,沉積犧牲膜317是藉由與硬掩膜319相同的方法。在一些實施方式中,沉積犧牲膜317是藉由與硬掩膜319不同的方法。犧牲膜317具有與硬掩膜319不同的蝕刻選擇性。
第3C圖為操作230之後的半導體裝置300截面圖。藉由使用微影製程和蝕刻製程來圖案化及形成複數個閘極堆疊322a’、322b’、322c’及322d’。在蝕刻製程之後,分離第一絕緣膜316A和第二絕緣膜316B以定義介面層350a’、350b’、350c及350d。在至少一實施方式中,閘極 堆疊322a’為n型核心裝置,閘極堆疊322b’為p型核心裝置,閘極堆疊322c’為n型輸入/輸出裝置以及閘極堆疊322d’為p型輸入/輸出裝置。
第3D圖為操作240之後的半導體裝置300截面圖。形成輕微摻雜汲極(LDD)區316在閘極堆疊322a’、332b’、322c’及322d’的相對兩側。形成輕微摻雜汲極(LDD)區316包含一或多個植入製程。每個輕微摻雜汲極(LDD)區316包含基於導電類型的各種摻雜劑。接著,沿著閘極堆疊322a’、332b’、322c’、322d’的側壁形成間隔物330,並限定源極/汲極特徵318的位置。類似地,每個源極/汲極區包含基於導電類型的各種摻雜劑。半導體裝置300還包含沉積在閘極堆疊322a’、332b’、322c’、322d’及鰭結構111上的層間電介層340。
第3E圖為操作250之後的半導體裝置300截面圖。在一些實施方式中,使用平坦化製程以暴露犧牲膜317並去除間隔物330的頂部部分。接著,去除犧牲膜317以暴露介面層350a’、350b’、350c及350d。在層間電介層340中形成溝槽321、323、325及327。在一些實施方式中,在層間電介層340中形成接觸開口,然後填充導電材料以形成接觸插塞與源極/汲極特徵318電性連接。
第3F圖為操作260之後的半導體裝置300截面圖。在介面層350c及350d的厚度滿足輸入/輸出裝置的厚度的一些實施方式中,保護層360覆蓋並填充溝槽325及327。在一些實施方式中,保護層360包含光阻。在一些實施方式 中,保護層360覆蓋整個第二操作區320B。
第3G圖為操作270之後的半導體裝置300截面圖。藉由濕蝕刻製程、乾蝕刻製程或其組合去除介面層350a’及350b’。在一些實施方式中,在單一步驟中去除介面層350a’及350b’。在一些實施方式中,在連續的步驟中去除介面層350a’及350b’。
第3H圖為操作280之後的半導體裝置300截面圖。在由通道層314生長的氧化物為水溶性(例如二氧化鍺或二氧化矽鍺)的一些實施方式中,使用非水溶劑基化學品在鰭結構311的暴露部分上同時形成介面層350a和介面層350b。在通道層314由矽鍺製成的一些實施方式中,介面層350b中二氧化鍺的百分比與通道層340中鍺的百分比成比例。在一些實施方式中,介面層350a包含與介面層350b相同的氧化物。在通道層314包含鍺且鰭結構311a包含矽的一些實施方式中,介面層350a包含與介面層350b不同的氧化物,例如介面層350a包含氧化矽,介面層350b包含氧化鍺。
第4圖為根據本揭露之各種實施方式繪示的半導體裝置400截面圖。半導體裝置400包含元件與半導體裝置100類似的元件,並且相似元件的編號中的最後兩位數字相同。半導體裝置400在由鰭結構411和間隔物430限定的空腔中具有U型介面層450b。介面層450b包含和通道層414平行的第一部分451以及垂直於通道層414的第二部分453。在一些實施方式中,在介面層450b的形成期間,沿著間隔物430的側壁發生氧化過程。在間隔物430包含矽原子 (例如氮化矽或碳氮化矽)的一些情況下,當形成第一部分451時,第二部分453同時包含二氧化矽。因此,在一些實施方式中,當間隔物430包含鍺原子時,第一部分451包含與第二部分453相同的材料;在一些實施方式中,當間隔物430包含矽原子時,第一部分451包含與第二部分453不同的材料。
本揭露之一態樣是關於一種製造半導體結構的方法。此方法包含在第一鰭結構上形成第一絕緣膜及在第二鰭結構上形成第二絕緣膜;在第二絕緣膜上塗佈保護層;去除第一絕緣膜以暴露第一鰭結構的一部分;以及使用非水溶劑基化學品在第一鰭結構的暴露部分上形成第一氧化物膜。在一些實施方式中,形成第一氧化物膜包含使用有機非質子溶劑。在一些實施方式中,形成第一氧化物膜包含使用濃度小於8%的非水溶劑基化學品水溶液。在一些實施方式中,形成第一氧化物膜包含使用非水溶劑基化學品。在一些實施方式中,形成第一氧化物膜包含使用碳酸丙烯酯、乙醇胺、環丁碸、N-甲基吡咯烷酮、二甲基亞碸或二甲基乙醯胺。在一些實施方式中,形成第一氧化物膜包含使用過氧化氫、氫氧化銨溶液、氯化氫、氟化氫、臭氧、硫酸、硝酸、過二硫酸或過一硫酸。在一些實施方式中,此方法還包含去除保護層以暴露第二絕緣膜。在一些實施方式中,去除保護層包含在單一步驟中形成第一氧化物膜及去除保護層。在一些實施方式中,去除保護層包含在連續的步驟中形成第一氧化物膜以及去除保護層。在一些實施方式中,形成第一氧化物膜 包含形成第一氧化物膜以包含至少兩種氧化物材料。
本揭露之另一態樣是關於一種製造半導體裝置的方法。此方法包含在第一鰭結構上形成第一絕緣膜以及在第二鰭結構上形成第二絕緣膜;在第一絕緣膜及第二絕緣膜上沉積犧牲膜;使用蝕刻製程形成第一閘極堆疊及第二閘極堆疊;在第一閘極堆疊及第二閘極堆疊上沉積層間電介層;去除犧牲膜以在層間電介層中形成第一溝槽及第二溝槽;塗佈保護層以填充第二溝槽;從第一溝槽去除第一絕緣膜;以及使用非水溶劑基化學品在第一溝槽中形成第一氧化物膜。在一些實施方式中,此方法還包含在第一鰭結構上形成通道層,其中通道層為水溶性的。在一些實施方式中,形成第一氧化物膜包含以每秒約0.5Å至每秒約10Å的生長速率生長第一氧化物膜。在一些實施方式中,形成第一氧化物膜包含在溫度為約25℃至約65℃生長第一氧化物膜。在一些實施方式中,形成第一氧化物膜包含形成第一氧化物膜以與第二絕緣膜具有相同的化合物。在一些實施方式中,形成第一氧化物膜包含形成第一氧化物膜以與第二絕緣膜具有不同的化合物。在一些實施方式中,此方法還包含在第三鰭結構上形成第三絕緣膜;使用蝕刻製程形成第三閘極堆疊;在第三閘極堆疊上沉積層間電介層;去除犧牲膜以在層間電介層中形成第三溝槽;從第三溝槽中去除第三絕緣膜;以及使用非水溶劑基化學品在第三溝槽中形成第三氧化物膜。第三氧化物膜包含與第一氧化物膜不同的材料。
本揭露之又一態樣是關於一種半導體積體電 路。此半導體積體電路包含具有水溶性通道層的鰭結構以及在水溶性通道層上的閘極結構。閘極結構包含氧化物膜、閘極介電膜以及閘極電極。半導體積體電路還包含沿著閘極結構的間隔物。間隔物和水溶性通道層之間的介面比氧化物膜和水溶性通道層之間的介面高約0Å至約6Å。在一些實施方式中,氧化物膜具有實質上垂直於水溶性通道層的第一部分以及實質上平行於水溶性通道層的第二部分。第一部分包含與第二部分不同的氧化物。
雖然本揭露已以實施方式揭露如上,然其並非用以限定本揭露,任何熟習此技藝者,在不脫離本揭露之精神和範圍內,當可作各種之更動與潤飾,因此本揭露之保護範圍當視後附之申請專利範圍所界定者為準。
Claims (1)
- 一種半導體裝置的製造方法,包含:形成一第一絕緣膜在一第一鰭結構上,以及形成一第二絕緣膜在一第二鰭結構上;塗佈一保護層在該第二絕緣膜上;去除該第一絕緣膜以暴露該第一鰭結構的一部分;以及使用非水溶劑基化學品形成一第一氧化物膜在該第一鰭結構的暴露部分上。
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KR100625175B1 (ko) * | 2004-05-25 | 2006-09-20 | 삼성전자주식회사 | 채널층을 갖는 반도체 장치 및 이를 제조하는 방법 |
US8575708B2 (en) * | 2011-10-26 | 2013-11-05 | United Microelectronics Corp. | Structure of field effect transistor with fin structure |
US8614127B1 (en) * | 2013-01-18 | 2013-12-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making a FinFET device |
KR102089682B1 (ko) * | 2013-07-15 | 2020-03-16 | 삼성전자 주식회사 | 반도체 장치 및 이의 제조 방법 |
US9177785B1 (en) * | 2014-05-30 | 2015-11-03 | Taiwan Semiconductor Manufacturing Company Limited | Thin oxide formation by wet chemical oxidation of semiconductor surface when the one component of the oxide is water soluble |
US9761699B2 (en) * | 2015-01-28 | 2017-09-12 | International Business Machines Corporation | Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures |
US9741829B2 (en) * | 2015-05-15 | 2017-08-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9607838B1 (en) * | 2015-09-18 | 2017-03-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Enhanced channel strain to reduce contact resistance in NMOS FET devices |
US9543419B1 (en) * | 2015-09-18 | 2017-01-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET structures and methods of forming the same |
US20170162570A1 (en) * | 2015-12-02 | 2017-06-08 | Advanced Device Research Inc. | Complementary Transistor Pair Comprising Field Effect Transistor Having Metal Oxide Channel Layer |
US9780092B2 (en) * | 2016-02-19 | 2017-10-03 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device having a filling conductor comprising a plug portion and a cap portion and manufacturing method thereof |
US10297505B2 (en) * | 2017-04-26 | 2019-05-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and fabrication method therefor |
-
2018
- 2018-01-23 US US15/877,958 patent/US10297505B2/en active Active
- 2018-03-19 TW TW107109322A patent/TW201839823A/zh unknown
- 2018-03-21 CN CN201810234683.5A patent/CN108807271A/zh active Pending
-
2019
- 2019-05-20 US US16/417,050 patent/US11101178B2/en active Active
-
2021
- 2021-07-29 US US17/388,512 patent/US20210358812A1/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI692854B (zh) * | 2019-01-30 | 2020-05-01 | 大陸商長江存儲科技有限責任公司 | 具有垂直擴散板的電容器結構 |
CN111653627A (zh) * | 2019-01-30 | 2020-09-11 | 长江存储科技有限责任公司 | 具有垂直扩散板的电容器结构 |
US10777690B2 (en) | 2019-01-30 | 2020-09-15 | Yangtze Memory Technologies Co., Ltd. | Capacitor structure having vertical diffusion plates |
Also Published As
Publication number | Publication date |
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US20200006150A1 (en) | 2020-01-02 |
CN108807271A (zh) | 2018-11-13 |
US10297505B2 (en) | 2019-05-21 |
US20180315661A1 (en) | 2018-11-01 |
US20210358812A1 (en) | 2021-11-18 |
US11101178B2 (en) | 2021-08-24 |
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