CN108717889A - A kind of voltage dependent resistor chip - Google Patents
A kind of voltage dependent resistor chip Download PDFInfo
- Publication number
- CN108717889A CN108717889A CN201810766871.2A CN201810766871A CN108717889A CN 108717889 A CN108717889 A CN 108717889A CN 201810766871 A CN201810766871 A CN 201810766871A CN 108717889 A CN108717889 A CN 108717889A
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- Prior art keywords
- piezoresistive wafer
- piezoresistive
- wafer
- dependent resistor
- voltage dependent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C1/00—Details
- H01C1/04—Arrangements of distinguishing marks, e.g. colour coding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C1/00—Details
- H01C1/14—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C1/00—Details
- H01C1/16—Resistor networks not otherwise provided for
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C13/00—Resistors not provided for elsewhere
- H01C13/02—Structural combinations of resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
- H01C7/10—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
- H01C7/12—Overvoltage protection resistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
The invention discloses a kind of voltage dependent resistor chips, including the first piezoresistive wafer, the second piezoresistive wafer and leading-out terminal, the first piezoresistive wafer series connection, second piezoresistive wafer, form a single port combinational circuit, wherein, performance of the performance of the first piezoresistive wafer tolerance surge impact higher than second piezoresistive wafer tolerance surge impact；At least one in two leading-out terminals of the single port combinational circuit is low thermal resistance heat conduction end, low thermal resistance heat conduction end with one of in first piezoresistive wafer, second piezoresistive wafer or two are thermally coupled to each other simultaneously.The gap that this technology is resistant to the performance of surge impact by artificially manufacturing two panels piezoresistive wafer, when making the deterioration breakdown of the second piezoresistive wafer, the first piezoresistive wafer is substantially intact, and the thermal stability that is not lowered substantially using it realizes safety release.
Description
Technical field
The present invention relates to field of power supplies, more particularly to a kind of voltage dependent resistor chip.
Background technology
Surge Protector (abbreviation SPD) is widely used in as a kind of low-voltage electrical apparatus of standard in low pressure electric line,
To occurring the surge caused by thunder and lightning etc. in circuit can effectively absorb and inhibit, to improving grid power transmission quality, protecting
Demonstrate,proving electrical appliance safely has apparent effect.
The core component of SPD is Surge suppression element, and the most commonly used is based varistor chips.Due to electric line
Transmission range is longer, but be easy to be exposed to it is outdoor, compared to indoor electric appliance equipment be easier by high-energy surge pulse, in SPD
Phase projected life in, based varistor chip be easier by the high-energy surge more than rated specification repeat impact,
Cause the deterioration failure of varistor.Since varistor is short circuit failure mode, once breakdown failure, will cause supply lines
Road short trouble, breakdown point will appear burst, smolder, arcing, it is serious when in addition catching fire can be caused.
The schematic diagram of most common ameliorative way is shown in attached drawing 1, on two end electrodes of based varistor chip 1,
It being respectively welded and connects a piece of conductive and all excellent heat conductivility scale copper electrode 2, scale copper electrode 2 is prefabricated with leading-out terminal 3,
Scale copper electrode 2 also forms thermal coupling while playing the role of conductive electrode with based varistor chip 1, can be by pressure-sensitive electricity
The heat that resistance ceramic chip 1 generates is transmitted on leading-out terminal 3.It is welded wherein with low-melting alloy 5 on a leading-out terminal 3
A piece of elastic sheet metal 4 forms overheat disconnector.When based varistor chip 1, which is deteriorated to leakage current, enters milliampere grade, open
Begin to enter accelerated deterioration area, leakage current can make the fever of based varistor chip 1 that leakage current be promoted to further increase, and accelerate
Based varistor chip 1 generates heat, and will finally make 1 thermal breakdown of based varistor chip.But it is closed when heat reaches low melting point
When golden 5 fusing-off temperature, disconnector action power dump is overheated, based varistor chip 1 is made to exit power grid before puncture short,
Protection is achieved the purpose that.The program can be by the failure mode of most based varistor chip 1 from pernicious short-circuit mode
Being converted to influences the open circuit mode of very little, greatly improves the safety of SPD.
But still there is also some defects for the program, since the action of overheat disconnector needs to be delayed by several seconds the time, and
1 leakage current of based varistor chip enters milliampere grade and starts accelerated deterioration adstante febre, and the defect inside porcelain body is very serious
, have the defect of partial chip serious to very short to the time of puncture short from starting to generate heat, heat also has little time to be transmitted to
Hot disconnector melts low-melting alloy 5, and short circuit accident just has occurred.Another much situation is exactly when pressure-sensitive electricity
Resistance ceramic chip 1 is deteriorated to when closing on accelerated deterioration area, and at this moment the leakage current of based varistor chip 1 is also less than milliampere grade,
It can also maintain thermostabilization, additionally it is possible to work is maintained under the operating voltage of power grid, but its pressure sensitive voltage value at this time has compared
Initial value when just starting to come into operation, which has, significantly significantly to be declined, the anti-surge punching of based varistor chip 1 at this moment
The ability hit is very fragile, an energy not counting it can be punctured or close to breakdown by too big surge, at this time it
Puncture short speed is also too fast, and overheat disconnector has little time response action and do not have protective effect.
Invention content
It is an object of the invention to overcome the above-mentioned deficiency in the presence of the prior art, a kind of voltage dependent resistor chip is provided.
In order to achieve the above-mentioned object of the invention, the present invention provides following technical schemes：
A kind of voltage dependent resistor chip, including the first piezoresistive wafer, the second piezoresistive wafer and leading-out terminal, described first
Piezoresistive wafer is connected with second piezoresistive wafer, forms a single port combinational circuit, wherein the first pressure-sensitive electricity
Hinder performance of the performance higher than second piezoresistive wafer tolerance surge impact of piece tolerance surge impact；
At least one in two leading-out terminals of the single port combinational circuit is low thermal resistance heat conduction end, the low-heat
One of in resistance heat conduction end and second piezoresistive wafer, first piezoresistive wafer or two mutually hot simultaneously
Coupling.In use, connecting overheat disconnector in low thermal resistance heat conduction end.
The principle Analysis of the present invention is as follows：
The series loop being made of the first piezoresistive wafer, the second piezoresistive wafer is to absorb the main channel of surge pulse,
When not having surge pulse, varistor is in high-impedance state.When surge arrives, varistor is in low resistive state, surge energy
Amount thus release by circuit.At this point, the voltage-limiting protection level of SPD is regarded as the residual voltage value of the first piezoresistive wafer and second pressure-sensitive
The sum of residual voltage value of resistor disc.After surge disappears, piezoresistive wafer returns to high-impedance state.In order to ensure the member in surge channel
Device degradation in tolerance surge impact capacity selection, will should follow the first piezoresistive wafer since the second piezoresistive wafer
Tolerance be more than the principle of the second piezoresistive wafer, significantly deteriorated when the second piezoresistive wafer with reaching, or even hit
When wearing short circuit, the also substantially intact purpose of the first piezoresistive wafer.
The Analysis of Failure Mechanism of the present invention is as follows：
Since the first piezoresistive wafer anti-impulse performance is better than the second piezoresistive wafer, they are to be connected on surge again
It absorbs in major loop, in practical applications, by the long-term impact of multiple surge, always the second piezoresistive wafer first starts bad
Change, once deterioration to a certain extent, such as pressure sensitive voltage value be reduced to initial value 10% hereinafter, pressure-sensitive porcelain body internal structure just
The case where greatly being destroyed, just will present accelerated deterioration at this time, several less big surges can puncture it.Such as
The pressure sensitive voltage value of first piezoresistive wafer is selected properly by fruit so that concatenated second piezoresistive wafer breakdown or close breakdown
When, the network voltage accessed just makes the first piezoresistive wafer enter accelerated deterioration area, flows through its electric current at more than ten milliamperes
It is best between to 200 milliamperes, due to the first piezoresistive wafer anti-impulse performance it is stronger and almost without being destroyed, heat is steady
It is qualitative, without breakdown, can to make low thermal resistance closer to not used new tile, the long period that can generate heat under above-mentioned electric current
Heat conduction end has more plenty of time that heat outflow is made its action to overheat disconnector, cuts off circuit, makes the SPD safety of damage
Ground exits power grid.It, will soon since overheat disconnector is generally provided with positioning indicator or electricity, sound, light warning device
It is found, maintenance personal can easily replace, and achieve the purpose that safe handling.To substantially increase the peace of SPD
Full property and reliability, the electrical equipment crash rate connected on circuit also will significantly reduce.
Undamaged piezoresistive wafer is compared with the piezoresistive wafer that serious pressure sensitive voltage value declines to a great extent is damaged, this two
Index difference is huge：First, anti-impulse ability, is impacted 1 time with nominal current In, undamaged varistor
The front and back pressure sensitive voltage value of piece impact has almost no change, and pressure sensitive voltage value has deteriorated 30% piezoresistive wafer, then uses
After In impacts 1 time, pressure sensitive voltage value can decline 10~30% or even 1 times again to be punctured.Besides thermostabilization
Property, original new tile can not breakdown in a short time, production by hundreds of milliamperes even 1~2 ampere of electric current
Raw heat is enough that the low-melting alloy fusing of disconnector will be overheated, and cuts off the power.And it is damaged serious piezoresistive wafer only
Apply 200 milliamperes of electric currents below to be possible to puncture in 1~2 second, disconnector will be overheated by, which at all having little time, is heated to act
It threads off.Therefore, this technology seeks to the gap of the performance of artificial manufacture two panels piezoresistive wafer tolerance surge impact, makes second
When piezoresistive wafer deterioration breakdown, the first piezoresistive wafer is substantially intact, the thermal stability not being lowered substantially using it come
Realize safety release.
Preferably, the first piezoresistive wafer electrode surface area of first piezoresistive wafer is more than the described second pressure-sensitive electricity
Hinder the second piezoresistive wafer electrode surface area of piece.Weighing piezoresistive wafer tolerance surge impact capacity has multinomial technical indicator,
It is main to have：Dash current Iimp, current waveform is 10/350 μ s；Maximum discharge current Imax, current waveform is 8/20 μ s；Energy
Tolerance, current waveform are 2ms square waves；Rush of current stability is exactly with 8/20 μ s waveform nominal discharge current In repeated impacts
The number etc. being resistant to.Under identical geometric dimension, by adjusting ceramic formula or technological parameter can optimize one of which or
Multiple parameters index, but want General Promotion or relatively difficult.But these technical indicators are all and varistor plate electrode
Area is directly proportional, therefore, as long as increasing the area of the first varistor plate electrode under the conditions of same process, so that it may to ensure to be resistant to
Surge impact capacity is comprehensively more than the second piezoresistive wafer.
Preferably, the nominal diameter of first piezoresistive wafer is nominal straight at least more than second piezoresistive wafer
One sequence number of diameter.Since the diameter of flanking sequence number is than about 1.25 times, they are resistant to the parameter difference of surge impact capacity
About 1.5 times, as long as the second piezoresistive wafer is designed to match with application environment, then the first piezoresistive wafer belongs to
Redundancy Design, crash rate will be reduced than the second piezoresistive wafer in the order of magnitude, so that it may to ensure to allow the second piezoresistive wafer first
Deterioration.
Preferably, the pressure sensitive voltage value of first piezoresistive wafer is the 0.75 of accessed network operation voltage peak
To 0.85 times.It can ensure that the network voltage accessed just makes in the case of the second piezoresistive wafer thorough puncture short
First piezoresistive wafer enters accelerated deterioration area, and it is best between more than ten milliamperes to 200 milliamperes to flow through its electric current, utilizes it
Substantially the characteristics of thermal stability not being destroyed is closer to not used new tile maintains longer fever time without being hit
It wears, makes low thermal resistance heat conduction end have more plenty of time that heat is output to overheat disconnector, make its action power dump.When
When the pressure sensitive voltage value of one piezoresistive wafer is selected too low, the initial current for flowing through it is excessive, can shorten it and remain heat-staple
Time.When selecting excessively high, the initial current for flowing through it is too small, is not enough to the process of Acceleration of starting deterioration.
Preferably, described is welded and connected on a second piezoresistive wafer electrode surface of second piezoresistive wafer
Another electricity of one electrode surface of one piezoresistive wafer, second piezoresistive wafer and/or first piezoresistive wafer
Low thermal resistance heat conduction end is also welded on pole-face, to realize the thermal coupling of element.
Preferably, the low thermal resistance heat conduction end with heat conduction function has foot using excellent materials of heat conductivilitys such as copper
Enough big cross-sectional areas.And pyrotoxin varistor on piece is connected to using thermal couplings modes such as welding, and heat conduction end away from
The distance of pyrotoxin will be as possible it is short, to obtain minimum thermal resistance, guarantee has enough heats to be transmitted to overheat disconnector.
Preferably, second piezoresistive wafer, the first piezoresistive wafer are packaged as a whole.
Preferably, first piezoresistive wafer is formed by two panels with the pressure-sensitive tile parallel connection of size.
Preferably, the impact resistance current rating of first piezoresistive wafer is resistance to higher than second piezoresistive wafer
Dash current rated value.
Compared with prior art, beneficial effects of the present invention：
The master that the present invention is equipped with the absorption surge pulse being composed in series by the first piezoresistive wafer, the second piezoresistive wafer is led to
Road and reliability are better than the first piezoresistive wafer of the second piezoresistive wafer, in the second piezoresistive wafer elder generation deterioration failure
In the case of, the first substantially intact piezoresistive wafer can make the overheat disconnector action power dump of SPD so that SPD finally with
Open circuit mode exits circuit, relative to traditional short-circuit mode, greatly improves the safety of SPD, it is therefore prevented that short circuit breakdown
When generate smolder, arcing, even catching fire serious accident.Meanwhile overheat the positioning indicator that is equipped with of disconnector or
Person's electricity, sound, light warning device so that the SPD of damage will soon be found, and maintenance personal can easily replace, and reach
The purpose for having arrived safe handling, to substantially increase the safety and reliability of SPD, the electrical equipment connected on circuit fails
Rate also will significantly reduce.
The gap that this technology is resistant to the performance of surge impact by artificially manufacturing two panels piezoresistive wafer, makes the second pressure-sensitive electricity
When hindering piece deterioration breakdown, the first piezoresistive wafer is substantially intact, and the thermal stability not being lowered substantially using it is pacified to realize
It is complete to thread off.
Description of the drawings：
Fig. 1 is the principle schematic of the improvement plan described in background technology.
It is marked in Fig. 1：1- based varistor chips, 2- scale copper electrodes, 3- leading-out terminals, 4- elastic sheet metals, 5-
Low-melting alloy.
Fig. 2 is a kind of principle schematic of voltage dependent resistor chip of the present invention.
Fig. 3 is a kind of part drawing of voltage dependent resistor chip described in the embodiment of the present invention 1.
Fig. 4 is a kind of assembling figure of voltage dependent resistor chip described in the embodiment of the present invention 1.
Fig. 5 is a kind of part drawing of voltage dependent resistor chip described in the embodiment of the present invention 2.
Fig. 6 is a kind of assembling figure of voltage dependent resistor chip described in the embodiment of the present invention 2.
It is marked in Fig. 2-Fig. 6：The first piezoresistive wafers of 1-, 11- the first piezoresistive wafer electrode surfaces, the second varistors of 2-
Piece, 21- the second piezoresistive wafer electrode surfaces, 3- leading-out terminals.
Specific implementation mode
With reference to test example and specific implementation mode, the present invention is described in further detail.But this should not be understood
It is only limitted to embodiment below for the range of the above-mentioned theme of the present invention, it is all that this is belonged to based on the technology that the content of present invention is realized
The range of invention.
Embodiment 1
As shown in figs 2-4, a kind of voltage dependent resistor chip, including the first piezoresistive wafer 1, the second piezoresistive wafer 2, draw
Going out terminal 3, first piezoresistive wafer 1 is connected with second piezoresistive wafer 2, forms a single port combinational circuit,
Wherein, first piezoresistive wafer 1 is resistant to the performance of surge impact higher than second piezoresistive wafer 2 tolerance surge impact
Performance.
At least one in two leading-out terminals 3 of the single port combinational circuit is low thermal resistance heat conduction end, described low
Thermal resistance heat conduction end and 1 thermal coupling of the first piezoresistive wafer, in use, de- in low thermal resistance heat conduction end connection overheat
From device.
11 area of the first piezoresistive wafer electrode surface of first piezoresistive wafer 1 is more than second piezoresistive wafer
2 21 area of the second piezoresistive wafer electrode surface, the nominal diameter of first piezoresistive wafer 1 is at least more than second pressure
One sequence number of nominal diameter of quick resistor disc 2, the pressure sensitive voltage value of first piezoresistive wafer 1 are accessed power grid works
Make voltage peak 0.75 to 0.85 times.
Specifically assembling mode is：
First piezoresistive wafer 1 selects the pressure-sensitive tile 50k241 of the rectangle of nominal diameter 50mm, pressure sensitive voltage 240
Volt, maximum discharge current Imax are 60KA.Second piezoresistive wafer 2 selects the pressure-sensitive tile of square of nominal diameter 40mm
40k391, pressure sensitive voltage are 390 volts, and maximum discharge current Imax is 40KA.The parameter selection is suitble in 220 volts of common frequency power networks
The operating temperature of work, the overheat disconnector mating with it is 120 DEG C.
First pressure is welded and connected on one the second piezoresistive wafer electrode surface 21 of second piezoresistive wafer 2
One the first piezoresistive wafer electrode surface 11 of quick resistor disc 1, another first varistor of first piezoresistive wafer 1
It is also welded with low thermal resistance heat conduction end on plate electrode face 11, a piece of bullet is welded with low-melting alloy on low thermal resistance heat conduction end
Property sheet metal formed overheat disconnector.First piezoresistive wafer 1, the second piezoresistive wafer 2 are packaged as a whole.
Package unit is connected on 220 coucher frequency circuits, and applies the surge repeated impacts of In=20KA, the 86th punching
Disconnector action is overheated after hitting, and is cooled to after room temperature and is tested the second piezoresistive wafer 2 and deteriorated breakdown, and the first varistor
Piece 1 is still 238 volts, is remained unchanged substantially.
Embodiment 2
As shown in Fig. 5-Fig. 6, the present embodiment difference from example 1 is that, first piezoresistive wafer 1 is by two
The pressure-sensitive tile (40K241x2) of square of piece nominal diameter 40mm is in parallel to be formed, and equivalent substitution is to reduce mounting surface after parallel connection
Product, the parallel way are the usual manner that the industry uses for reduction mounting area, and 1 voltage of the first piezoresistive wafer is 240
Volt, maximum discharge current Imax are 80KA.Second piezoresistive wafer 2 selects the pressure-sensitive tile of square of nominal diameter 40mm
40K391, pressure sensitive voltage are 390 volts, and maximum discharge current Imax is 40KA.Reference selection is suitble in 220 volts of common frequency power networks
The operating temperature of work, the overheat disconnector mating with it is 120 DEG C.
Package unit is connected on 220 coucher frequency circuits, and applies the surge repeated impacts of In=20KA, the 101st time
Disconnector action is overheated after impact, is cooled to after room temperature and is tested the second piezoresistive wafer 2 and deteriorated breakdown, and the first pressure-sensitive electricity
It is 240 volts to hinder piece 1 still, is remained unchanged.
Above example is only to illustrate the present invention and not limits technical solution described in the invention, although this explanation
Book is with reference to above-mentioned each embodiment to present invention has been detailed description, but the present invention is not limited to above-mentioned specific implementation
Mode, therefore any modify to the present invention or equivalent replacement；And the technical side of all spirit and scope for not departing from invention
Case and its improvement, are intended to be within the scope of the claims of the invention.
Claims (8)
1. a kind of voltage dependent resistor chip, including the first piezoresistive wafer (1), the second piezoresistive wafer (2) and leading-out terminal (3),
It is characterized in that, first piezoresistive wafer (1) is connected with second piezoresistive wafer (2), a single port group is formed
Close circuit, wherein the performance of the first piezoresistive wafer (1) tolerance surge impact is higher than second piezoresistive wafer (2)
It is resistant to the performance of surge impact；
At least one in two leading-out terminals (3) of the single port combinational circuit is low thermal resistance heat conduction end, the low-heat
One of hinder in heat conduction end and first piezoresistive wafer (1), second piezoresistive wafer (2) or two simultaneously
It is thermally coupled to each other.
2. a kind of voltage dependent resistor chip according to claim 1, which is characterized in that first piezoresistive wafer (1)
First piezoresistive wafer electrode surface (11) area is more than the second piezoresistive wafer electrode surface of second piezoresistive wafer (2)
(21) area.
3. a kind of voltage dependent resistor chip according to claim 1, which is characterized in that first piezoresistive wafer (1)
One sequence number of nominal diameter of nominal diameter at least more than second piezoresistive wafer (2).
4. a kind of voltage dependent resistor chip according to claim 1, which is characterized in that first piezoresistive wafer (1)
Pressure sensitive voltage value is 0.75 to 0.85 times of accessed network operation voltage peak.
5. a kind of voltage dependent resistor chip according to claim 1, which is characterized in that second piezoresistive wafer (2)
A first pressure-sensitive electricity of first piezoresistive wafer (1) is welded and connected on one the second piezoresistive wafer electrode surface (21)
It hinders plate electrode face (11), another the first piezoresistive wafer electrode surface (11) of first piezoresistive wafer (1) and/or described
It is also welded with low thermal resistance heat conduction end on another the second piezoresistive wafer electrode surface (21) of second piezoresistive wafer (2).
6. a kind of voltage dependent resistor chip according to claim 5, which is characterized in that second piezoresistive wafer (2),
One piezoresistive wafer (1) is packaged as a whole.
7. a kind of voltage dependent resistor chip according to claim 5, which is characterized in that first piezoresistive wafer (1) by
Two panels is formed with the pressure-sensitive tile parallel connection of size.
8. according to a kind of any voltage dependent resistor chips of claim 1-7, which is characterized in that first piezoresistive wafer
(1) impact resistance current rating is higher than the impact resistance current rating of second piezoresistive wafer (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810766871.2A CN108717889A (en) | 2018-07-12 | 2018-07-12 | A kind of voltage dependent resistor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810766871.2A CN108717889A (en) | 2018-07-12 | 2018-07-12 | A kind of voltage dependent resistor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108717889A true CN108717889A (en) | 2018-10-30 |
Family
ID=63913653
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810766871.2A Withdrawn CN108717889A (en) | 2018-07-12 | 2018-07-12 | A kind of voltage dependent resistor chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108717889A (en) |
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2018
- 2018-07-12 CN CN201810766871.2A patent/CN108717889A/en not_active Withdrawn
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| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20181030 |
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