CN209072060U - A kind of surge protection circuit and surge protective device - Google Patents
A kind of surge protection circuit and surge protective device Download PDFInfo
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- CN209072060U CN209072060U CN201821459140.5U CN201821459140U CN209072060U CN 209072060 U CN209072060 U CN 209072060U CN 201821459140 U CN201821459140 U CN 201821459140U CN 209072060 U CN209072060 U CN 209072060U
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Abstract
The utility model discloses a kind of surge protection circuit and surge protective devices, protecting circuit includes the first piezoresistive wafer, second piezoresistive wafer, third piezoresistive wafer, posive temperature coefficient thermistor piece, gas-discharge tube and leading-out terminal, first piezoresistive wafer is connected with gas-discharge tube, posive temperature coefficient thermistor piece is connected with third piezoresistive wafer, it connects again with the second piezoresistive wafer after two series arms are in parallel, form a single port combinational circuit, wherein, first piezoresistive wafer and the performance of gas-discharge tube tolerance surge impact are above the performance of the second piezoresistive wafer tolerance surge impact;At least one in two leading-out terminals of single port combinational circuit is the thermally conductive end of low thermal resistance, second piezoresistive wafer, third piezoresistive wafer and posive temperature coefficient thermistor piece form thermal coupling, and the thermally conductive end of low thermal resistance is thermally coupled to each other simultaneously with wherein one or two in the second piezoresistive wafer, posive temperature coefficient thermistor piece.
Description
Technical field
The utility model relates to field of power supplies, in particular to a kind of surge protection circuit and surge protective device.
Background technique
A kind of low-voltage electrical apparatus of the Surge Protector (abbreviation SPD) as standard, is widely used in low pressure electric line,
The surge as caused by thunder and lightning etc. occurred in route effectively can be absorbed and be inhibited, to improvement grid power transmission quality, be protected
Card electrical appliance has safely apparent effect.
The core component of SPD is Surge suppression element, and the most commonly used is based varistor chips.Due to electric line
Transmission range is longer, but be easy to be exposed to it is outdoor, compared to indoor electric appliance equipment be easier by high-energy surge pulse, in SPD
Phase projected life in, based varistor chip be easier by be more than rated specification high-energy surge repeat impact,
Cause the deterioration failure of varistor.Since varistor is short circuit failure mode, once breakdown failure, will cause supply lines
Road short trouble, breakdown point will appear burst, smolder, arcing, it is serious when in addition will cause catching fire.
Improvement plan is first is that most common method, concrete principle figure are shown in attached drawing 1, at two of based varistor chip 1
It on end electrode, is respectively welded and connects a piece of conductive and all excellent heating conduction scale copper electrode 2, scale copper electrode 2 is prefabricated
There is leading-out terminal 3, scale copper electrode 2 also forms thermal coupling with based varistor chip 1 while playing the role of conductive electrode
It closes, the heat that based varistor chip 1 generates can be transmitted on leading-out terminal 3.Wherein with low on a leading-out terminal 3
Melting alloy 5 welds a piece of elastic sheet metal 4 and forms overheat disconnector.It is flowed into when based varistor chip 1 is deteriorated to electric leakage
When entering milliampere grade, accelerated deterioration area is initially entered, leakage current can make the fever of based varistor chip 1 promote leakage current further
Increase, and accelerate the fever of based varistor chip 1, will finally make 1 thermal breakdown of based varistor chip.When heat reaches
When 5 fusing-off temperature of low-melting alloy, disconnector action power dump is overheated, makes based varistor chip 1 before puncture short
Power grid is exited, has achieved the purpose that protection.The program can be by the failure mode of most based varistor chip 1 from pernicious
Short-circuit mode is converted to the open circuit mode for influencing very little, greatly improves the safety of SPD.
But still there is also some defects for the program, since the movement of overheat disconnector needs to be delayed by several seconds the time, and
1 leakage current of based varistor chip enters milliampere grade and starts accelerated deterioration adstante febre, and the defect inside porcelain body is very serious
, there is the defect of partial chip seriously to arrive very short to the time of puncture short from starting to generate heat, heat also has little time to be transmitted to
Hot disconnector melts low-melting alloy 5, and short circuit accident just has occurred.Another much situation is exactly when pressure-sensitive electricity
Resistance ceramic chip 1 is deteriorated to when closing on accelerated deterioration area, and at this moment the leakage current of based varistor chip 1 is also less than milliampere grade,
It can also maintain thermostabilization, additionally it is possible to work is maintained under the operating voltage of power grid, but its pressure sensitive voltage value at this time has compared
Initial value when just starting to come into operation has apparent sharp fall, the anti-surge punching of based varistor chip 1 at this moment
The ability hit is very fragile, an energy not counting it can be punctured or close to breakdown by too big surge, at this time it
Puncture short speed is also that too fastly, overheat disconnector has little time response action and do not have protective effect.
For improvement plan second is that application No. is 201310268111.6 Chinese utility model patent, schematic diagram is shown in attached drawing 2,
It will connect again with piezoresistive wafer 11 after ceramic positive temperature coefficient thermistor piece 12 and 13 parallel connection of gas-discharge tube, and temperature-sensitive
Resistor disc 12 and piezoresistive wafer 11 are welded together to form thermal coupling, and exit 14 and exit 15 are connected in parallel on by protection power source
On route, using epoxy resin enclosed, solidification after welding lead, encapsulated layer 16 is formed.Its main feature is that when piezoresistive wafer 11 is bad
Change to leakage current to significantly increase and start to generate heat into after accelerated deterioration area, heating temperature is coupled to positive temperature coefficient ceramic temperature-sensitive electricity
Piece 12 is hindered, resistance value rises after keeping it heated, reduces the leakage current for flowing into piezoresistive wafer 11, plays and extends the deterioration time
Effect, and after the heating temperature of piezoresistive wafer 11 reaches the Curie point of thermosensitive resistor film 12, positive temperature coefficient ceramic
Thermosensitive resistor film 12 becomes high-impedance state, limits the increase of leakage current, forces piezoresistive wafer 11 near Curie point
Reach thermal balance, piezoresistive wafer 11 can maintain work under network operation voltage in spite of illness.
But the program still has some serious defects, is firstly because ceramic positive temperature coefficient thermistor piece 12
Metering function, piezoresistive wafer 11 deteriorates severe again, and heating temperature also only maintains the curie point temperature of thermosensitive resistor film 12
Near degree, work is exited without departing from power grid, until the pressure sensitive voltage value deterioration of piezoresistive wafer 12 is reduced to network operation electricity
When the about half of voltage crest value, after concatenated discharge tube is connected for another surge impact, too low pressure sensitive voltage value pincers
The power network current constantly followed causes gas-discharge tube 13 not return to off-state, will protect 12 short circuit of thermosensitive resistor film
Protection circuit failure, at this time piezoresistive wafer 11 will puncture short immediately, cause serious short trouble.Theoretically, if do not had
There are other safeguard procedures, most of varistor can all fail in this way.Another failure procedure and scheme one
Situation is similar, i.e., when piezoresistive wafer 11 deteriorates to a certain extent, even if having not been entered into accelerated deterioration area, but because of its internal junction
Structure has been seriously damaged, and the ability sharp fall of tolerance surge impact, a surge can be hit at this time
It wears or close to breakdown, and gas-discharge tube 13 is also on state at this time, breakdown or same close to the piezoresistive wafer 11 of breakdown
Sample also loses the ability of pincers power-off net follow current, causes thermosensitive resistor film 12 to protect circuit malfunction, causes serious short circuit
Failure.
Utility model content
The purpose of the utility model is to overcome the above-mentioned deficiencies in the presence of the prior art, provide a kind of surge protection electricity
Road and surge protective device.
In order to achieve the above-mentioned object of the invention, the utility model provides following technical scheme:
A kind of surge protection circuit, including the first piezoresistive wafer, the second piezoresistive wafer, third piezoresistive wafer, just
Temperature coefficient thermistor piece, gas-discharge tube and leading-out terminal, first piezoresistive wafer and the gas-discharge tube string
Connection, the posive temperature coefficient thermistor piece are connected with the third piezoresistive wafer, after described two series arms are in parallel again
It connects with second piezoresistive wafer, forms a single port combinational circuit, wherein first piezoresistive wafer and gas
The performance of discharge tube tolerance surge impact is above the performance of the second piezoresistive wafer tolerance surge impact;
At least one in two leading-out terminals of the single port combinational circuit be the thermally conductive end of low thermal resistance, described second
Piezoresistive wafer and the third piezoresistive wafer form thermal coupling, and the third piezoresistive wafer and the positive temperature coefficient
Thermosensitive resistor film forms thermal coupling, the thermally conductive end of low thermal resistance and second piezoresistive wafer, positive temperature coefficient heat
Wherein one or two in quick resistor disc is thermally coupled to each other simultaneously.In use, in the thermally conductive end connection overheat of the low thermal resistance
Disconnector, the Curie point of the posive temperature coefficient thermistor piece are higher than the operating temperature of the overheat disconnector.
The principle Analysis of the utility model is as follows:
It is to absorb surge arteries and veins by the series loop that the first piezoresistive wafer, gas-discharge tube, the second piezoresistive wafer form
The main channel of punching, when not having surge pulse, varistor is in high-impedance state, and discharge tube is in an off state, which is in
Open-circuit condition.When surge arrives, varistor is in low resistive state, and discharge tube is on state, and surge energy thus let out by circuit
It puts.At this point, the pressure drop on gas-discharge tube is very low negligible.It is pressure-sensitive that the voltage-limiting protection level of SPD is regarded as first
The residual voltage value of resistor disc and the sum of the residual voltage value of the second piezoresistive wafer.After surge disappears, piezoresistive wafer returns to high resistant shape
State, pincers have broken the afterflow of discharge tube, and discharge tube is made to return to off-state.In order to ensure the component deterioration in surge channel will be from
Second piezoresistive wafer starts, and in tolerance surge impact capacity selection, should follow the first piezoresistive wafer and gas-discharge tube
Tolerance be greater than the principle of the second piezoresistive wafer, significantly deteriorated with reaching when the second piezoresistive wafer, started to open
When dynamic Thermal protection circuit, the first piezoresistive wafer and the also substantially intact purpose of gas-discharge tube.
Another circuit is to be connected by the second piezoresistive wafer, third piezoresistive wafer with posive temperature coefficient thermistor piece
Made of Thermal protection branch, and overheat disconnector is connected to by thermally conductive end.When the intact no surge of element, due in height
Not on-state is hindered, the leakage current for flowing through Thermal protection branch is minimum (microampere order), and branch is protected not generate heat.Even if when surge is arrived
When, since the posive temperature coefficient thermistor piece being serially connected in branch still has tens Dao several hundred ohm resistance value at normal temperature, and
The series arm of first piezoresistive wafer and gas-discharge tube connected in parallel its dynamic electric resistor in the case where absorbing surge on state
Can be several ohm down to zero point, major part surge current absolutely passes through from this dynamic low-resistance branch, and positive temperature coefficient temperature-sensitive electricity
Resistance piece and the voltage at third piezoresistive wafer series arm both ends are also limited in the residual voltage value of the first piezoresistive wafer, flow through heat
The surge current of branch is protected at most namely to pacify times grade with this condition, the heat that thermistor generates in a short period of time
It is minimum and surge just disappears, protection branch can because generate heat it is faint due to be failure to actuate.
The Analysis of Failure Mechanism of the utility model is as follows:
When the second piezoresistive wafer significantly deteriorates, pressure sensitive voltage value declines to a great extent, the pressure sensitive voltage of the second piezoresistive wafer
After value is superimposed with the pressure sensitive voltage value of third piezoresistive wafer, when being still below 90% or less network operation voltage peak, heat is protected
The leakage current of shield branch enters milliampere area and starts after accelerating fever deterioration, by the second piezoresistive wafer and third pressure being coupled to
It generates heat caused by the leakage current of heat and increase that quick resistor disc generates, in the resistance value for promoting posive temperature coefficient thermistor piece
It rises, and finally reaches thermal balance above Curie point, leakage current strangulation compared with fractional value, so that the second piezoresistive wafer
It is elongated with the deterioration process of third piezoresistive wafer.Heat can be transmitted to overheat disconnector from thermally conductive end at leisure,
Temperature can achieve near Curie temperature, and the operating temperature for overheating disconnector is set below at Curie temperature, can be reliably
Disengaging movement, so that the SPD deteriorated be made to be detached from power network line.The technical program can make the SPD after most deterioration with this
The mode of kind safety exits power grid.
For those much special circumstances, i.e., when the second piezoresistive wafer deteriorates to a certain extent or has located
When accelerated deterioration area, its anti-impulse ability has declined to a great extent at this time, and stronger surge of energy can be
It directly punctures or close breakdown.When surge disappear after, due to resistance to surge impact capacity it is stronger and substantially intact than it first
Piezoresistive wafer still is able to the follow current of the disconnected discharge tube of pincers, and gas-discharge tube can still return to off-state, at this time power grid
Operating voltage still will be applied to Thermal protection branch both ends, it still can generate heat to Curie point and keep overheat disconnector dynamic
Make, overheat disconnector will action power dump, make damage SPD safely exit power grid.Generally all due to overheat disconnector
It is provided with positioning indicator or electricity, sound, light warning device, will soon be found, maintenance personal carries out more in which can be convenient
It changes, has achieved the purpose that safe handling.To substantially increase the safety and reliability of SPD, the electricity consumption connected on route is set
Standby crash rate also will significantly reduce.
It should be noted that the second piezoresistive wafer is not necessarily to identify oneself in thermal coupling in Thermal protection branch,
After choosing suitable component parameters, the thermal coupling branch that is shaped to by third piezoresistive wafer and posive temperature coefficient thermistor piece group
Heat caused by road is equally enough to make the fever of posive temperature coefficient thermistor piece to Curie point and keeps overheat disconnector dynamic
Make, also can achieve the goal of the invention of the utility model.And the thermally conductive end of low thermal resistance is connected with overheat disconnector, the low thermal resistance
Thermal coupling is realized in the one or both ends that thermally conductive end need to only be connected to Thermal protection branch, is not limited to be connected to a certain specific
On resistor disc.
Further, the posive temperature coefficient thermistor piece can replace with the resistance of linear feature, linear special
The electric current of the resistance of sign is substantially proportional to voltage, i.e., its characteristic equation is mainly linear homogeneous, and defers to Ohm's law.
The resistance of linear feature can also play the role of following in Thermal protection branch: first is that metering function, when described second pressure-sensitive
After resistor disc accelerated deterioration even puncture short, the resistance of linear feature can pacify the current limit in Thermal protection branch
Within total head, it not will cause the surge protection circuit short circuit and burn;Second is that heating functioin, the electric current within safety value persistently leads to
The resistance for crossing second piezoresistive wafer and linear feature, which will be such that they are warming up to, makes to overheat disconnector movement, equally may be used
To achieve the purpose that Thermal protection.To reach said effect, (second is pressure-sensitive in the most adverse case for the current value of Thermal protection branch
Resistor disc puncture short) it is advisable for tens milliamperes to several amperes, the resistance value of the resistance of corresponding linear feature is several kilo-ohms
Nurse is to tens ohm.
In the present invention, the resistance of linear feature both includes linear resistance, also allow containing it is some it is non-linear at
Divide (non-linear component is smaller, mainly still embodies Ohm's law feature), but power is required to want sufficiently large, pressure resistance is wanted
It is sufficiently high, at least to adhere to that failure cannot be damaged before overheating disconnector movement.
The third piezoresistive wafer for being serially connected in Thermal protection branch mainly plays two, first is that adjusting the starting of Thermal protection branch
Sensitivity;Second is that adjusting the ability that single port combinational circuit is resistant to accessed voltage ripple of power network.Third piezoresistive wafer
Pressure sensitive voltage value is selected lower, and Thermal protection branch starts more early, and the second piezoresistive wafer is not deteriorated to also close to when breakdown
Power grid is detached from regard to movement.But the pressure sensitive voltage value of third piezoresistive wafer can not be selected excessively high, once choosing value is higher than power grid
After the 90% of crest voltage, even if the second piezoresistive wafer has deteriorated puncture short, third piezoresistive wafer can also be maintained
Thermostabilization, does not accelerate deterioration failure, and Thermal protection branch is just passivated and fails.
Since the maximum continuous work voltage value in single port combinational circuit is continuous by the maximum of the second piezoresistive wafer
The sum of operating voltage value and the maximum continuous work voltage value of third piezoresistive wafer determine, and the second piezoresistive wafer be
On surge absorbing major loop, pressure sensitive voltage value (being proportional to maximum continuous work voltage value) should not select get Tai Gao, in order to avoid increase
Residual voltage value influences level of protection.Therefore, the pressure sensitive voltage value of third piezoresistive wafer can be selected into Gao Yidian, is accessed with tolerance
The erratic fluctuations of network operation voltage.
Due to the series connection Thermal protection branch roadlock of the posive temperature coefficient thermistor piece when surge is impacted and third piezoresistance piece
Anti- higher, both ends are protected by the residual voltage of the first piezoresistive wafer again, so hardly by surge damage, their tile is straight
Diameter can choose smaller, is typically chosen diameter 12mm or less and is sufficient.
Preferably, the pressure sensitive voltage value of first piezoresistive wafer is the 0.5 of accessed network operation voltage peak
To 1 times.It can guarantee in the case where the second piezoresistive wafer thorough puncture short, can also only be incited somebody to action by the first piezoresistive wafer
The follow current pincers of discharge tube is disconnected, and discharge tube is made to return to off-state, improves the safety of single port combinational circuit.When the first pressure
When the pressure sensitive voltage value of quick resistor disc is selected too low, it cannot be guaranteed that in the case reliably pincers break discharge tube follow current;
When selecting excessively high, the limitation voltage indexes of single port over-voltage protector can be improved, level of protection is influenced.
Preferably, the pressure sensitive voltage value of the third piezoresistive wafer is less than or equal to accessed network operation Voltage Peak
The 85% of value;The maximum continuous work voltage value of second piezoresistive wafer and the maximum of the third piezoresistive wafer are continuous
The sum of operating voltage value is greater than accessed network operation voltage value.
Preferably, the impact resistance current rating of first piezoresistive wafer and gas-discharge tube is above described second
The impact resistance current rating of piezoresistive wafer.
Preferably, the thermally conductive end of the low thermal resistance is thermally coupled to each other and can replace with the posive temperature coefficient thermistor piece
For the thermally conductive end of low thermal resistance is thermally coupled to each other with the third piezoresistive wafer.
The invention also discloses a kind of surge protection circuit, including the first piezoresistive wafer, the second piezoresistive wafer,
Third piezoresistive wafer, posive temperature coefficient thermistor piece, gas-discharge tube and leading-out terminal, first piezoresistive wafer with
The gas-discharge tube series connection, the posive temperature coefficient thermistor piece is connected with the third piezoresistive wafer, described two
It connects again with second piezoresistive wafer after series arm is in parallel, forms a single port combinational circuit, wherein described first
Piezoresistive wafer and the performance of gas-discharge tube tolerance surge impact are above the second piezoresistive wafer tolerance surge impact
Performance;
There is one in two leading-out terminals of the single port combinational circuit for the thermally conductive end of low thermal resistance, the third is pressure-sensitive
Resistor disc and the posive temperature coefficient thermistor piece form thermal coupling, the thermally conductive end of low thermal resistance and the pressure-sensitive electricity of the third
Resistance piece or the posive temperature coefficient thermistor piece are thermally coupled to each other.
The invention also discloses a kind of surge protective device, welded on an electrode surface of second piezoresistive wafer
The third piezoresistive wafer and the gas-discharge tube are connected in succession, on another electrode surface of the third piezoresistive wafer
It is connected with the posive temperature coefficient thermistor piece, another electricity of the posive temperature coefficient thermistor piece and gas-discharge tube
Two electrode surfaces of first piezoresistive wafer, second piezoresistive wafer and/or the positive temperature are connected separately on extremely
Degree coefficient resistance on piece is also welded with the thermally conductive end of low thermal resistance, to realize the thermal coupling of element.The connection of element is preferentially selected
It selects and is directly welded between electrode surface, as far as possible less with internal connecting lead wire or conducting bracket.
Preferably, the first piezoresistive wafer, second piezoresistive wafer, the third piezoresistive wafer, the positive temperature
Degree coefficient resistance piece, the gas-discharge tube are packaged as a whole, with insulating materials by remaining table in addition to two leading-out terminals
Wrap up in envelope in face.
Preferably, the thermally conductive end of low thermal resistance with thermally conductive function has foot using excellent materials of heating conductions such as copper
Enough big cross-sectional areas.And pyrotoxin (piezoresistive wafer or positive temperature coefficient temperature-sensitive are connected to using thermal couplings modes such as welding
On resistor disc), and distance of the thermally conductive end away from pyrotoxin will as far as possible it is short, to obtain minimum thermal resistance, guarantee has enough
Heat is transmitted to overheat disconnector.
Preferably, the first piezoresistive wafer electrode surface area of first piezoresistive wafer is greater than the described second pressure-sensitive electricity
Hinder the second piezoresistive wafer electrode surface area of piece.Measuring piezoresistive wafer tolerance surge impact capacity has multinomial technical indicator,
It is main to have: dash current Iimp, current waveform is 10/350 μ s;Maximum discharge current Imax, current waveform is 8/20 μ s;Energy
Tolerance, current waveform are 2ms square wave;Rush of current stability is exactly with 8/20 μ s waveform nominal discharge current In repeated impacts
The number etc. being resistant to.Under identical geometric dimension, by adjusting ceramic formula or technological parameter can optimize one of them or
Multiple parameters index, but want General Promotion or relatively difficult.But these technical indicators are all and varistor plate electrode
Area is directly proportional, therefore, as long as increasing the area of the first varistor plate electrode under the conditions of same process, so that it may ensure to be resistant to
Surge impact capacity is comprehensively more than the second piezoresistive wafer.
Preferably, the nominal diameter of first piezoresistive wafer is nominal straight at least more than second piezoresistive wafer
One sequence number of diameter.Since the diameter of flanking sequence number is than about 1.25 times, they are resistant to the parameter difference of surge impact capacity
About 1.5 times, as long as the second piezoresistive wafer is designed to match with application environment, then the first piezoresistive wafer belongs to
Redundancy Design, crash rate will be reduced than the second piezoresistive wafer in the order of magnitude, so that it may which guarantee makes the second piezoresistive wafer first
Deterioration.
Compared with prior art, the utility model has the beneficial effects that
The utility model is equipped with simultaneously to be composed in series by the first piezoresistive wafer, gas-discharge tube, the second piezoresistive wafer
Absorption surge pulse main channel, and by the second piezoresistive wafer, third piezoresistive wafer, posive temperature coefficient thermistor
The Thermal protection branch that piece is connected in series, and two branch circuit parallel connections.Under conventional failure conditions and special failure conditions, the mistake of SPD
Hot disconnector can action power dump so that SPD finally exits circuit with open circuit mode, relative to traditional short-circuit mode,
Greatly improve the safety of SPD, it is therefore prevented that short circuit breakdown when generate smolder, arcing, even catching fire pernicious thing
Therefore.Meanwhile positioning indicator or electricity, sound, light warning device that disconnector is equipped with are overheated, so that the SPD of damage is soon
It can be found, maintenance personal replaces in which can be convenient, and has achieved the purpose that safe handling, to substantially increase SPD's
Safety and reliability, the electrical equipment crash rate connected on route also will significantly reduce.
In addition, the third piezoresistive wafer for being serially connected in Thermal protection branch mainly plays two, first is that adjusting Thermal protection branch
The sensitivity of road starting;Second is that adjusting the ability that single port combinational circuit is resistant to accessed voltage ripple of power network.
Detailed description of the invention:
Fig. 1 is the schematic illustration of improvement plan one described in background technique.
It is marked in Fig. 1: 1- based varistor chip, 2- scale copper electrode, 3- leading-out terminal, 4- elastic sheet metal, 5-
Low-melting alloy.
Fig. 2 is the schematic illustration of improvement plan two described in background technique.
Mark in Fig. 2: 11- piezoresistive wafer, 12- thermosensitive resistor film, 13- gas-discharge tube, 14- exit, 15- are drawn
End, 16- encapsulated layer.
Fig. 3 is a kind of schematic diagram of surge protection circuit described in the utility model embodiment 1.
Fig. 4 is a kind of schematic diagram of surge protection circuit described in the utility model embodiment 2.
Fig. 5 is a kind of schematic diagram of surge protection circuit described in the utility model embodiment 3.
Fig. 6 is a kind of schematic diagram of surge protection circuit described in the utility model embodiment 3.
Fig. 7 is a kind of schematic diagram of surge protection circuit described in the utility model embodiment 4.
Fig. 8 is a kind of schematic diagram of surge protection circuit described in the utility model embodiment 4.
Fig. 9 is a kind of part drawing of surge protective device described in the utility model embodiment 5.
Figure 10 is a kind of assembling figure of surge protective device described in the utility model embodiment 5.
It is marked in Fig. 3-Figure 10: the first piezoresistive wafer of 1-, 11- the first piezoresistive wafer electrode surface, the pressure-sensitive electricity of 2- second
Resistance piece, 21- the second piezoresistive wafer electrode surface, 3- third piezoresistive wafer, 4- posive temperature coefficient thermistor piece, 5- gas are put
Fulgurite, 6- leading-out terminal, 7- internal connection line.
Specific embodiment
The utility model is described in further detail below with reference to test example and specific embodiment.But it should not be by this
The range for being interpreted as the above-mentioned theme of the utility model is only limitted to embodiment below, all to be realized based on the content of the present invention
Technology belongs to the scope of the utility model.
Embodiment 1
As shown in figure 3, a kind of surge protection circuit, including the first piezoresistive wafer 1, the second piezoresistive wafer 2, third
Piezoresistive wafer 3, posive temperature coefficient thermistor piece 4, gas-discharge tube 5 and leading-out terminal 6, first piezoresistive wafer 1
It connects with the gas-discharge tube 5, the posive temperature coefficient thermistor piece 4 is connected with the third piezoresistive wafer 3, institute
It connects again with second piezoresistive wafer 2 after stating two series arms parallel connections, forms a single port combinational circuit, wherein
It is resistance to that the performance that first piezoresistive wafer 1 and gas-discharge tube 5 are resistant to surge impact is above second piezoresistive wafer 2
The performance impacted by surge.
Two leading-out terminals 6 of the single port combinational circuit are the thermally conductive end of low thermal resistance, second varistor
Piece 2 and the third piezoresistive wafer 3 form thermal coupling, and the third piezoresistive wafer 3 and the positive temperature coefficient temperature-sensitive
Resistor disc 4 forms thermal coupling, and the thermally conductive end of low thermal resistance is thermally coupled to each other with second piezoresistive wafer 2, meanwhile, it is described
The thermally conductive end of low thermal resistance is thermally coupled to each other with the posive temperature coefficient thermistor piece 4.
The pressure sensitive voltage value of first piezoresistive wafer 1 is 0.5 to 1 times of accessed network operation voltage peak;
The pressure sensitive voltage value of the third piezoresistive wafer 3 is less than or equal to the 85% of accessed network operation voltage peak;It is described
The maximum continuous work voltage value of second piezoresistive wafer 2 and the maximum continuous work voltage value of the third piezoresistive wafer 3
The sum of be greater than accessed network operation voltage value.
Embodiment 2
As shown in figure 4, the present embodiment the difference from embodiment 1 is that, two exits of the single port combinational circuit
Sub 5 only ones are the thermally conductive end of low thermal resistance, and second piezoresistive wafer 2 forms thermal coupling with the third piezoresistive wafer 3,
And the third piezoresistive wafer 3 forms thermal coupling, the thermally conductive end of low thermal resistance with the posive temperature coefficient thermistor piece 4
It is thermally coupled to each other with second piezoresistive wafer 2.
Embodiment 3
The present embodiment the difference from embodiment 1 is that, two 5 only ones of leading-out terminal of the single port combinational circuit
For the thermally conductive end of low thermal resistance, second piezoresistive wafer 2 and the third piezoresistive wafer 3 form thermal coupling, and described the
Three piezoresistive wafers 3 form thermal coupling with the posive temperature coefficient thermistor piece 4.The thermally conductive end of low thermal resistance and it is described just
Temperature coefficient thermistor piece 4 be thermally coupled to each other (as shown in Fig. 5) or the thermally conductive end of the low thermal resistance and the third it is pressure-sensitive
Resistor disc 3 is thermally coupled to each other (as shown in Figure 6).
Embodiment 4
The present embodiment the difference from embodiment 1 is that, two 5 only ones of leading-out terminal of the single port combinational circuit
For the thermally conductive end of low thermal resistance, the third piezoresistive wafer 3 forms thermal coupling with the posive temperature coefficient thermistor piece 4.Institute
It states the thermally conductive end of low thermal resistance and the posive temperature coefficient thermistor piece 4 is thermally coupled to each other (as shown in Figure 7) or the low thermal resistance
Thermally conductive end and the third piezoresistive wafer 3 are thermally coupled to each other (as shown in Figure 8).At this point, second piezoresistive wafer 2 is not
Participate in thermal coupling.
Embodiment 5
As shown in Fig. 9-Figure 10, a kind of surge protective device, second varistor of second piezoresistive wafer 2
The third piezoresistive wafer 3 and the gas-discharge tube 5, the third piezoresistive wafer are welded and connected on plate electrode face 21
The posive temperature coefficient thermistor piece 4 is connected on 3 another electrode surface, the posive temperature coefficient thermistor piece 4
Another electrode is connected with a first piezoresistive wafer electrode surface of first piezoresistive wafer 1 by internal connection line 7
11, another electrode welding of the gas-discharge tube 5 connects another first varistor of first piezoresistive wafer 1
Plate electrode face 11.Exit is also welded on second piezoresistive wafer 2 and/or the posive temperature coefficient thermistor piece 4
Son 6, wherein at least one are the thermally conductive end of low thermal resistance.First piezoresistive wafer 1, second piezoresistive wafer 2, the third
Piezoresistive wafer 3, the posive temperature coefficient thermistor piece 4, the gas-discharge tube 5 are packaged as a whole.
Specifically, the pressure-sensitive tile (40K241x2) of square of the first piezoresistive wafer 1 selection two panels nominal diameter 40mm
For equivalent substitution to reduce mounting area, which is that the industry is the routine side for reducing mounting area and using after parallel connection
Formula can also directly adopt the pressure-sensitive tile of rectangle certainly, and pressure sensitive voltage is 240 volts, and maximum discharge current Imax is 80KA;The
Two piezoresistive wafers 2 select the pressure-sensitive tile 40K331 of square of nominal diameter 40mm, and pressure sensitive voltage is 330 volts, maximum electric discharge
Electric current Imax is 40KA;Third piezoresistive wafer 3 select the pressure-sensitive tile 10K221 of circle of nominal diameter 10mm, pressure sensitive voltage for
220V;The maximum discharge current Imax of gas-discharge tube 5 be 50KA, 450 volts of pulse breakdown voltage;Posive temperature coefficient thermistor
4 160 DEG C of Curie point of selections, 150 ohm of room temperature resistance value, the disk of diameter 10mm.Reference selection is suitble in 220 couchers frequency
It works in power grid, the operating temperature of overheat disconnector matched with its is 120 DEG C.
Package unit is connected on 220 coucher frequency routes, and applies the surge repeated impacts of In=20KA, the 98th punching
Disconnector movement is overheated after hitting, and is cooled to and is tested the pressure sensitive voltage value of the second piezoresistive wafer 2 after room temperature to have deteriorated be 0 volt,
To puncture short, and the first piezoresistive wafer 1 is still 238 volts, is remained unchanged substantially.
Above embodiments are only to illustrate the utility model and not limit technical solution described in the utility model, to the greatest extent
Pipe this specification has been carried out detailed description to the utility model referring to above-mentioned each embodiment, but the utility model not office
It is limited to above-mentioned specific embodiment, therefore any pair of the utility model is modified or equivalent replacement;And all do not depart from it is practical
The technical solution and its improvement of novel spirit and scope, should all cover in the scope of the claims of the utility model.
Claims (10)
1. a kind of surge protection circuit, including the first piezoresistive wafer (1), the second piezoresistive wafer (2), third piezoresistive wafer
(3), posive temperature coefficient thermistor piece (4), gas-discharge tube (5) and leading-out terminal (6), which is characterized in that first pressure
Quick resistor disc (1) is connected with the gas-discharge tube (5), and the posive temperature coefficient thermistor piece (4) and the third are pressure-sensitive
Resistor disc (3) series connection connects again with second piezoresistive wafer (2) after described two series arms are in parallel, forms a list
Port combination circuit, wherein the performance of first piezoresistive wafer (1) and gas-discharge tube (5) tolerance surge impact is high
In the performance of second piezoresistive wafer (2) tolerance surge impact;
At least one in two leading-out terminals (6) of the single port combinational circuit be the thermally conductive end of low thermal resistance, described second
Piezoresistive wafer (2) and the third piezoresistive wafer (3) form thermal coupling, and the third piezoresistive wafer (3) with it is described
Posive temperature coefficient thermistor piece (4) formation thermal coupling, the thermally conductive end of low thermal resistance and second piezoresistive wafer (2),
Wherein one or two in the posive temperature coefficient thermistor piece (4) is thermally coupled to each other simultaneously.
2. a kind of surge protection circuit according to claim 1, which is characterized in that first piezoresistive wafer (1)
Pressure sensitive voltage value is 0.5 to 1 times of accessed network operation voltage peak.
3. a kind of surge protection circuit according to claim 2, which is characterized in that when accessing 220V power grid, described
The pressure sensitive voltage value of one piezoresistive wafer (1) is 156V-311V;When accessing 110V power grid, first piezoresistive wafer (1)
Pressure sensitive voltage value be 78V-156V;When accessing 380V power grid, the pressure sensitive voltage value of first piezoresistive wafer (1) is
269V-537V。
4. a kind of surge protection circuit according to claim 1, which is characterized in that the third piezoresistive wafer (3)
Pressure sensitive voltage value is less than or equal to the 85% of accessed network operation voltage peak;Second piezoresistive wafer (2) is most
The sum of maximum continuous work voltage value of big continuous operating voltage value and the third piezoresistive wafer (3) is greater than accessed electricity
Net operating voltage value.
5. a kind of surge protection circuit according to claim 4, which is characterized in that when accessing 220V power grid, described
The pressure sensitive voltage value of three piezoresistive wafers (3) is less than or equal to 264V;When accessing 110V power grid, the third piezoresistive wafer
(3) pressure sensitive voltage value is less than or equal to 132V;When accessing 380V power grid, the pressure-sensitive electricity of the third piezoresistive wafer (3)
Pressure value is less than or equal to 457V.
6. a kind of surge protection circuit according to claim 1, which is characterized in that the thermally conductive end of low thermal resistance with it is described
Posive temperature coefficient thermistor piece (4) is thermally coupled to each other and can replace with, and the thermally conductive end of low thermal resistance and the third are pressure-sensitive
Resistor disc (3) is thermally coupled to each other.
7. a kind of surge protection circuit, including the first piezoresistive wafer (1), the second piezoresistive wafer (2), third piezoresistive wafer
(3), posive temperature coefficient thermistor piece (4), gas-discharge tube (5) and leading-out terminal (6), which is characterized in that first pressure
Quick resistor disc (1) is connected with the gas-discharge tube (5), and the posive temperature coefficient thermistor piece (4) and the third are pressure-sensitive
Resistor disc (3) series connection connects again with second piezoresistive wafer (2) after described two series arms are in parallel, forms a list
Port combination circuit, wherein the performance of first piezoresistive wafer (1) and gas-discharge tube (5) tolerance surge impact is high
In the performance of second piezoresistive wafer (2) tolerance surge impact;
There is one in two leading-out terminals (6) of the single port combinational circuit for the thermally conductive end of low thermal resistance, the third is pressure-sensitive
Resistor disc (3) and the posive temperature coefficient thermistor piece (4) form thermal coupling, the thermally conductive end of low thermal resistance and the third
Piezoresistive wafer (3) or the posive temperature coefficient thermistor piece (4) are thermally coupled to each other.
8. -7 any a kind of surge protection circuit according to claim 1, which is characterized in that the positive temperature coefficient temperature-sensitive
Resistor disc (4) can replace with the resistance of linear feature.
9. a kind of surge protective device, which is characterized in that including a kind of surge protection electricity as claimed in claim 1
Road is welded and connected with the third piezoresistive wafer (3) and the gas on one electrode surface of second piezoresistive wafer (2)
Body discharge tube (5) is connected with the posive temperature coefficient thermistor on another electrode surface of the third piezoresistive wafer (3)
It is connected separately on another electrode of piece (4), the posive temperature coefficient thermistor piece (4) and gas-discharge tube (5) described
First electrode surface of piezoresistive wafer (1) two, second piezoresistive wafer (2) and/or the posive temperature coefficient thermistor
The thermally conductive end of low thermal resistance is also welded on piece (4).
10. a kind of surge protective device according to claim 9, which is characterized in that first piezoresistive wafer (1)
First piezoresistive wafer electrode surface (11) area is greater than the second piezoresistive wafer electrode surface of second piezoresistive wafer (2)
(21) area;And/or the nominal diameter of first piezoresistive wafer (1) is at least more than second piezoresistive wafer (2)
One sequence number of nominal diameter.
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Cited By (1)
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CN109066641A (en) * | 2018-07-12 | 2018-12-21 | 成都铁达电子股份有限公司 | A kind of surge protection circuit and surge protective device |
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CN109066641A (en) * | 2018-07-12 | 2018-12-21 | 成都铁达电子股份有限公司 | A kind of surge protection circuit and surge protective device |
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