CN108879642A - The surge protection circuit and surge protective device of high safety - Google Patents
The surge protection circuit and surge protective device of high safety Download PDFInfo
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- CN108879642A CN108879642A CN201811040609.6A CN201811040609A CN108879642A CN 108879642 A CN108879642 A CN 108879642A CN 201811040609 A CN201811040609 A CN 201811040609A CN 108879642 A CN108879642 A CN 108879642A
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- piezoresistive wafer
- piezoresistive
- wafer
- temperature coefficient
- surge
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/042—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage comprising means to limit the absorbed power or indicate damaged over-voltage protection device
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/20—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess voltage
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/008—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for protective arrangements according to this subclass
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/044—Physical layout, materials not provided for elsewhere
Abstract
The invention discloses a kind of surge protection circuit of high safety and surge protective devices; protecting circuit includes the first piezoresistive wafer, the second piezoresistive wafer, third piezoresistive wafer, posive temperature coefficient thermistor piece and leading-out terminal; posive temperature coefficient thermistor piece is in parallel with the first piezoresistive wafer after connecting with third piezoresistive wafer; the series-parallel branch is connected with the second piezoresistive wafer again; form a single port combinational circuit; wherein, the performance of the first piezoresistive wafer tolerance surge impact is higher than the performance of the second piezoresistive wafer tolerance surge impact；At least one in two leading-out terminals of single port combinational circuit is the thermally conductive end of low thermal resistance, second piezoresistive wafer and third piezoresistive wafer form thermal coupling, and third piezoresistive wafer and posive temperature coefficient thermistor piece form thermal coupling, the thermally conductive end of low thermal resistance is thermally coupled to each other simultaneously with wherein one or two in the second piezoresistive wafer, posive temperature coefficient thermistor piece.
Description
Technical field
The present invention relates to field of power supplies, in particular to the surge protection circuit and surge protective device of a kind of high safety.
Background technique
A kind of low-voltage electrical apparatus of the Surge Protector (abbreviation SPD) as standard, is widely used in low pressure electric line,
The surge as caused by thunder and lightning etc. occurred in route effectively can be absorbed and be inhibited, to improvement grid power transmission quality, be protected
Card electrical appliance has safely apparent effect.
The core component of SPD is Surge suppression element, and the most commonly used is based varistor chips.Due to electric line
Transmission range is longer, but be easy to be exposed to it is outdoor, compared to indoor electric appliance equipment be easier by high-energy surge pulse, in SPD
Phase projected life in, based varistor chip be easier by be more than rated specification high-energy surge repeat impact,
Cause the deterioration failure of varistor.Since varistor is short circuit failure mode, once breakdown failure, will cause supply lines
Road short trouble, breakdown point will appear burst, smolder, arcing, it is serious when in addition will cause catching fire.
Improvement plan is first is that most common method, concrete principle figure are shown in attached drawing 1, at two of based varistor chip 1
It on end electrode, is respectively welded and connects a piece of conductive and all excellent heating conduction scale copper electrode 2, scale copper electrode 2 is prefabricated
There is leading-out terminal 3, scale copper electrode 2 also forms thermal coupling with based varistor chip 1 while playing the role of conductive electrode
It closes, the heat that based varistor chip 1 generates can be transmitted on leading-out terminal 3.Wherein with low on a leading-out terminal 3
Melting alloy 5 welds a piece of elastic sheet metal 4 and forms overheat disconnector.It is flowed into when based varistor chip 1 is deteriorated to electric leakage
When entering milliampere grade, accelerated deterioration area is initially entered, leakage current can make the fever of based varistor chip 1 promote leakage current further
Increase, and accelerate the fever of based varistor chip 1, will finally make 1 thermal breakdown of based varistor chip.When heat reaches
When 5 fusing-off temperature of low-melting alloy, disconnector action power dump is overheated, makes based varistor chip 1 before puncture short
Power grid is exited, has achieved the purpose that protection.The program can be by the failure mode of most based varistor chip 1 from pernicious
Short-circuit mode is converted to the open circuit mode for influencing very little, greatly improves the safety of SPD.
But still there is also some defects for the program, since the movement of overheat disconnector needs to be delayed by several seconds the time, and
1 leakage current of based varistor chip enters milliampere grade and starts accelerated deterioration adstante febre, and the defect inside porcelain body is very serious
, there is the defect of partial chip seriously to arrive very short to the time of puncture short from starting to generate heat, heat also has little time to be transmitted to
Hot disconnector melts low-melting alloy 5, and short circuit accident just has occurred.Another much situation is exactly when pressure-sensitive electricity
Resistance ceramic chip 1 is deteriorated to when closing on accelerated deterioration area, and at this moment the leakage current of based varistor chip 1 is also less than milliampere grade,
It can also maintain thermostabilization, additionally it is possible to work is maintained under the operating voltage of power grid, but its pressure sensitive voltage value at this time has compared
Initial value when just starting to come into operation has apparent sharp fall, the anti-surge punching of based varistor chip 1 at this moment
The ability hit is very fragile, an energy not counting it can be punctured or close to breakdown by too big surge, at this time it
Puncture short speed is also that too fastly, overheat disconnector has little time response action and do not have protective effect.
For improvement plan second is that application No. is 201310268111.6 Chinese invention patent, schematic diagram is shown in attached drawing 2, will just
It connects again with piezoresistive wafer 11 after temperature coefficient ceramics thermosensitive resistor film 12 and 13 parallel connection of gas-discharge tube, and thermistor
Piece 12 and piezoresistive wafer 11 are welded together to form thermal coupling, and exit 14 and exit 15 are connected in parallel on by protection power source route
On, using epoxy resin enclosed, solidification after welding lead, form encapsulated layer 16.Its main feature is that when piezoresistive wafer 11 is deteriorated to
Leakage current, which significantly increases, to be started to generate heat into after accelerated deterioration area, and heating temperature is coupled to ceramic positive temperature coefficient thermistor piece
12, resistance value rises after keeping it heated, reduces the leakage current for flowing into piezoresistive wafer 11, plays the work for extending the deterioration time
With, and after the heating temperature of piezoresistive wafer 11 reaches the Curie point of thermosensitive resistor film 12, positive temperature coefficient ceramic heat
Quick resistor disc 12 becomes high-impedance state, limits the increase of leakage current, and piezoresistive wafer 11 is forced to reach near Curie point
To thermal balance, piezoresistive wafer 11 can maintain work under network operation voltage in spite of illness.
But the program still has some serious defects, is firstly because ceramic positive temperature coefficient thermistor piece 12
Metering function, piezoresistive wafer 11 deteriorates severe again, and heating temperature also only maintains the curie point temperature of thermosensitive resistor film 12
Near degree, work is exited without departing from power grid, until the pressure sensitive voltage value deterioration of piezoresistive wafer 12 is reduced to network operation electricity
When the about half of voltage crest value, after concatenated discharge tube is connected for another surge impact, too low pressure sensitive voltage value pincers
The power network current constantly followed causes gas-discharge tube 13 not return to off-state, will protect 12 short circuit of thermosensitive resistor film
Protection circuit failure, at this time piezoresistive wafer 11 will puncture short immediately, cause serious short trouble.Theoretically, if do not had
There are other safeguard procedures, most of varistor can all fail in this way.Another failure procedure and scheme one
Situation is similar, i.e., when piezoresistive wafer 11 deteriorates to a certain extent, even if having not been entered into accelerated deterioration area, but because of its internal junction
Structure has been seriously damaged, and the ability sharp fall of tolerance surge impact, a surge can be hit at this time
It wears or close to breakdown, and gas-discharge tube 13 is also on state at this time, breakdown or same close to the piezoresistive wafer 11 of breakdown
Sample also loses the ability of pincers power-off net follow current, causes thermosensitive resistor film 12 to protect circuit malfunction, causes serious short circuit
Failure.
Summary of the invention
It is an object of the invention to overcome the above-mentioned deficiency in the presence of the prior art, the surge for providing a kind of high safety is protected
Protection circuit and surge protective device.
In order to achieve the above-mentioned object of the invention, the present invention provides following technical schemes：
A kind of surge protection circuit of high safety, including the first piezoresistive wafer, the second piezoresistive wafer, the pressure-sensitive electricity of third
Hinder piece, posive temperature coefficient thermistor piece and leading-out terminal, the posive temperature coefficient thermistor piece and the pressure-sensitive electricity of the third
In parallel with first piezoresistive wafer after resistance piece series connection, which connects with second piezoresistive wafer again, shape
At a single port combinational circuit, wherein the performance of the first piezoresistive wafer tolerance surge impact is higher than second pressure
The performance of quick resistor disc tolerance surge impact；
At least one in two leading-out terminals of the single port combinational circuit be the thermally conductive end of low thermal resistance, described second
Piezoresistive wafer and the third piezoresistive wafer form thermal coupling, and the third piezoresistive wafer and the positive temperature coefficient
Thermosensitive resistor film forms thermal coupling, the thermally conductive end of low thermal resistance and second piezoresistive wafer, positive temperature coefficient heat
Wherein one or two in quick resistor disc is thermally coupled to each other simultaneously.In use, in the thermally conductive end connection overheat of the low thermal resistance
Disconnector, the Curie point of the posive temperature coefficient thermistor piece are higher than the operating temperature of the overheat disconnector.
The working principle of the invention is analyzed as follows：
It is the main channel for absorbing surge pulse by the series loop that the first piezoresistive wafer, the second piezoresistive wafer form,
When not having surge pulse, varistor is in high-impedance state, and when surge arrives, varistor is in low resistive state, surge energy
Amount thus release by circuit.At this point, the voltage-limiting protection level of SPD is regarded as the residual voltage value of the first piezoresistive wafer and second pressure-sensitive
The sum of residual voltage value of resistor disc.After surge disappears, piezoresistive wafer returns to high-impedance state.In order to ensure the member in surge channel
Device degradation in tolerance surge impact capacity selection, will should follow the first piezoresistive wafer since the second piezoresistive wafer
Tolerance be greater than the principle of the second piezoresistive wafer, significantly deteriorated with reaching when the second piezoresistive wafer, started to open
When dynamic Thermal protection circuit, the also substantially intact purpose of the first piezoresistive wafer.
Another circuit is to be connected by the second piezoresistive wafer, third piezoresistive wafer with posive temperature coefficient thermistor piece
Made of Thermal protection branch, and overheat disconnector is connected to by thermally conductive end.When the intact no surge of element, due in height
Not on-state is hindered, the leakage current for flowing through Thermal protection branch is minimum (microampere order), and branch is protected not generate heat.Even if when surge is arrived
When, since the posive temperature coefficient thermistor piece being serially connected in branch still has tens Dao several hundred ohm resistance value at normal temperature, and
Its dynamic electric resistor can be several ohm down to zero point in the case where absorbing surge on state for first piezoresistive wafer connected in parallel, exhausted big portion
Part surge current passes through from the first piezoresistive wafer, and posive temperature coefficient thermistor piece and third piezoresistive wafer series connection branch
The voltage at road both ends is also limited in the residual voltage value of the first piezoresistive wafer, flows through the surge current of Thermal protection branch in this condition
Lower at most namely to pacify times grade, the heat that thermistor generates in a short period of time is minimum and surge just disappears, protection branch
Road can be failure to actuate because fever is faint.
Analysis of Failure Mechanism of the invention is as follows：
When the second piezoresistive wafer significantly deteriorates, pressure sensitive voltage value declines to a great extent, the pressure sensitive voltage of the second piezoresistive wafer
After value is superimposed with the pressure sensitive voltage value of third piezoresistive wafer, when being still below 90% or less network operation voltage peak, heat is protected
The leakage current of shield branch enters milliampere area and starts after accelerating fever deterioration, by the second piezoresistive wafer and third pressure being coupled to
It generates heat caused by the leakage current of heat and increase that quick resistor disc generates, in the resistance value for promoting posive temperature coefficient thermistor piece
It rises, and finally reaches thermal balance above Curie point, leakage current strangulation compared with fractional value, so that the second piezoresistive wafer
It is elongated with the deterioration process of third piezoresistive wafer.Heat can be transmitted to overheat disconnector from thermally conductive end at leisure,
Temperature can achieve near Curie temperature, and the operating temperature for overheating disconnector is set below at Curie temperature, can be reliably
Disengaging movement, so that the SPD deteriorated be made to be detached from power network line.The technical program can make the SPD after most deterioration with this
The mode of kind safety exits power grid.
For those much special circumstances, i.e., when the second piezoresistive wafer deteriorates to a certain extent or has located
When accelerated deterioration area, its anti-impulse ability has declined to a great extent at this time, and stronger surge of energy can be
It directly punctures or close breakdown.When surge disappear after, due to resistance to surge impact capacity it is stronger and substantially intact than it first
Piezoresistive wafer still is able to maintain high-impedance state, and thermostabilization is maintained in power grid, significant degradation phenomena does not occur, electric at this time
Net operating voltage still will be applied to Thermal protection branch both ends, it still can generate heat to Curie point and keep overheat disconnector dynamic
Make, overheat disconnector will action power dump, make damage SPD safely exit power grid.Generally all due to overheat disconnector
It is provided with positioning indicator or electricity, sound, light warning device, will soon be found, maintenance personal carries out more in which can be convenient
It changes, has achieved the purpose that safe handling.To substantially increase the safety and reliability of SPD, the electricity consumption connected on route is set
Standby crash rate also will significantly reduce.
It should be noted that the second piezoresistive wafer is not necessarily to identify oneself in thermal coupling in Thermal protection branch,
After choosing suitable component parameters, the thermal coupling branch that is shaped to by third piezoresistive wafer and posive temperature coefficient thermistor piece group
Heat caused by road is equally enough to make the fever of posive temperature coefficient thermistor piece to Curie point and keeps overheat disconnector dynamic
Make, also can achieve goal of the invention of the invention.And the thermally conductive end of low thermal resistance is connected with overheat disconnector, the low thermal resistance is thermally conductive
Thermal coupling is realized in the one or both ends that end need to only be connected to Thermal protection branch, is not limited to be connected to a certain specific resistance
On piece.
Further, the posive temperature coefficient thermistor piece could alternatively be the resistance of linear feature, linear special
The electric current of the resistance of sign is substantially proportional to voltage, i.e., its characteristic equation is mainly linear homogeneous, and defers to Ohm's law.
The resistance of linear feature can also play the role of following in Thermal protection branch：First is that metering function, when described second pressure-sensitive
After resistor disc accelerated deterioration even puncture short, the resistance of linear feature can pacify the current limit in Thermal protection branch
Within total head, it not will cause the surge protection circuit short circuit and burn；Second is that heating functioin, the electric current within safety value persistently leads to
The resistance for crossing second piezoresistive wafer and linear feature, which will be such that they are warming up to, makes to overheat disconnector movement, equally may be used
To achieve the purpose that Thermal protection.To reach said effect, (second is pressure-sensitive in the most adverse case for the current value of Thermal protection branch
Resistor disc puncture short) it is advisable for tens milliamperes to several amperes, the resistance value of the resistance of corresponding linear feature is several kilo-ohms
Nurse is to tens ohm.
In the present invention, the resistance of linear feature both includes linear resistance, and also allowing (should containing some non-linear components
Non-linear component is smaller, mainly still embodies Ohm's law feature), but power is required to want sufficiently large, pressure resistance is enough
Height will at least adhere to that failure cannot be damaged before overheating disconnector movement.
The third piezoresistive wafer for being serially connected in Thermal protection branch mainly plays two, first is that adjusting the starting of Thermal protection branch
Sensitivity；Second is that adjusting the ability that single port combinational circuit is resistant to accessed voltage ripple of power network.Third piezoresistive wafer
Pressure sensitive voltage value is selected lower, and Thermal protection branch starts more early, and the second piezoresistive wafer is not deteriorated to also close to when breakdown
Power grid is detached from regard to movement.But the pressure sensitive voltage value of third piezoresistive wafer can not be selected excessively high, once choosing value is higher than power grid
After the 90% of crest voltage, even if the second piezoresistive wafer has deteriorated puncture short, third piezoresistive wafer can also be maintained
Thermostabilization, does not accelerate deterioration failure, and Thermal protection branch is just passivated and fails.
Since the maximum continuous work voltage value in single port combinational circuit is continuous by the maximum of the second piezoresistive wafer
The sum of operating voltage value and the maximum continuous work voltage value of third piezoresistive wafer determine, and the second piezoresistive wafer be
On surge absorbing major loop, pressure sensitive voltage value (being proportional to maximum continuous work voltage value) should not select get Tai Gao, in order to avoid increase
Residual voltage value influences level of protection.Therefore, the pressure sensitive voltage value of third piezoresistive wafer can be selected into height a bit, is accessed with tolerance
The erratic fluctuations of network operation voltage.
Due to the series connection Thermal protection branch roadlock of the posive temperature coefficient thermistor piece when surge is impacted and third piezoresistance piece
Anti- higher, both ends are protected by the residual voltage of the first piezoresistive wafer again, so hardly by surge damage, their tile is straight
Diameter can choose smaller, is typically chosen diameter 12mm or less and is sufficient.
Preferably, the pressure sensitive voltage value of first piezoresistive wafer is the 0.9 of accessed network operation voltage peak
To 1.1 times.It can guarantee in the case where the second piezoresistive wafer thorough puncture short, after surge disappearance, the first pressure-sensitive electricity
Resistance piece can also maintain high-impedance state, and thermostabilization is maintained in power grid, does not occur significantly to deteriorate, and be the movement of Thermal protection branch
The sufficient response time is provided, the safety of single port combinational circuit is improved.When the pressure sensitive voltage value of the first piezoresistive wafer is selected
When obtaining too low, it cannot be guaranteed that securely maintaining thermostabilization in the case, when selecting excessively high, single port overvoltage protector can be improved
The limitation voltage indexes of part, influence level of protection.
Preferably, the pressure sensitive voltage value of the third piezoresistive wafer is less than or equal to accessed network operation Voltage Peak
The 85% of value；The maximum continuous work voltage value of second piezoresistive wafer and the maximum of the third piezoresistive wafer are continuous
The sum of operating voltage value is greater than accessed network operation voltage value.
Preferably, the impact resistance current rating of first piezoresistive wafer is higher than the resistance to of second piezoresistive wafer
Dash current rated value.
Preferably, the thermally conductive end of the low thermal resistance and the posive temperature coefficient thermistor piece are thermally coupled to each other alternatively
For the thermally conductive end of low thermal resistance is thermally coupled to each other with the third piezoresistive wafer.
The invention also discloses a kind of surge protection circuits of high safety, including the first piezoresistive wafer, the second pressure-sensitive electricity
Hinder piece, third piezoresistive wafer, posive temperature coefficient thermistor piece and leading-out terminal, the posive temperature coefficient thermistor piece with
It is in parallel with the first piezoresistive wafer after third piezoresistive wafer series connection, the series-parallel branch again with second varistor
Piece series connection, forms a single port combinational circuit, wherein the performance of the first piezoresistive wafer tolerance surge impact is higher than institute
State the performance of the second piezoresistive wafer tolerance surge impact；
There is one in two leading-out terminals of the single port combinational circuit for the thermally conductive end of low thermal resistance, the third is pressure-sensitive
Resistor disc and the posive temperature coefficient thermistor piece form thermal coupling, the thermally conductive end of low thermal resistance and the positive temperature coefficient
Thermosensitive resistor film or the third piezoresistive wafer are thermally coupled to each other.
The invention also discloses a kind of surge protective device of high safety, an electrode surface of second piezoresistive wafer
On be connected with an electrode of the third piezoresistive wafer and first piezoresistive wafer, the third piezoresistive wafer
Be connected with the posive temperature coefficient thermistor piece on another electrode surface, the posive temperature coefficient thermistor piece another
Another electrode of first piezoresistive wafer, second piezoresistive wafer and/or the positive temperature are connected on electrode
Coefficient resistance on piece is also welded with the thermally conductive end of low thermal resistance, to realize the thermal coupling of element.The connection of element preferentially selects
It is directly welded between electrode surface, as far as possible less with internal connecting lead wire or conducting bracket.
Preferably, first piezoresistive wafer, second piezoresistive wafer, the third piezoresistive wafer, described
Posive temperature coefficient thermistor piece is packaged as a whole, and the remaining surface in addition to two leading-out terminals is wrapped up in envelope with insulating materials.
Preferably, the thermally conductive end of low thermal resistance with thermally conductive function has foot using excellent materials of heating conductions such as copper
Enough big cross-sectional areas.And pyrotoxin (piezoresistive wafer or positive temperature coefficient temperature-sensitive are connected to using thermal couplings modes such as welding
On resistor disc), and distance of the thermally conductive end away from pyrotoxin will as far as possible it is short, to obtain minimum thermal resistance, guarantee has enough
Heat is transmitted to overheat disconnector.
Preferably, the first piezoresistive wafer electrode surface area of first piezoresistive wafer is greater than the described second pressure-sensitive electricity
Hinder the second piezoresistive wafer electrode surface area of piece.Measuring piezoresistive wafer tolerance surge impact capacity has multinomial technical indicator,
It is main to have：Dash current Iimp, current waveform is 10/350 μ s；Maximum discharge current Imax, current waveform is 8/20 μ s；Energy
Tolerance, current waveform are 2ms square wave；Rush of current stability is exactly with 8/20 μ s waveform nominal discharge current In repeated impacts
The number etc. being resistant to.Under identical geometric dimension, by adjusting ceramic formula or technological parameter can optimize one of them or
Multiple parameters index, but want General Promotion or relatively difficult.But these technical indicators are all and varistor plate electrode
Area is directly proportional, therefore, as long as increasing the area of the first varistor plate electrode under the conditions of same process, so that it may ensure to be resistant to
Surge impact capacity is comprehensively more than the second piezoresistive wafer.
Preferably, the nominal diameter of first piezoresistive wafer is nominal straight at least more than second piezoresistive wafer
One sequence number of diameter.Since the diameter of flanking sequence number is than about 1.25 times, they are resistant to the parameter difference of surge impact capacity
About 1.5 times, as long as the second piezoresistive wafer is designed to match with application environment, then the first piezoresistive wafer belongs to
Redundancy Design, crash rate will be reduced than the second piezoresistive wafer in the order of magnitude, so that it may which guarantee makes the second piezoresistive wafer first
Deterioration.
Preferably, an electrode surface of second piezoresistive wafer connects first varistor by conducting bracket
One electrode of piece；Another electrode of the posive temperature coefficient thermistor piece connects first pressure by internal connection line
Another electrode of quick resistor disc.
Compared with prior art, beneficial effects of the present invention：
The present invention is equipped with the absorption surge pulse being composed in series by the first piezoresistive wafer, the second piezoresistive wafer simultaneously
Main channel, and protected by the heat that the second piezoresistive wafer, third piezoresistive wafer, posive temperature coefficient thermistor piece are connected in series
Protect branch, and two branch circuit parallel connections.Under conventional failure conditions and special failure conditions, the overheat disconnector of SPD can be acted
It cuts off the power, so that SPD finally exits circuit with open circuit mode, relative to traditional short-circuit mode, greatly improves SPD's
Safety, it is therefore prevented that short circuit breakdown when generate smolder, arcing, even catching fire serious accident.Meanwhile overheating disconnector
Positioning indicator or electricity, sound, the light warning device being equipped with, so that the SPD of damage will soon be found, maintenance personal can
Easily to be replaced, safe handling is achieved the purpose that, to substantially increase the safety and reliability of SPD, route
The electrical equipment crash rate of upper connection also will significantly reduce.
In addition, the third piezoresistive wafer for being serially connected in Thermal protection branch mainly plays two, first is that adjusting Thermal protection branch
The sensitivity of road starting；Second is that adjusting the ability that single port combinational circuit is resistant to accessed voltage ripple of power network.
Detailed description of the invention：
Fig. 1 is the schematic illustration of improvement plan one described in background technique.
It is marked in Fig. 1：1- based varistor chip, 2- scale copper electrode, 3- leading-out terminal, 4- elastic sheet metal, 5-
Low-melting alloy.
Fig. 2 is the schematic illustration of improvement plan two described in background technique.
It is marked in Fig. 2：11- piezoresistive wafer, 12- thermosensitive resistor film, 13- gas-discharge tube, 14- exit, 15- are drawn
End, 16- encapsulated layer.
Fig. 3 is a kind of schematic diagram of the surge protection circuit of high safety described in the embodiment of the present invention 1.
Fig. 4 is a kind of schematic diagram of the surge protection circuit of high safety described in the embodiment of the present invention 2.
Fig. 5 is a kind of schematic diagram of the surge protection circuit of high safety described in the embodiment of the present invention 3.
Fig. 6 is a kind of schematic diagram of the surge protection circuit of high safety described in the embodiment of the present invention 3.
Fig. 7 is a kind of schematic diagram of the surge protection circuit of high safety described in the embodiment of the present invention 4.
Fig. 8 is a kind of schematic diagram of the surge protection circuit of high safety described in the embodiment of the present invention 4.
Fig. 9 is a kind of part drawing of the surge protective device of high safety described in the embodiment of the present invention 5.
Figure 10 is a kind of assembling figure of the surge protective device of high safety described in the embodiment of the present invention 5.
It is marked in Fig. 3-Figure 10：The first piezoresistive wafer of 1-, 11- the first piezoresistive wafer electrode surface, the pressure-sensitive electricity of 2- second
Hinder piece, 21- the second piezoresistive wafer electrode surface, 3- third piezoresistive wafer, 4- posive temperature coefficient thermistor piece, 5- exit
Son, 6- internal connection line, 7- conducting bracket.
Specific embodiment
Below with reference to test example and specific embodiment, the present invention is described in further detail.But this should not be understood
It is all that this is belonged to based on the technology that the content of present invention is realized for the scope of the above subject matter of the present invention is limited to the following embodiments
The range of invention.
Embodiment 1
As shown in figure 3, a kind of surge protection circuit of high safety, including the first piezoresistive wafer 1, the second piezoresistive wafer
2, third piezoresistive wafer 3, posive temperature coefficient thermistor piece 4 and leading-out terminal 5, the posive temperature coefficient thermistor piece 4
In parallel with first piezoresistive wafer 1 after connecting with the third piezoresistive wafer 3, the series-parallel branch is again with described second
Piezoresistive wafer 2 is connected, and a single port combinational circuit is formed, wherein first piezoresistive wafer 1 is resistant to surge impact
Performance is higher than the performance of second piezoresistive wafer 2 tolerance surge impact.
Two leading-out terminals 5 of the single port combinational circuit are the thermally conductive end of low thermal resistance, second varistor
Piece 2 and the third piezoresistive wafer 3 form thermal coupling, and the third piezoresistive wafer 3 and the positive temperature coefficient temperature-sensitive
Resistor disc 4 forms thermal coupling, and the thermally conductive end of low thermal resistance is thermally coupled to each other with second piezoresistive wafer 2, meanwhile, it is described
The thermally conductive end of low thermal resistance is thermally coupled to each other with the posive temperature coefficient thermistor piece 4.
The pressure sensitive voltage value of first piezoresistive wafer 1 is the 0.9 to 1.1 of accessed network operation voltage peak
Times；The pressure sensitive voltage value of the third piezoresistive wafer 3 is less than or equal to the 85% of accessed network operation voltage peak；Institute
State the maximum continuous work voltage value of the second piezoresistive wafer 2 and the maximum continuous work voltage of the third piezoresistive wafer 3
The sum of value is greater than accessed network operation voltage value.
Embodiment 2
As shown in figure 4, the present embodiment the difference from embodiment 1 is that, two exits of the single port combinational circuit
Sub 5 only ones are the thermally conductive end of low thermal resistance, and second piezoresistive wafer 2 forms thermal coupling with the third piezoresistive wafer 3,
And the third piezoresistive wafer 3 forms thermal coupling, the thermally conductive end of low thermal resistance with the posive temperature coefficient thermistor piece 4
It is thermally coupled to each other with second piezoresistive wafer 2.
Embodiment 3
The present embodiment the difference from embodiment 1 is that, two 5 only ones of leading-out terminal of the single port combinational circuit are
The thermally conductive end of low thermal resistance, second piezoresistive wafer 2 form thermal coupling, and the third with the third piezoresistive wafer 3
Piezoresistive wafer 3 and the posive temperature coefficient thermistor piece 4 form thermal coupling.The thermally conductive end of low thermal resistance and the positive temperature
Degree coefficient resistance piece 4 is thermally coupled to each other (as shown in Figure 5) or the thermally conductive end of the low thermal resistance and the third varistor
Piece 3 is thermally coupled to each other (as shown in Figure 6).
Embodiment 4
The present embodiment the difference from embodiment 1 is that, two 5 only ones of leading-out terminal of the single port combinational circuit are
The thermally conductive end of low thermal resistance, the third piezoresistive wafer 3 form thermal coupling with the posive temperature coefficient thermistor piece 4.It is described
The thermally conductive end of low thermal resistance and the posive temperature coefficient thermistor piece 4 are thermally coupled to each other (as shown in Figure 7) or the low thermal resistance is led
Hot end head is thermally coupled to each other (as shown in Figure 8) with the third piezoresistive wafer 3.At this point, second piezoresistive wafer 2 is not joined
With thermal coupling.
Embodiment 5
As shown in Fig. 9-Figure 10, a kind of surge protective device of high safety, one second of second piezoresistive wafer 2
It is connected with the third piezoresistive wafer 3 on piezoresistive wafer electrode surface 21, while the first pressure-sensitive electricity is connected by conducting bracket 7
An electrode surface 11 of piece 1 is hindered, the positive temperature coefficient heat is connected on another electrode surface of the third piezoresistive wafer 3
Another electrode of quick resistor disc 4, the posive temperature coefficient thermistor piece 4 is connected with described first by internal connection line 6
Another the first piezoresistive wafer electrode surface 11 of piezoresistive wafer 1, second piezoresistive wafer 2 and/or the positive temperature
Leading-out terminal 5 is also welded on coefficient resistance piece 4, wherein at least one is the thermally conductive end of low thermal resistance.First varistor
Piece 1, second piezoresistive wafer 2, the third piezoresistive wafer 3, the posive temperature coefficient thermistor piece 4 are encapsulated as one
Body.
Specifically, the pressure-sensitive tile (40K331x2) of square of the first piezoresistive wafer 1 selection two panels nominal diameter 40mm
For equivalent substitution to reduce mounting area, which is that the industry is the routine side for reducing mounting area and using after parallel connection
Formula can also directly adopt the pressure-sensitive tile of rectangle certainly, and pressure sensitive voltage is 330 volts, and maximum discharge current Imax is 80KA；The
Two piezoresistive wafers 2 select the pressure-sensitive tile 40K331 of square of nominal diameter 40mm, and pressure sensitive voltage is 330 volts, maximum electric discharge
Electric current Imax is 40KA；Third piezoresistive wafer 3 select the pressure-sensitive tile 10K201 of circle of nominal diameter 10mm, pressure sensitive voltage for
200V；160 DEG C of Curie point of the selection of posive temperature coefficient thermistor 4,150 ohm of room temperature resistance value, the disk of diameter 10mm.It should
It is suitble to work in 220 volts of common frequency power networks with reference to selection, the operating temperature of overheat disconnector matched with its is 120 DEG C.
Package unit is connected on 220 coucher frequency routes, and applies the surge repeated impacts of In=20KA, the 99th punching
Disconnector movement is overheated after hitting, and is cooled to and is tested the pressure sensitive voltage value of the second piezoresistive wafer 2 after room temperature to be that 0 ambuscade is worn short
Road, and the first piezoresistive wafer 1 is still 327 volts, is remained unchanged substantially.
Above embodiments are only to illustrate the present invention and not limit the technical scheme described by the invention, although this explanation
The present invention has been described in detail referring to above-mentioned each embodiment for book, but the present invention is not limited to above-mentioned specific implementation
Mode, therefore any couple of present invention modifies or equivalent replacement；And the technical side of all spirit and scope for not departing from invention
Case and its improvement, are intended to be within the scope of the claims of the invention.
Claims (10)
1. a kind of surge protection circuit of high safety, including the first piezoresistive wafer (1), the second piezoresistive wafer (2), third pressure
Quick resistor disc (3), posive temperature coefficient thermistor piece (4) and leading-out terminal (5), which is characterized in that the positive temperature coefficient heat
Quick resistor disc (4) is in parallel with the first piezoresistive wafer (1) after connecting with the third piezoresistive wafer (3), the series-parallel branch
It connects again with second piezoresistive wafer (2), forms a single port combinational circuit, wherein first piezoresistive wafer
(1) performance of tolerance surge impact is higher than the performance of second piezoresistive wafer (2) tolerance surge impact；
At least one in two leading-out terminals (5) of the single port combinational circuit be the thermally conductive end of low thermal resistance, described second
Piezoresistive wafer (2) and the third piezoresistive wafer (3) form thermal coupling, and the third piezoresistive wafer (3) with it is described
Posive temperature coefficient thermistor piece (4) formation thermal coupling, the thermally conductive end of low thermal resistance and second piezoresistive wafer (2),
Wherein one or two in the posive temperature coefficient thermistor piece (4) is thermally coupled to each other simultaneously.
2. the surge protection circuit of high safety according to claim 1, which is characterized in that first piezoresistive wafer
(1) pressure sensitive voltage value is 0.9 to 1.1 times of accessed network operation voltage peak.
3. the surge protection circuit of high safety according to claim 2, which is characterized in that when accessing 220V power grid, institute
The pressure sensitive voltage value for stating the first piezoresistive wafer (1) is 280V-342V；When accessing 110V power grid, first varistor
The pressure sensitive voltage value of piece (1) is 140V-171V；When accessing 380V power grid, the pressure sensitive voltage of first piezoresistive wafer (1)
Value is 484V-591V.
4. the surge protection circuit of high safety according to claim 1, which is characterized in that the third piezoresistive wafer
(3) pressure sensitive voltage value is less than or equal to the 85% of accessed network operation voltage peak；Second piezoresistive wafer (2)
The sum of maximum continuous work voltage value and the maximum continuous work voltage value of the third piezoresistive wafer (3) be greater than and accessed
Network operation voltage value.
5. the surge protection circuit of high safety according to claim 4, which is characterized in that when accessing 220V power grid, institute
The pressure sensitive voltage value for stating third piezoresistive wafer (3) is less than or equal to 264V；When accessing 110V power grid, the pressure-sensitive electricity of third
The pressure sensitive voltage value for hindering piece (3) is less than or equal to 132V；When accessing 380V power grid, the pressure of the third piezoresistive wafer (3)
Quick voltage value is less than or equal to 457V.
6. the surge protection circuit of high safety according to claim 1, which is characterized in that the thermally conductive end of low thermal resistance with
The posive temperature coefficient thermistor piece (4), which is thermally coupled to each other, can be replaced, the thermally conductive end of low thermal resistance and the third pressure
Quick resistor disc (3) is thermally coupled to each other.
7. a kind of surge protection circuit of high safety, including the first piezoresistive wafer (1), the second piezoresistive wafer (2), third pressure
Quick resistor disc (3), posive temperature coefficient thermistor piece (4) and leading-out terminal (5), which is characterized in that the positive temperature coefficient heat
Quick resistor disc (4) is in parallel with the first piezoresistive wafer (1) after connecting with the third piezoresistive wafer (3), the series-parallel branch
It connects again with second piezoresistive wafer (2), forms a single port combinational circuit, wherein first piezoresistive wafer
(1) performance of tolerance surge impact is higher than the performance of second piezoresistive wafer (2) tolerance surge impact；
There is one in two leading-out terminals (5) of the single port combinational circuit for the thermally conductive end of low thermal resistance, the third is pressure-sensitive
Resistor disc (3) and the posive temperature coefficient thermistor piece (4) form thermal coupling, the thermally conductive end of low thermal resistance and the positive temperature
Degree coefficient resistance piece (4) or the third piezoresistive wafer (3) are thermally coupled to each other.
8. the surge protection circuit of -7 any high safeties according to claim 1, which is characterized in that the positive temperature coefficient
Thermosensitive resistor film (4) can be replaced the resistance of linear feature.
9. a kind of surge protective device of high safety, which is characterized in that including a kind of Gao An as claimed in claim 1
Full surge protection circuit is connected with the third piezoresistive wafer on one electrode surface of second piezoresistive wafer (2)
(3) and an electrode of the first piezoresistive wafer (1) it, is connected on another electrode surface of the third piezoresistive wafer (3)
The posive temperature coefficient thermistor piece (4) connects on another electrode of the posive temperature coefficient thermistor piece (4)
State another electrode of the first piezoresistive wafer (1), second piezoresistive wafer (2) and/or the positive temperature coefficient temperature-sensitive
The thermally conductive end of low thermal resistance (5) is also welded on resistor disc (4).
10. the surge protective device of high safety according to claim 9, which is characterized in that first piezoresistive wafer
(1) the first piezoresistive wafer electrode surface (11) area is greater than the second piezoresistive wafer electricity of second piezoresistive wafer (2)
Pole-face (21) area；And/or the nominal diameter of first piezoresistive wafer (1) is at least more than second piezoresistive wafer
(2) one sequence number of nominal diameter.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2018107684626 | 2018-07-12 | ||
| CN201810768462 | 2018-07-12 |
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| CN108879642A true CN108879642A (en) | 2018-11-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201811040609.6A Withdrawn CN108879642A (en) | 2018-07-12 | 2018-09-06 | The surge protection circuit and surge protective device of high safety |
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|---|---|---|---|---|
| CN1581626A (en) * | 2003-08-05 | 2005-02-16 | 刘金生 | Anti interference method and device |
| TWI231078B (en) * | 2000-08-29 | 2005-04-11 | Citel | Overvoltage-protection device |
| JP2012210009A (en) * | 2011-03-29 | 2012-10-25 | Ntt Facilities Inc | Surge protection device |
| CN103346547A (en) * | 2013-06-28 | 2013-10-09 | 华南理工大学 | Anti-thunder overvoltage protection device |
| CN104393562A (en) * | 2014-11-14 | 2015-03-04 | 华南理工大学 | Overvoltage and electric leakage integrated protection circuit breaker |
| CN209072062U (en) * | 2018-07-12 | 2019-07-05 | 成都铁达电子股份有限公司 | The surge protection circuit and surge protective device of high safety |
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2018
- 2018-09-06 CN CN201811040609.6A patent/CN108879642A/en not_active Withdrawn
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI231078B (en) * | 2000-08-29 | 2005-04-11 | Citel | Overvoltage-protection device |
| CN1581626A (en) * | 2003-08-05 | 2005-02-16 | 刘金生 | Anti interference method and device |
| JP2012210009A (en) * | 2011-03-29 | 2012-10-25 | Ntt Facilities Inc | Surge protection device |
| CN103346547A (en) * | 2013-06-28 | 2013-10-09 | 华南理工大学 | Anti-thunder overvoltage protection device |
| CN104393562A (en) * | 2014-11-14 | 2015-03-04 | 华南理工大学 | Overvoltage and electric leakage integrated protection circuit breaker |
| CN209072062U (en) * | 2018-07-12 | 2019-07-05 | 成都铁达电子股份有限公司 | The surge protection circuit and surge protective device of high safety |
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Application publication date: 20181123 |