CN209072061U - Novel Thunder-prevention overvoltage protection device - Google Patents

Abstract

The utility model discloses a kind of novel Thunder-prevention overvoltage protection devices; including the first piezoresistive wafer, the second piezoresistive wafer, posive temperature coefficient thermistor piece and leading-out terminal; first piezoresistive wafer is in parallel with the posive temperature coefficient thermistor piece; the parallel branch is connected with second piezoresistive wafer again; form a single port combinational circuit; wherein, the performance of the first piezoresistive wafer tolerance surge impact is higher than the performance of second piezoresistive wafer tolerance surge impact；At least one in two leading-out terminals of the single port combinational circuit is the thermally conductive end of low thermal resistance, second piezoresistive wafer and the posive temperature coefficient thermistor piece thermal coupling, the thermally conductive end of low thermal resistance is thermally coupled to each other simultaneously with wherein one or two in second piezoresistive wafer, the posive temperature coefficient thermistor piece.

Description

Novel Thunder-prevention overvoltage protection device

Technical field

The utility model relates to field of power supplies, in particular to a kind of novel Thunder-prevention overvoltage protection device.

Background technique

A kind of low-voltage electrical apparatus of the Surge Protector (abbreviation SPD) as standard, is widely used in low pressure electric line, The surge as caused by thunder and lightning etc. occurred in route effectively can be absorbed and be inhibited, to improvement grid power transmission quality, be protected Card electrical appliance has safely apparent effect.

The core component of SPD is Surge suppression element, and the most commonly used is based varistor chips.Due to electric line Transmission range is longer, but be easy to be exposed to it is outdoor, compared to indoor electric appliance equipment be easier by high-energy surge pulse, in SPD Phase projected life in, based varistor chip be easier by be more than rated specification high-energy surge repeat impact, Cause the deterioration failure of varistor.Since varistor is short circuit failure mode, once breakdown failure, will cause supply lines Road short trouble, breakdown point will appear burst, smolder, arcing, it is serious when in addition will cause catching fire.

Improvement plan is first is that most common method, concrete principle figure are shown in attached drawing 1, at two of based varistor chip 1 It on end electrode, is respectively welded and connects a piece of conductive and all excellent heating conduction scale copper electrode 2, scale copper electrode 2 is prefabricated There is leading-out terminal 3, scale copper electrode 2 also forms thermal coupling with based varistor chip 1 while playing the role of conductive electrode It closes, the heat that based varistor chip 1 generates can be transmitted on leading-out terminal 3.Wherein with low on a leading-out terminal 3 Melting alloy 5 welds a piece of elastic sheet metal 4 and forms overheat disconnector.It is flowed into when based varistor chip 1 is deteriorated to electric leakage When entering milliampere grade, accelerated deterioration area is initially entered, leakage current can make the fever of based varistor chip 1 promote leakage current further Increase, and accelerate the fever of based varistor chip 1, will finally make 1 thermal breakdown of based varistor chip.When heat reaches When 5 fusing-off temperature of low-melting alloy, disconnector action power dump is overheated, makes based varistor chip 1 before puncture short Power grid is exited, has achieved the purpose that protection.The program can be by the failure mode of most based varistor chip 1 from pernicious Short-circuit mode is converted to the open circuit mode for influencing very little, greatly improves the safety of SPD.

But still there is also some defects for the program, since the movement of overheat disconnector needs to be delayed by several seconds the time, and 1 leakage current of based varistor chip enters milliampere grade and starts accelerated deterioration adstante febre, and the defect inside porcelain body is very serious , there is the defect of partial chip seriously to arrive very short to the time of puncture short from starting to generate heat, heat also has little time to be transmitted to Hot disconnector melts low-melting alloy 5, and short circuit accident just has occurred.Another much situation is exactly when pressure-sensitive electricity Resistance ceramic chip 1 is deteriorated to when closing on accelerated deterioration area, and at this moment the leakage current of based varistor chip 1 is also less than milliampere grade, It can also maintain thermostabilization, additionally it is possible to work is maintained under the operating voltage of power grid, but its pressure sensitive voltage value at this time has compared Initial value when just starting to come into operation has apparent sharp fall, the anti-surge punching of based varistor chip 1 at this moment The ability hit is very fragile, an energy not counting it can be punctured or close to breakdown by too big surge, at this time it Puncture short speed is also that too fastly, overheat disconnector has little time response action and do not have protective effect.

For improvement plan second is that application No. is 201310268111.6 Chinese utility model patent, schematic diagram is shown in attached drawing 2, It will connect again with piezoresistive wafer 11 after ceramic positive temperature coefficient thermistor piece 12 and 13 parallel connection of gas-discharge tube, and temperature-sensitive Resistor disc 12 and piezoresistive wafer 11 are welded together to form thermal coupling, and exit 14 and exit 15 are connected in parallel on by protection power source On route, using epoxy resin enclosed, solidification after welding lead, encapsulated layer 16 is formed.Its main feature is that when piezoresistive wafer 11 is bad Change to leakage current to significantly increase and start to generate heat into after accelerated deterioration area, heating temperature is coupled to positive temperature coefficient ceramic temperature-sensitive electricity Piece 12 is hindered, resistance value rises after keeping it heated, reduces the leakage current for flowing into piezoresistive wafer 11, plays and extends the deterioration time Effect, and after the heating temperature of piezoresistive wafer 11 reaches the Curie point of thermosensitive resistor film 12, positive temperature coefficient ceramic Thermosensitive resistor film 12 becomes high-impedance state, limits the increase of leakage current, forces piezoresistive wafer 11 near Curie point Reach thermal balance, piezoresistive wafer 11 can maintain work under network operation voltage in spite of illness.

But the program still has some serious defects, is firstly because ceramic positive temperature coefficient thermistor piece 12 Metering function, piezoresistive wafer 11 deteriorates severe again, and heating temperature also only maintains the curie point temperature of thermosensitive resistor film 12 Near degree, work is exited without departing from power grid, until the pressure sensitive voltage value deterioration of piezoresistive wafer 12 is reduced to network operation electricity When the about half of voltage crest value, after concatenated discharge tube is connected for another surge impact, too low pressure sensitive voltage value pincers The power network current constantly followed causes gas-discharge tube 13 not return to off-state, will protect 12 short circuit of thermosensitive resistor film Protection circuit failure, at this time piezoresistive wafer 11 will puncture short immediately, cause serious short trouble.Theoretically, if do not had There are other safeguard procedures, most of varistor can all fail in this way.Another failure procedure and scheme one Situation is similar, i.e., when piezoresistive wafer 11 deteriorates to a certain extent, even if having not been entered into accelerated deterioration area, but because of its internal junction Structure has been seriously damaged, and the ability sharp fall of tolerance surge impact, a surge can be hit at this time It wears or close to breakdown, and gas-discharge tube 13 is also on state at this time, breakdown or same close to the piezoresistive wafer 11 of breakdown Sample also loses the ability of pincers power-off net follow current, causes thermosensitive resistor film 12 to protect circuit malfunction, causes serious short circuit Failure.

Utility model content

The purpose of the utility model is to overcome the above-mentioned deficiencies in the presence of the prior art, provide a kind of novel lightning protection Over-voltage protector.

In order to achieve the above-mentioned object of the invention, the utility model provides following technical scheme:

A kind of novel Thunder-prevention overvoltage protection device, including the first piezoresistive wafer, the second piezoresistive wafer, positive temperature system Number thermosensitive resistor film and leading-out terminal, first piezoresistive wafer is in parallel with the posive temperature coefficient thermistor piece, this is simultaneously Connection branch is connected with second piezoresistive wafer again, forms a single port combinational circuit, wherein first varistor The performance that piece is resistant to surge impact is higher than the performance of second piezoresistive wafer tolerance surge impact；

At least one in two leading-out terminals of the single port combinational circuit be the thermally conductive end of low thermal resistance, described second Piezoresistive wafer and the posive temperature coefficient thermistor piece thermal coupling, the thermally conductive end of low thermal resistance and the described second pressure-sensitive electricity Wherein one or two in resistance piece, the posive temperature coefficient thermistor piece is thermally coupled to each other simultaneously.In use, described low The thermally conductive end connection overheat disconnector of thermal resistance, it is de- that the Curie point of the posive temperature coefficient thermistor piece is higher than the overheat Operating temperature from device.

The principle Analysis of the utility model is as follows:

It is the main channel for absorbing surge pulse by the series loop that the first piezoresistive wafer, the second piezoresistive wafer form, When not having surge pulse, varistor is in high-impedance state, and when surge arrives, varistor is in low resistive state, surge energy Amount thus release by circuit.At this point, the voltage-limiting protection level of SPD is regarded as the residual voltage value of the first piezoresistive wafer and second pressure-sensitive The sum of residual voltage value of resistor disc.After surge disappears, piezoresistive wafer returns to high-impedance state.In order to ensure the member in surge channel Device degradation in tolerance surge impact capacity selection, will should follow the first piezoresistive wafer since the second piezoresistive wafer Tolerance be greater than the principle of the second piezoresistive wafer, significantly deteriorated with reaching when the second piezoresistive wafer, started to open When dynamic Thermal protection circuit, the also substantially intact purpose of the first piezoresistive wafer.

Another circuit is the Thermal protection branch being connected in series by the second piezoresistive wafer and posive temperature coefficient thermistor piece Road, and overheat disconnector is connected to by thermally conductive end.When the intact no surge of element, due to being in high resistant not on-state, The leakage current for flowing through the second piezoresistive wafer is minimum (microampere order), and branch is protected not generate heat.Even if when surge comes temporarily, due to just Temperature coefficient thermistor piece still has tens Dao a several hundred ohm resistance value at normal temperature, and the first piezoresistive wafer connected in parallel In the case where absorbing surge on state, its dynamic electric resistor can be several ohm down to zero point, and major part surge current absolutely is from the first varistor Piece passes through.And the voltage at posive temperature coefficient thermistor piece both ends is also limited in the residual voltage value of the first piezoresistive wafer, stream The surge current for crossing thermistor at most namely pacifies times grade with this condition, the heat that thermistor generates in a short period of time Measure minimum and surge just disappears, protection branch can because generate heat it is faint due to be failure to actuate.

The Analysis of Failure Mechanism of the utility model is as follows:

After the second piezoresistive wafer, which is deteriorated to leakage current, to be reached milliampere grade and enter accelerated deterioration area, by be coupled to second It generates heat caused by the leakage current of heat and increase that piezoresistive wafer generates, in the resistance value for promoting posive temperature coefficient thermistor piece It rises, and finally reaches thermal balance above Curie point, leakage current strangulation compared with fractional value, so that the second piezoresistive wafer Deterioration process elongated.Heat can be transmitted to overheat disconnector from thermally conductive end at leisure, and temperature can achieve Curie Near temperature, the operating temperature for overheating disconnector is set lower than at Curie temperature, can reliably disengaging be acted, to make to deteriorate SPD be detached from power network line.The technical program can make the SPD after most deteriorate exit electricity in this safe mode Net.

For those much special circumstances, i.e., when the second piezoresistive wafer deteriorates to a certain extent or has located When accelerated deterioration area, its anti-impulse ability has declined to a great extent at this time, and stronger surge of energy can be It directly punctures or close breakdown.When surge disappear after, due to resistance to surge impact capacity it is stronger and substantially intact than it first Piezoresistive wafer still is able to maintain high-impedance state, and thermostabilization can still be maintained in power grid, will not occur significant bad Change phenomenon, sufficient action response time can be provided to Thermal protection branch, network operation voltage still will be applied to just at this time Temperature coefficient thermistor piece both ends, it still can generate heat to Curie point and make to overheat disconnector movement, overheat disconnector Will action power dump, make damage SPD safely exit power grid.Since overheat disconnector is generally provided with state instruction Device or electricity, sound, light warning device, will soon be found, and maintenance personal replaces in which can be convenient, and having reached safety makes Purpose.To substantially increase the safety and reliability of SPD, the electrical equipment crash rate connected on route also will substantially Degree reduces.

It should be noted that in Thermal protection branch, second piezoresistive wafer and positive temperature coefficient temperature-sensitive electricity Resistance piece is not necessarily to form thermal coupling, after choosing suitable component parameters, second piezoresistive wafer or the positive temperature Fever caused by the coefficient resistance piece heat individually generated and the leakage current of increase is spent, can equally promote to overheat disconnector Movement, also can achieve the goal of the invention of the utility model.

Further, the posive temperature coefficient thermistor piece can replace with the resistance of linear feature, linear special The electric current of the resistance of sign is substantially proportional to voltage, i.e., its characteristic equation is mainly linear homogeneous, and defers to Ohm's law. The resistance of linear feature can also play the role of following in Thermal protection branch: first is that metering function, when described second pressure-sensitive After resistor disc accelerated deterioration even puncture short, the resistance of linear feature can pacify the current limit in Thermal protection branch Within total head, it not will cause the Thunder-prevention overvoltage protection device short circuit and burn；Second is that heating functioin, the electric current within safety value is held The continuous resistance by second piezoresistive wafer and linear feature, which will be such that they are warming up to, makes to overheat disconnector movement, together Sample can achieve the purpose of Thermal protection.To reach said effect, the current value of Thermal protection branch in the most adverse case (second Piezoresistive wafer puncture short) it is advisable for tens milliamperes to several amperes, the resistance value of the resistance of corresponding linear feature is several Kilohm to tens ohm.

In the present invention, the resistance of linear feature both includes linear resistance, also allow containing it is some it is non-linear at Divide (non-linear component is smaller, mainly still embodies Ohm's law feature), but power is required to want sufficiently large, pressure resistance is wanted It is sufficiently high, at least to adhere to that failure cannot be damaged before overheating disconnector movement.

Preferably, the first piezoresistive wafer electrode surface area of first piezoresistive wafer is greater than the described second pressure-sensitive electricity Hinder the second piezoresistive wafer electrode surface area of piece.Measuring piezoresistive wafer tolerance surge impact capacity has multinomial technical indicator, It is main to have: dash current I_imp, current waveform is 10/350 μ s；Maximum discharge current I_max, current waveform is 8/20 μ s；Energy Tolerance, current waveform are 2ms square wave；Rush of current stability is exactly with 8/20 μ s waveform nominal discharge current In repeated impacts The number etc. being resistant to.Under identical geometric dimension, by adjusting ceramic formula or technological parameter can optimize one of them or Multiple parameters index, but want General Promotion or relatively difficult.But these technical indicators are all and varistor plate electrode Area is directly proportional, therefore, as long as increasing the area of the first varistor plate electrode under the conditions of same process, so that it may ensure to be resistant to Surge impact capacity is comprehensively more than the second piezoresistive wafer.

Preferably, the nominal diameter of first piezoresistive wafer is nominal straight at least more than second piezoresistive wafer One sequence number of diameter.Since the diameter of flanking sequence number is than about 1.25 times, they are resistant to the parameter difference of surge impact capacity About 1.5 times, as long as the second piezoresistive wafer is designed to match with application environment, then the first piezoresistive wafer belongs to Redundancy Design, crash rate will be reduced than the second piezoresistive wafer in the order of magnitude, so that it may which guarantee makes the second piezoresistive wafer first Deterioration.

Preferably, the pressure sensitive voltage value of first piezoresistive wafer is the 0.9 of accessed network operation voltage peak To 1.1 times.It can guarantee in the case where the second piezoresistive wafer thorough puncture short, after surge disappears, the first pressure-sensitive electricity Resistance piece can also return to high-impedance state, and thermostabilization can still be maintained in power grid, and sufficient movement is provided to Thermal protection branch Response time improves the safety of single port combinational circuit.When the pressure sensitive voltage value of the first piezoresistive wafer is selected too low, no It can guarantee and securely maintain thermostabilization in the case；When selecting excessively high, the limitation electricity of single port over-voltage protector can be improved Index is pressed, level of protection is influenced.

Specifically, the pressure sensitive voltage value of first piezoresistive wafer is 280V-342V when accessing 220V power grid；When When accessing 110V power grid, the pressure sensitive voltage value of first piezoresistive wafer is 140V-171V；When accessing 380V power grid, institute The pressure sensitive voltage value for stating the first piezoresistive wafer is 484V-591V.

Preferably, positive temperature coefficient is connected on a second piezoresistive wafer electrode surface of second piezoresistive wafer One electrode of thermosensitive resistor film and the first piezoresistive wafer connects on another electrode of the posive temperature coefficient thermistor piece It is connected to another electrode of first piezoresistive wafer, second piezoresistive wafer and/or the positive temperature coefficient temperature-sensitive The thermally conductive end of low thermal resistance is welded on resistor disc, also to realize the thermal coupling of element.The connection of element preferentially select electrode surface it Between directly weld, as far as possible less with internal connecting lead wire or conducting bracket.

Preferably, the thermally conductive end of low thermal resistance with thermally conductive function has foot using excellent materials of heating conductions such as copper Enough big cross-sectional areas.And pyrotoxin (piezoresistive wafer or positive temperature coefficient temperature-sensitive are connected to using thermal couplings modes such as welding On resistor disc), and distance of the thermally conductive end away from pyrotoxin will as far as possible it is short, to obtain minimum thermal resistance, guarantee has enough Heat is transmitted to overheat disconnector.

Preferably, second piezoresistive wafer, posive temperature coefficient thermistor piece, the first piezoresistive wafer are encapsulated as one Body.

Preferably, first piezoresistive wafer is formed by two panels with the pressure-sensitive tile parallel connection of size.

Preferably, an electrode surface of second piezoresistive wafer connects first varistor by conducting bracket One electrode of piece；It is pressure-sensitive that one electrode of the posive temperature coefficient thermistor piece by internal connection line connects described first Another electrode of resistor disc.

Preferably, the impact resistance current rating of first piezoresistive wafer is higher than the resistance to of second piezoresistive wafer Dash current rated value.

The invention also discloses a kind of novel Thunder-prevention overvoltage protection devices, including the first piezoresistive wafer, second Piezoresistive wafer, posive temperature coefficient thermistor piece and leading-out terminal, first piezoresistive wafer and the positive temperature coefficient Thermosensitive resistor film is in parallel, which connects with second piezoresistive wafer again, forms a single port combinational circuit, In, the performance of the first piezoresistive wafer tolerance surge impact is higher than the property of second piezoresistive wafer tolerance surge impact Energy；

At least one in two leading-out terminals of the single port combinational circuit is the thermally conductive end of low thermal resistance, the low-heat Hinder thermally conductive end and second piezoresistive wafer, in the posive temperature coefficient thermistor piece wherein one or two simultaneously It is thermally coupled to each other.

Compared with prior art, the utility model has the beneficial effects that

The utility model is equipped with the absorption surge arteries and veins being composed in series by the first piezoresistive wafer, the second piezoresistive wafer simultaneously The main channel of punching, and the Thermal protection branch being connected in series by the second piezoresistive wafer and posive temperature coefficient thermistor piece, and Two branch circuit parallel connections.Under conventional failure conditions and special failure conditions, the overheat disconnector of SPD can action power dump, So that SPD finally exits circuit with open circuit mode, relative to traditional short-circuit mode, the safety of SPD is greatly improved, is prevented Stopped generated when short-circuit breakdown smolder, arcing, even catching fire serious accident.Meanwhile overheating what disconnector was equipped with Positioning indicator or electricity, sound, light warning device, so that the SPD of damage will soon be found, maintenance personal can be convenient ground It is replaced, has achieved the purpose that safe handling, to substantially increase the safety and reliability of SPD, connected on route Electrical equipment crash rate also will significantly reduce.

Detailed description of the invention:

Fig. 1 is the schematic illustration of improvement plan one described in background technique.

It is marked in Fig. 1: 1- based varistor chip, 2- scale copper electrode, 3- leading-out terminal, 4- elastic sheet metal, 5- Low-melting alloy.

Fig. 2 is the schematic illustration of improvement plan two described in background technique.

Mark in Fig. 2: 11- piezoresistive wafer, 12- thermosensitive resistor film, 13- gas-discharge tube, 14- exit, 15- are drawn End, 16- encapsulated layer.

Fig. 3 is the schematic illustration of the novel Thunder-prevention overvoltage protection device of one kind described in the utility model.

Fig. 4 is the part drawing of the novel Thunder-prevention overvoltage protection device of one kind described in the utility model embodiment 1.

Fig. 5 is the assembling figure of the novel Thunder-prevention overvoltage protection device of one kind described in the utility model embodiment 1.

Fig. 6 is the part drawing of the novel Thunder-prevention overvoltage protection device of one kind described in the utility model embodiment 2.

Fig. 7 is the assembling figure of the novel Thunder-prevention overvoltage protection device of one kind described in the utility model embodiment 2.

It is marked in Fig. 3-Fig. 7: the second piezoresistive wafer of 1-, 11- the second piezoresistive wafer electrode surface, 2- positive temperature coefficient heat Quick resistor disc, the first piezoresistive wafer of 3-, 31- the first piezoresistive wafer electrode surface, 4- leading-out terminal, 5- internal connection line, 6- Conducting bracket.

Specific embodiment

The utility model is described in further detail below with reference to test example and specific embodiment.But it should not be by this The range for being interpreted as the above-mentioned theme of the utility model is only limitted to embodiment below, all to be realized based on the content of the present invention Technology belongs to the scope of the utility model.

Embodiment 1

As shown in Figure 3-Figure 5, a kind of novel Thunder-prevention overvoltage protection device, including the first piezoresistive wafer 3, second are pressure-sensitive Resistor disc 1, posive temperature coefficient thermistor piece 2 and leading-out terminal 4, first piezoresistive wafer 3 and the positive temperature coefficient Thermosensitive resistor film 2 is in parallel, which connects with second piezoresistive wafer 1 again, forms a single port combinational circuit, Wherein, the performance that first piezoresistive wafer 3 is resistant to surge impact is higher than second piezoresistive wafer 1 tolerance surge impact Performance.

At least one in two leading-out terminals 4 of the single port combinational circuit is the thermally conductive end of low thermal resistance, described the Two piezoresistive wafers 1 and 2 thermal coupling of posive temperature coefficient thermistor piece, the thermally conductive end of low thermal resistance and second pressure Quick 1 thermal coupling of resistor disc, and the thermally conductive end of the low thermal resistance and 2 thermal coupling of posive temperature coefficient thermistor piece.In use, In the thermally conductive end connection overheat disconnector of the low thermal resistance, the Curie point of the posive temperature coefficient thermistor piece 2 is higher than The operating temperature of the overheat disconnector.

31 area of the first piezoresistive wafer electrode surface of first piezoresistive wafer 3 is greater than second piezoresistive wafer 1 11 area of the second piezoresistive wafer electrode surface, the nominal diameter of first piezoresistive wafer 3 is at least more than second pressure One sequence number of nominal diameter of quick resistor disc 1, the pressure sensitive voltage value of first piezoresistive wafer 3 is accessed power grid 0.9 to 1.1 times of operating voltage peak value.

Specific assembling mode are as follows:

First piezoresistive wafer 3 selects the pressure-sensitive tile 50k301 of the rectangle of nominal diameter 50mm, pressure sensitive voltage 300 Volt, maximum discharge current Imax are 60KA.Second piezoresistive wafer 1 selects the pressure-sensitive tile of square of nominal diameter 40mm 40k391, pressure sensitive voltage are 390 volts, and maximum discharge current Imax is 40KA.Posive temperature coefficient thermistor 2 selects Curie temperature 160 DEG C of point, 150 ohm of room temperature resistance value, the disk of diameter 12mm.The parameter selection is suitble to work in 220 volts of common frequency power networks, The operating temperature of overheat disconnector matched with its is 120 DEG C.

Positive temperature coefficient is welded and connected on one the second piezoresistive wafer electrode surface 11 of second piezoresistive wafer 1 Thermosensitive resistor film 2, while passing through the electrode that conducting bracket 6 is connected with first piezoresistive wafer 3, the positive temperature system Number thermosensitive resistor films 2 another electrode by internal connection line 5 be connected with first piezoresistive wafer 3 another first Piezoresistive wafer electrode surface 31.It is also welded on second piezoresistive wafer 1 and/or the posive temperature coefficient thermistor piece 2 There is the thermally conductive end of low thermal resistance, welds a piece of elastic sheet metal formation overheat with low-melting alloy on the thermally conductive end of low thermal resistance and take off From device.Second piezoresistive wafer 1, posive temperature coefficient thermistor piece 2, the first piezoresistive wafer 3 are packaged as a whole.

Package unit is connected on 220 coucher frequency routes, and applies the surge repeated impacts of In=20KA, the 86th punching Disconnector movement is overheated after hitting, and is cooled to and is tested the pressure sensitive voltage value of the second piezoresistive wafer 1 after room temperature and be deteriorated to 224 Volt, and the first piezoresistive wafer 3 is still 298 volts, is remained unchanged substantially.

Embodiment 2

As Figure 6-Figure 7, the present embodiment difference from example 1 is that, first piezoresistive wafer 3 is by two The pressure-sensitive tile (40K301x2) of square of piece nominal diameter 40mm is in parallel to be formed, and equivalent substitution is after parallel connection to reduce mounting surface Product, the parallel way are that the industry is the usual manner for reducing mounting area and using, and 3 voltage of the first piezoresistive wafer is 300 Volt, maximum discharge current Imax are 80KA.Second piezoresistive wafer 1 selects the pressure-sensitive tile of square of nominal diameter 40mm 40K391, pressure sensitive voltage are 390 volts, and maximum discharge current Imax is 40KA.Posive temperature coefficient thermistor 2 selects Curie temperature 160 DEG C of point, 150 ohm of room temperature resistance value, the disk of diameter 12mm.Reference selection is suitble to work in 220 volts of common frequency power networks, with The operating temperature of its matched overheat disconnector is 120 DEG C.

Package unit is connected on 220 coucher frequency routes, and applies the surge repeated impacts of In=20KA, the 101st time Disconnector movement is overheated after impact, is cooled to and is tested the pressure sensitive voltage value of the second piezoresistive wafer 1 after room temperature and be deteriorated to 256 Volt, and the first piezoresistance piece 3 is still 299 volts, is remained unchanged substantially.

Above embodiments are only to illustrate the utility model and not limit technical solution described in the utility model, to the greatest extent Pipe this specification has been carried out detailed description to the utility model referring to above-mentioned each embodiment, but the utility model not office It is limited to above-mentioned specific embodiment, therefore any pair of the utility model is modified or equivalent replacement；And all do not depart from it is practical The technical solution and its improvement of novel spirit and scope, should all cover in the scope of the claims of the utility model.

Claims (11)

1. a kind of novel Thunder-prevention overvoltage protection device, including the first piezoresistive wafer (3), the second piezoresistive wafer (1), positive temperature Spend coefficient resistance piece (2) and leading-out terminal (4), which is characterized in that first piezoresistive wafer (3) and the positive temperature Coefficient resistance piece (2) is in parallel, which connects with second piezoresistive wafer (1) again, forms a single port Combinational circuit, wherein the performance of the first piezoresistive wafer (3) tolerance surge impact is higher than second piezoresistive wafer (1) performance of tolerance surge impact；

At least one in two leading-out terminals (4) of the single port combinational circuit be the thermally conductive end of low thermal resistance, described second Piezoresistive wafer (1) and posive temperature coefficient thermistor piece (2) thermal coupling, the thermally conductive end of low thermal resistance and described second Wherein one or two in piezoresistive wafer (1), the posive temperature coefficient thermistor piece (2) is thermally coupled to each other simultaneously.

2. novel Thunder-prevention overvoltage protection device according to claim 1, which is characterized in that first piezoresistive wafer (3) the first piezoresistive wafer electrode surface (31) area is greater than the second piezoresistive wafer electricity of second piezoresistive wafer (1) Pole-face (11) area.

3. novel Thunder-prevention overvoltage protection device according to claim 1, which is characterized in that first piezoresistive wafer (3) one sequence number of nominal diameter of nominal diameter at least more than second piezoresistive wafer (1).

4. novel Thunder-prevention overvoltage protection device according to claim 1, which is characterized in that first piezoresistive wafer (3) pressure sensitive voltage value is 0.9 to 1.1 times of accessed network operation voltage peak.

5. novel Thunder-prevention overvoltage protection device according to claim 1, which is characterized in that second piezoresistive wafer (1) posive temperature coefficient thermistor piece (2) and first pressure are connected on a second piezoresistive wafer electrode surface (11) One the first piezoresistive wafer electrode surface (31) of quick resistor disc, another electricity of the posive temperature coefficient thermistor piece (2) Another the first piezoresistive wafer electrode surface (31) of first piezoresistive wafer (3) is connected on extremely, described second is pressure-sensitive The thermally conductive end of low thermal resistance is also welded on resistor disc (1) and/or the posive temperature coefficient thermistor piece (2).

6. novel Thunder-prevention overvoltage protection device according to claim 5, which is characterized in that second piezoresistive wafer (1), posive temperature coefficient thermistor piece (2), the first piezoresistive wafer (3) are packaged as a whole.

7. novel Thunder-prevention overvoltage protection device according to claim 1, which is characterized in that first piezoresistive wafer (3) impact resistance current rating is higher than the impact resistance current rating of second piezoresistive wafer (1).

8. novel Thunder-prevention overvoltage protection device according to claim 1, which is characterized in that when accessing 220V power grid, The pressure sensitive voltage value of first piezoresistive wafer (3) is 280V-342V；When accessing 110V power grid, the first pressure-sensitive electricity The pressure sensitive voltage value for hindering piece (3) is 140V-171V；When accessing 380V power grid, the pressure-sensitive electricity of first piezoresistive wafer (3) Pressure value is 484V-591V.

9. -8 any novel Thunder-prevention overvoltage protection device according to claim 1, which is characterized in that the positive temperature system Number thermosensitive resistor film (2) can replace with the resistance of linear feature.

10. a kind of novel Thunder-prevention overvoltage protection device, including the first piezoresistive wafer (3), the second piezoresistive wafer (1), just Temperature coefficient thermistor piece (2) and leading-out terminal (4), which is characterized in that first piezoresistive wafer (3) and the positive temperature Coefficient resistance piece (2) parallel connection is spent, which connects with second piezoresistive wafer (1) again, and formation one is single-ended Mouth combinational circuit, wherein the performance of the first piezoresistive wafer (3) tolerance surge impact is higher than second piezoresistive wafer (1) performance of tolerance surge impact；

At least one in two leading-out terminals (4) of the single port combinational circuit is the thermally conductive end of low thermal resistance, the low-heat Hinder one of them in thermally conductive end and second piezoresistive wafer (1), the posive temperature coefficient thermistor piece (2) or two It is a to be thermally coupled to each other simultaneously.

11. novel Thunder-prevention overvoltage protection device according to claim 10, which is characterized in that the positive temperature coefficient heat Quick resistor disc (2) can replace with the resistance of linear feature.