CN208385107U - A kind of voltage dependent resistor chip - Google Patents

Abstract

The utility model discloses a kind of voltage dependent resistor chips, including the first piezoresistive wafer, the second piezoresistive wafer and leading-out terminal, the first piezoresistive wafer series connection, second piezoresistive wafer, form a single port combinational circuit, wherein, the performance of the first piezoresistive wafer tolerance surge impact is higher than the performance of second piezoresistive wafer tolerance surge impact；At least one in two leading-out terminals of the single port combinational circuit is the thermally conductive end of low thermal resistance, and the thermally conductive end of low thermal resistance is thermally coupled to each other simultaneously with wherein one or two in first piezoresistive wafer, second piezoresistive wafer.This technology is resistant to the gap of the performance of surge impact by artificially manufacture two panels piezoresistive wafer, and when making the deterioration breakdown of the second piezoresistive wafer, the first piezoresistive wafer is substantially intact, realizes safety release using the thermal stability that it is not lowered substantially.

Description

A kind of voltage dependent resistor chip

Technical field

The utility model relates to field of power supplies, in particular to a kind of voltage dependent resistor chip.

Background technique

A kind of low-voltage electrical apparatus of the Surge Protector (abbreviation SPD) as standard, is widely used in low pressure electric line, The surge as caused by thunder and lightning etc. occurred in route effectively can be absorbed and be inhibited, to improvement grid power transmission quality, be protected Card electrical appliance has safely apparent effect.

The core component of SPD is Surge suppression element, and the most commonly used is based varistor chips.Due to electric line Transmission range is longer, but be easy to be exposed to it is outdoor, compared to indoor electric appliance equipment be easier by high-energy surge pulse, in SPD Phase projected life in, based varistor chip be easier by be more than rated specification high-energy surge repeat impact, Cause the deterioration failure of varistor.Since varistor is short circuit failure mode, once breakdown failure, will cause supply lines Road short trouble, breakdown point will appear burst, smolder, arcing, it is serious when in addition will cause catching fire.

The schematic diagram of most common ameliorative way is shown in attached drawing 1, on two end electrodes of based varistor chip 1, It being respectively welded and connects a piece of conductive and all excellent heating conduction scale copper electrode 2, scale copper electrode 2 is prefabricated with leading-out terminal 3, Scale copper electrode 2 also forms thermal coupling with based varistor chip 1 while playing the role of conductive electrode, can be by pressure-sensitive electricity The heat that resistance ceramic chip 1 generates is transmitted on leading-out terminal 3.It is welded on a leading-out terminal 3 with low-melting alloy 5 wherein A piece of elastic sheet metal 4 forms overheat disconnector.When based varistor chip 1, which is deteriorated to leakage current, enters milliampere grade, open Begin to enter accelerated deterioration area, leakage current can make the fever of based varistor chip 1 that leakage current be promoted to further increase, and accelerate Based varistor chip 1 generates heat, and will finally make 1 thermal breakdown of based varistor chip.But when heat reaches low melting point conjunction When golden 5 fusing-off temperature, disconnector action power dump is overheated, based varistor chip 1 is made to exit power grid before puncture short, Protection is achieved the purpose that.The program can be by the failure mode of most based varistor chip 1 from pernicious short-circuit mode The open circuit mode for influencing very little is converted to, the safety of SPD is greatly improved.

But still there is also some defects for the program, since the movement of overheat disconnector needs to be delayed by several seconds the time, and 1 leakage current of based varistor chip enters milliampere grade and starts accelerated deterioration adstante febre, and the defect inside porcelain body is very serious , there is the defect of partial chip seriously to arrive very short to the time of puncture short from starting to generate heat, heat also has little time to be transmitted to Hot disconnector melts low-melting alloy 5, and short circuit accident just has occurred.Another much situation is exactly when pressure-sensitive electricity Resistance ceramic chip 1 is deteriorated to when closing on accelerated deterioration area, and at this moment the leakage current of based varistor chip 1 is also less than milliampere grade, It can also maintain thermostabilization, additionally it is possible to work is maintained under the operating voltage of power grid, but its pressure sensitive voltage value at this time has compared Initial value when just starting to come into operation has apparent sharp fall, the anti-surge punching of based varistor chip 1 at this moment The ability hit is very fragile, an energy not counting it can be punctured or close to breakdown by too big surge, at this time it Puncture short speed is also that too fastly, overheat disconnector has little time response action and do not have protective effect.

Utility model content

The purpose of the utility model is to overcome the above-mentioned deficiencies in the presence of the prior art, provide a kind of varistor core Piece.

In order to achieve the above-mentioned object of the invention, the utility model provides following technical scheme:

A kind of voltage dependent resistor chip, including the first piezoresistive wafer, the second piezoresistive wafer and leading-out terminal, described first Piezoresistive wafer is connected with second piezoresistive wafer, forms a single port combinational circuit, wherein the first pressure-sensitive electricity The performance for hindering piece tolerance surge impact is higher than the performance of second piezoresistive wafer tolerance surge impact；

At least one in two leading-out terminals of the single port combinational circuit is the thermally conductive end of low thermal resistance, the low-heat Wherein one or two hindered in thermally conductive end and second piezoresistive wafer, first piezoresistive wafer is mutually hot simultaneously Coupling.In use, in the thermally conductive end connection overheat disconnector of the low thermal resistance.

The principle Analysis of the utility model is as follows:

It is the main channel for absorbing surge pulse by the series loop that the first piezoresistive wafer, the second piezoresistive wafer form, When not having surge pulse, varistor is in high-impedance state.When surge arrives, varistor is in low resistive state, surge energy Amount thus release by circuit.At this point, the voltage-limiting protection level of SPD is regarded as the residual voltage value of the first piezoresistive wafer and second pressure-sensitive The sum of residual voltage value of resistor disc.After surge disappears, piezoresistive wafer returns to high-impedance state.In order to ensure the member in surge channel Device degradation in tolerance surge impact capacity selection, will should follow the first piezoresistive wafer since the second piezoresistive wafer Tolerance be greater than the principle of the second piezoresistive wafer, significantly deteriorated with reaching when the second piezoresistive wafer, or even hit When wearing short circuit, the also substantially intact purpose of the first piezoresistive wafer.

The Analysis of Failure Mechanism of the utility model is as follows:

Since the first piezoresistive wafer anti-impulse performance is better than the second piezoresistive wafer, they are to be connected on surge again It absorbs in major loop, in practical applications, by the long-term impact of multiple surge, always the second piezoresistive wafer first starts bad Change, once deterioration to a certain extent, such as pressure sensitive voltage value be reduced to initial value 10% hereinafter, pressure-sensitive porcelain body internal structure just The case where greatly being destroyed, accelerated deterioration will be presented at this time, several less big surges can puncture it.Such as The pressure sensitive voltage value of first piezoresistive wafer is selected properly by fruit, so that the breakdown of concatenated second piezoresistive wafer or close breakdown When, the network voltage accessed just makes the first piezoresistive wafer enter accelerated deterioration area, flows through its electric current at more than ten milliamperes It is best between to 200 milliamperes, due to the first piezoresistive wafer anti-impulse performance it is stronger and almost without being destroyed, heat is steady It is qualitative, without breakdown, can to make low thermal resistance closer to not used new tile, the long period that can generate heat under above-mentioned electric current Thermally conductive end has more plenty of time that heat outflow is made its movement to overheat disconnector, cuts off circuit, makes the SPD safety of damage Ground exits power grid.It, will soon since overheat disconnector is generally provided with positioning indicator or electricity, sound, light warning device It is found, maintenance personal replaces in which can be convenient, and has achieved the purpose that safe handling.To substantially increase the peace of SPD Full property and reliability, the electrical equipment crash rate connected on route also will significantly reduce.

Undamaged piezoresistive wafer is compared with the piezoresistive wafer that serious pressure sensitive voltage value declines to a great extent is damaged, and this two Index difference is huge: first is that anti-impulse ability, is equally to be impacted with nominal current In 1 time, undamaged varistor Piece impact front and back pressure sensitive voltage value has almost no change, and pressure sensitive voltage value has deteriorated 30% piezoresistive wafer, then uses After In impacts 1 time, pressure sensitive voltage value can decline 10~30% or even 1 times again to be punctured.Besides thermostabilization Property, original new tile can be not breakdown in a short time by even 1~2 ampere of electric current of several hundred milliamperes, produces Raw heat is enough that the low-melting alloy fusing of disconnector will be overheated, and cuts off the power.And it is damaged serious piezoresistive wafer only Apply 200 milliamperes of electric currents below to be possible to puncture in 1~2 second, disconnector will be overheated by, which having little time at all, is heated to act Tripping.Therefore, this technology seeks to the gap of the performance of artificial manufacture two panels piezoresistive wafer tolerance surge impact, makes second Piezoresistive wafer deterioration breakdown when, the first piezoresistive wafer is substantially intact, using the thermal stability that it is not lowered substantially come Realize safety release.

Preferably, the first piezoresistive wafer electrode surface area of first piezoresistive wafer is greater than the described second pressure-sensitive electricity Hinder the second piezoresistive wafer electrode surface area of piece.Measuring piezoresistive wafer tolerance surge impact capacity has multinomial technical indicator, It is main to have: dash current I_imp, current waveform is 10/350 μ s；Maximum discharge current I_max, current waveform is 8/20 μ s；Energy Tolerance, current waveform are 2ms square wave；Rush of current stability is exactly with 8/20 μ s waveform nominal discharge current In repeated impacts The number etc. being resistant to.Under identical geometric dimension, by adjusting ceramic formula or technological parameter can optimize one of them or Multiple parameters index, but want General Promotion or relatively difficult.But these technical indicators are all and varistor plate electrode Area is directly proportional, therefore, as long as increasing the area of the first varistor plate electrode under the conditions of same process, so that it may ensure to be resistant to Surge impact capacity is comprehensively more than the second piezoresistive wafer.

Preferably, the nominal diameter of first piezoresistive wafer is nominal straight at least more than second piezoresistive wafer One sequence number of diameter.Since the diameter of flanking sequence number is than about 1.25 times, they are resistant to the parameter difference of surge impact capacity About 1.5 times, as long as the second piezoresistive wafer is designed to match with application environment, then the first piezoresistive wafer belongs to Redundancy Design, crash rate will be reduced than the second piezoresistive wafer in the order of magnitude, so that it may which guarantee makes the second piezoresistive wafer first Deterioration.

Preferably, the pressure sensitive voltage value of first piezoresistive wafer is the 0.75 of accessed network operation voltage peak To 0.85 times.It can guarantee that the network voltage accessed just makes in the case where the second piezoresistive wafer thorough puncture short First piezoresistive wafer enters accelerated deterioration area, and the electric current for flowing through it is best between more than ten milliamperes to 200 milliamperes, utilizes it Substantially the characteristics of thermal stability not being destroyed is closer to not used new tile, maintains longer fever time without being hit It wears, makes the thermally conductive end of low thermal resistance have more plenty of time that heat is output to overheat disconnector, make its action power dump.When When the pressure sensitive voltage value of one piezoresistive wafer is selected too low, the initial current for flowing through it is excessive, can shorten it and remain heat-staple Time.When selecting excessively high, the initial current for flowing through it is too small, is not enough to the process of Acceleration of starting deterioration.

Preferably, described is welded and connected on a second piezoresistive wafer electrode surface of second piezoresistive wafer Another electricity of one electrode surface of one piezoresistive wafer, second piezoresistive wafer and/or first piezoresistive wafer The thermally conductive end of low thermal resistance is welded on pole-face, also to realize the thermal coupling of element.

Preferably, the thermally conductive end of low thermal resistance with thermally conductive function has foot using excellent materials of heating conductions such as copper Enough big cross-sectional areas.And pyrotoxin varistor on piece is connected to using thermal couplings modes such as welding, and thermally conductive end away from The distance of pyrotoxin will as far as possible it is short, to obtain minimum thermal resistance, guarantee has enough heats to be transmitted to overheat disconnector.

Preferably, second piezoresistive wafer, the first piezoresistive wafer are packaged as a whole.

Preferably, first piezoresistive wafer is formed by two panels with the pressure-sensitive tile parallel connection of size.

Preferably, the impact resistance current rating of first piezoresistive wafer is higher than the resistance to of second piezoresistive wafer Dash current rated value.

Compared with prior art, the utility model has the beneficial effects that

The utility model is equipped with the absorption surge pulse being composed in series by the first piezoresistive wafer, the second piezoresistive wafer Main channel and reliability are better than the first piezoresistive wafer of the second piezoresistive wafer, first deteriorate mistake in the second piezoresistive wafer In the case where effect, the first substantially intact piezoresistive wafer can make the overheat disconnector action power dump of SPD, so that SPD is most Circuit is exited with open circuit mode eventually, relative to traditional short-circuit mode, greatly improves the safety of SPD, it is therefore prevented that short circuit Generated when breakdown smolder, arcing, even catching fire serious accident.Meanwhile overheating the state instruction that disconnector is equipped with Device or electricity, sound, light warning device, so that the SPD of damage will soon be found, maintenance personal carries out more in which can be convenient It changes, has achieved the purpose that safe handling, to substantially increase the safety and reliability of SPD, the electricity consumption connected on route is set Standby crash rate also will significantly reduce.

This technology is resistant to the gap of the performance of surge impact by artificially manufacture two panels piezoresistive wafer, makes the second pressure-sensitive electricity When hindering piece deterioration breakdown, the first piezoresistive wafer is substantially intact, and peace is realized using the thermal stability that it is not lowered substantially Full tripping.

Detailed description of the invention:

Fig. 1 is the schematic illustration of improvement plan described in background technique.

It is marked in Fig. 1: 1- based varistor chip, 2- scale copper electrode, 3- leading-out terminal, 4- elastic sheet metal, 5- Low-melting alloy.

Fig. 2 is a kind of schematic illustration of voltage dependent resistor chip described in the utility model.

Fig. 3 is a kind of part drawing of voltage dependent resistor chip described in the utility model embodiment 1.

Fig. 4 is a kind of assembling figure of voltage dependent resistor chip described in the utility model embodiment 1.

Fig. 5 is a kind of part drawing of voltage dependent resistor chip described in the utility model embodiment 2.

Fig. 6 is a kind of assembling figure of voltage dependent resistor chip described in the utility model embodiment 2.

It is marked in Fig. 2-Fig. 6: the first piezoresistive wafer of 1-, 11- the first piezoresistive wafer electrode surface, the second varistor of 2- Piece, 21- the second piezoresistive wafer electrode surface, 3- leading-out terminal.

Specific embodiment

The utility model is described in further detail below with reference to test example and specific embodiment.But it should not be by this The range for being interpreted as the above-mentioned theme of the utility model is only limitted to embodiment below, all to be realized based on the content of the present invention Technology belongs to the scope of the utility model.

Embodiment 1

As shown in figs 2-4, a kind of voltage dependent resistor chip, including the first piezoresistive wafer 1, the second piezoresistive wafer 2, draw Terminal 3 out, first piezoresistive wafer 1 are connected with second piezoresistive wafer 2, form a single port combinational circuit, Wherein, the performance that first piezoresistive wafer 1 is resistant to surge impact is higher than second piezoresistive wafer 2 tolerance surge impact Performance.

At least one in two leading-out terminals 3 of the single port combinational circuit is the thermally conductive end of low thermal resistance, described low The thermally conductive end of thermal resistance and 1 thermal coupling of the first piezoresistive wafer, in use, de- in the thermally conductive end connection overheat of the low thermal resistance From device.

11 area of the first piezoresistive wafer electrode surface of first piezoresistive wafer 1 is greater than second piezoresistive wafer 2 21 area of the second piezoresistive wafer electrode surface, the nominal diameter of first piezoresistive wafer 1 is at least more than second pressure One sequence number of nominal diameter of quick resistor disc 2, the pressure sensitive voltage value of first piezoresistive wafer 1 are accessed power grid works 0.75 to 0.85 times for making voltage peak.

Specific assembling mode are as follows:

First piezoresistive wafer 1 selects the pressure-sensitive tile 50k241 of the rectangle of nominal diameter 50mm, pressure sensitive voltage 240 Volt, maximum discharge current Imax are 60KA.Second piezoresistive wafer 2 selects the pressure-sensitive tile of square of nominal diameter 40mm 40k391, pressure sensitive voltage are 390 volts, and maximum discharge current Imax is 40KA.The parameter selection is suitble in 220 volts of common frequency power networks The operating temperature of work, overheat disconnector matched with its is 120 DEG C.

First pressure is welded and connected on one the second piezoresistive wafer electrode surface 21 of second piezoresistive wafer 2 One the first piezoresistive wafer electrode surface 11 of quick resistor disc 1, another first varistor of first piezoresistive wafer 1 It is also welded with the thermally conductive end of low thermal resistance on plate electrode face 11, welds a piece of bullet with low-melting alloy on the thermally conductive end of low thermal resistance Property sheet metal formed overheat disconnector.First piezoresistive wafer 1, the second piezoresistive wafer 2 are packaged as a whole.

Package unit is connected on 220 coucher frequency routes, and applies the surge repeated impacts of In=20KA, the 86th punching Disconnector movement is overheated after hitting, and is cooled to after room temperature and is tested the second piezoresistive wafer 2 and deteriorated breakdown, and the first varistor Piece 1 is still 238 volts, is remained unchanged substantially.

Embodiment 2

As shown in Fig. 5-Fig. 6, the present embodiment difference from example 1 is that, first piezoresistive wafer 1 is by two The pressure-sensitive tile (40K241x2) of square of piece nominal diameter 40mm is in parallel to be formed, and equivalent substitution is after parallel connection to reduce mounting surface Product, the parallel way are that the industry is the usual manner for reducing mounting area and using, and 1 voltage of the first piezoresistive wafer is 240 Volt, maximum discharge current Imax are 80KA.Second piezoresistive wafer 2 selects the pressure-sensitive tile of square of nominal diameter 40mm 40K391, pressure sensitive voltage are 390 volts, and maximum discharge current Imax is 40KA.Reference selection is suitble in 220 volts of common frequency power networks The operating temperature of work, overheat disconnector matched with its is 120 DEG C.

Package unit is connected on 220 coucher frequency routes, and applies the surge repeated impacts of In=20KA, the 101st time Disconnector movement is overheated after impact, is cooled to after room temperature and is tested the second piezoresistive wafer 2 and deteriorated breakdown, and the first pressure-sensitive electricity Hindering piece 1 is still 240 volts, is remained unchanged.

Above embodiments are only to illustrate the utility model and not limit technical solution described in the utility model, to the greatest extent Pipe this specification has been carried out detailed description to the utility model referring to above-mentioned each embodiment, but the utility model not office It is limited to above-mentioned specific embodiment, therefore any pair of the utility model is modified or equivalent replacement；And all do not depart from it is practical The technical solution and its improvement of novel spirit and scope, should all cover in the scope of the claims of the utility model.

Claims (8)

1. a kind of voltage dependent resistor chip, including the first piezoresistive wafer (1), the second piezoresistive wafer (2) and leading-out terminal (3), It is characterized in that, first piezoresistive wafer (1) is connected with second piezoresistive wafer (2), a single port group is formed Close circuit, wherein the performance of the first piezoresistive wafer (1) tolerance surge impact is higher than second piezoresistive wafer (2) It is resistant to the performance of surge impact；

At least one in two leading-out terminals (3) of the single port combinational circuit is the thermally conductive end of low thermal resistance, the low-heat Hinder thermally conductive end and first piezoresistive wafer (1), in second piezoresistive wafer (2) wherein one or two simultaneously It is thermally coupled to each other.

2. a kind of voltage dependent resistor chip according to claim 1, which is characterized in that first piezoresistive wafer (1) First piezoresistive wafer electrode surface (11) area is greater than the second piezoresistive wafer electrode surface of second piezoresistive wafer (2) (21) area.

3. a kind of voltage dependent resistor chip according to claim 1, which is characterized in that first piezoresistive wafer (1) One sequence number of nominal diameter of nominal diameter at least more than second piezoresistive wafer (2).

4. a kind of voltage dependent resistor chip according to claim 1, which is characterized in that first piezoresistive wafer (1) Pressure sensitive voltage value is 0.75 to 0.85 times of accessed network operation voltage peak.

5. a kind of voltage dependent resistor chip according to claim 1, which is characterized in that second piezoresistive wafer (2) A first pressure-sensitive electricity of first piezoresistive wafer (1) is welded and connected on one the second piezoresistive wafer electrode surface (21) It hinders plate electrode face (11), another the first piezoresistive wafer electrode surface (11) of first piezoresistive wafer (1) and/or described The thermally conductive end of low thermal resistance is also welded on another the second piezoresistive wafer electrode surface (21) of second piezoresistive wafer (2).

6. a kind of voltage dependent resistor chip according to claim 5, which is characterized in that second piezoresistive wafer (2), One piezoresistive wafer (1) is packaged as a whole.

7. a kind of voltage dependent resistor chip according to claim 5, which is characterized in that first piezoresistive wafer (1) by Two panels is formed with the pressure-sensitive tile parallel connection of size.

8. -7 any a kind of voltage dependent resistor chip according to claim 1, which is characterized in that first piezoresistive wafer (1) impact resistance current rating is higher than the impact resistance current rating of second piezoresistive wafer (2).