CN108598160A - 一种具有折叠型复合栅结构的igbt芯片 - Google Patents

一种具有折叠型复合栅结构的igbt芯片 Download PDF

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CN108598160A
CN108598160A CN201810148664.0A CN201810148664A CN108598160A CN 108598160 A CN108598160 A CN 108598160A CN 201810148664 A CN201810148664 A CN 201810148664A CN 108598160 A CN108598160 A CN 108598160A
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gate
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trench
igbt chip
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CN108598160B (zh
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刘国友
朱春林
朱利恒
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Zhuzhou CRRC Times Semiconductor Co Ltd
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Zhuzhou CRRC Times Electric Co Ltd
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Abstract

本发明公开了一种具有折叠型复合栅结构的IGBT芯片，包括若干复合栅单元，每一所述复合栅单元包括栅极区和位于所述栅极区两侧的有源区，其中，所述栅极区包括：在所述栅极区的指定位置向下刻蚀而成的至少一个沟槽，所述沟槽内设置有沟槽栅极；位于所述栅极区的表面上的平面栅极，所述平面栅极与沟槽栅极相连。所述有源区包括分别位于所述栅极区两侧的沟槽栅有源区和平面栅有源区，沟槽栅有源区和平面栅有源区均包括自下而上分布的N阱区、P阱区、P+掺杂区和N+掺杂扩散区。采用本发明可以大幅度提升IGBT芯片密度，并保留沟槽栅低通耗、高电流密度和平面栅宽安全工作区的特性。

Description

一种具有折叠型复合栅结构的IGBT芯片
技术领域
本发明涉及半导体器件技术领域，尤其涉及一种具有折叠型复合栅结构的IGBT芯片。
背景技术
自1980年前后IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)器件问世以来，由于其既具有双极晶体管通态压降低、电流密度大的特点，又具有MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor，金属-氧化物半导体场效应晶体管)管输入阻抗高、响应速度快等特点，被广泛应用于轨道交通、智能电网、工业变频及新能源开发等领域。
图1为现有技术中的具有平面栅结构的IGBT芯片的半元胞的剖面示意图。如图1所示，主要包括：衬底101、N阱区102、P阱区103、N+掺杂区104、P+掺杂区105、平面栅极106、栅氧化层107、钝化层108以及金属层109。图1所示的具有平面栅结构的IGBT芯片的主要优点是工艺制作简单，对设备要求低，而且平面栅耐压性能好，皮实度高，因而能用于工作环境比较恶劣的场所。但是，由于其沟道区在表面，沟道密度受到芯片表面积大小限制，导致IGBT芯片体内的电导调制效应较弱，导通压降较高。
图2为现有技术中的具有沟槽栅结构的IGBT芯片的半元胞的剖面示意图。如图2所示，主要包括：衬底201、N阱区202、P阱区203、N+掺杂区204、P+掺杂区205、沟槽栅极206、栅氧化层207、钝化层208以及金属层209。为了降低IGBT芯片的导通压降，采用如图2所示的沟槽栅结构取代平面栅结构。如图2所示，通过刻蚀工艺形成沟槽栅极，使得沟道进入衬底体内，实现将沟道由横向转化为纵向，从而实现一维电流通道，有效消除平面栅沟道中的JFET效应，同时缩小了元胞尺寸，使沟道密度不再受芯片表面积限制，大大提高元胞密度从而大幅度提升芯片电流密度。但是，随着沟槽栅密度的增加，芯片饱和电流过大，弱化了芯片的短路性能，从而影响了芯片的安全工作区。
图3为现有技术中的具有陪栅和沟槽栅结构的IGBT芯片的半元胞的剖面示意图。如图3所示，主要包括：衬底301、N阱区302、P阱区303、N+掺杂区304、P+掺杂区305、沟槽栅极306、陪栅307、栅氧化层308、钝化层309以及金属层310。为了平衡短路性能和电流密度之间的折中关系，采用如图3所示的陪栅和沟槽栅极共存的结构取代如图2所示的沟槽栅结构。
图2和图3中的沟槽栅极的底部对IGBT芯片的阻压能力有一定的限制。其与图1所示的具有平面栅结构的IGBT芯片相比，在提升IGBT芯片性能的同时也牺牲了平面栅部分耐压和皮实的性能。
发明内容
针对上述技术问题，本发明提供了一种具有折叠型复合栅结构的IGBT芯片，包括晶圆基片和形成于所述晶圆基片正面的若干个依次排列的复合栅单元，每一所述复合栅单元包括栅极区和位于所述栅极区两侧的有源区；
所述栅极区包括：
在所述栅极区的指定位置向下刻蚀形成的沟槽，所述沟槽内设置有沟槽栅极；
位于所述栅极区的表面上的平面栅极，所述平面栅极与沟槽栅极相连；
以及隔离所述沟槽栅极和平面栅极与所述晶圆基片的栅氧化层，和覆盖所述平面栅极外表面的隔离保护层；
所述有源区包括位于所述栅极区两侧的沟槽栅有源区和平面栅有源区，其中，所述沟槽栅有源区和平面栅有源区均包括自下而上分布的N阱区、P阱区、P+掺杂区和N+掺杂扩散区。
在一个实施例中，所述平面栅极和沟槽栅极的材料均为多晶硅，所述平面栅极的多晶硅和沟槽栅极的多晶硅相连。
在一个实施例中，所述P阱区位于其所属的所述有源区下方和所述平面栅极中与其所属的有源区相接触的边缘的下方的区域；
所述N阱区位于其对应的所述P阱区下方且与该P阱区相接触；
所述N+掺杂扩散区是位于其对应的所述P阱区上方且与该P阱区相接触的N+掺杂区经刻蚀而保留在所述平面栅极下方的部分，所述N+掺杂扩散区的底部高于其对应的P阱区经过此次刻蚀而暴露出的表面；
所述P+掺杂区位于其对应的所述P阱区经过此次刻蚀而暴露出的表面内，所述P+掺杂区的侧部通过扩散与其对应的所述N+掺杂扩散区相连；
其中，所述沟槽栅有源区的N阱区、P阱区以及N+掺杂扩散区的侧部止于所述沟槽栅极侧壁的栅氧化层。
在一个实施例中，还包括覆盖所述隔离保护层、所述沟槽栅有源区的P+掺杂区和所述平面栅有源区的金属层。
在一个实施例中，所述N+掺杂扩散区与所述金属层相连。
在一个实施例中，每两个所述复合栅单元以镜像对称的方式组成一个元胞。
在一个实施例中，所述元胞为六角形元胞结构，并且多个所述元胞以蜂窝状分布在所述晶圆基片上。
在一个实施例中，所述元胞为方形元胞结构，并且多个所述元胞矩阵式地分布在所述晶圆基片上。
在一个实施例中，所述元胞为条形元胞结构，并且多个所述元胞并排地分布在所述晶圆基片上。
在一个实施例中，所述IGBT芯片还包括形成在所述晶圆基片背面的背部结构，所述背部结构为穿通型、非穿通型或软穿通型。
与现有技术相比，本发明的一个或多个实施例可以具有如下优点：
1)在本发明中，平面栅极和沟槽栅极共存于同一芯片，相当于在具有平面栅结构的IGBT芯片的薄弱区域引入沟槽栅，或者在具有沟槽栅结构的IGBT芯片的非工作区引入平面栅，可以发挥平面栅和沟槽栅的优点并减弱各自的弱点，从而大幅度提升IGBT芯片密度，并保留沟槽栅低通耗、高电流密度和平面栅宽安全工作区的特性。
2)在本发明中，平面栅的沟道分布在晶圆表面，沟槽栅的沟道垂直于晶圆表面分布在晶圆体内，平面栅的多晶硅和沟槽栅的多晶硅连接在一起，共同作为本发明复合栅结构的呈折叠状的栅极。
本发明的其它特征和优点将在随后的说明书中阐述，并且部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。在附图中：
图1示出了现有技术中的具有平面栅结构的IGBT芯片的半元胞的剖面示意图；
图2示出了现有技术中的具有沟槽栅结构的IGBT芯片的半元胞的剖面示意图；
图3示出了现有技术中的具有陪栅和沟槽栅结构的IGBT芯片的半元胞的剖面示意图；
图4示出了本发明实施例中的具有折叠型复合栅结构的IGBT芯片六角形元胞的俯视示意图；
图5示出了本发明实施例中的具有折叠型复合栅结构的IGBT芯片沿A-A’方向的元胞剖面图；
图6示出了本发明实施例中的具有折叠型复合栅结构的IGBT芯片方形元胞的俯视示意图；
图7示出了本发明实施例中的具有折叠型复合栅结构的IGBT芯片条形元胞的俯视示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
图4为本发明实施例中的具有折叠型复合栅结构的IGBT芯片六角形元胞的俯视示意图。如图4所示，每个元胞410为六角形元胞结构，并且多个元胞以蜂窝状分布在晶圆基片上。其中，每个元胞410包括栅极区401和位于栅极区401两侧的沟槽栅有源区402和平面栅有源区403。
为了更清楚地说明图4所示的IGBT芯片的结构，下面以图4所示的IGBT芯片沿A-A’方向的元胞剖面图为例进行详细说明。
图5为本发明实施例中IGBT芯片沿A-A’方向的元胞剖面图。如图5所示，一个元胞主要包括两个镜像对称的复合栅单元。由于图5中的两个复合栅单元结构对称，因此下面仅以右边的复合栅单元为例来说明元胞的具体结构。
如图5所示，复合栅单元包括栅极区401和位于栅极区401两侧的沟槽栅有源区402和平面栅有源区403。其中，栅极区401包括沟槽栅极510、平面栅极520、栅氧化层531和隔离保护层530。有源区包括沟槽栅有源区402和平面栅有源区403，且沟槽栅有源区402和平面栅有源区403通过相同的工艺步骤同时实现。其中，沟槽栅有源区402和平面栅有源区403均包括从下到上分布的N阱区540、P阱区550、P+掺杂区560和N+掺杂扩散区570。
具体地，沟槽栅极510位于栅极区401的一侧，于栅极区401的指定位置向下刻蚀而成的沟槽内。平面栅极520位于栅极区401的表面。其中，平面栅极520与沟槽栅极510相连。
在一个优选的实施例中，沟槽栅极510和平面栅极520是通过向栅极区401的表面沉积多晶硅同时形成的。其中，平面栅极520的多晶硅与沟槽栅极510的多晶硅连接在一起，平面栅极520的沟道分布在晶圆基片500表面，沟槽栅极510的沟道垂直于晶圆基片500表面且分布在晶圆基片500内，共同作为复合栅单元的呈折叠状的栅极。
栅氧化层531隔离沟槽栅极510和平面栅极520与晶圆基片500。隔离保护层530覆盖平面栅极520外表面，用于有效隔离平面栅极520与用作源极的金属层580。栅氧化层531和隔离保护层530通过不同的工艺步骤而形成。隔离保护层530的厚度大于栅氧化层531的厚度。
沟槽栅有源区402的P阱区550位于沟槽栅有源区402下方和平面栅极520中与沟槽栅有源区402相接触的边缘的下方。沟槽栅有源区402的P阱区550的侧部止于沟槽侧壁的栅氧化层531。平面栅有源区403的P阱区550位于平面栅有源区403下方和平面栅极520中与平面栅有源区403相接触的边缘的下方。平面栅有源区403的P阱区550与平面栅极520下方的栅氧化层531相接触，其中位于栅极区下方的P阱区550呈弧形。
N阱区540位于其对应的P阱区550下方且与该P阱区550相接触。沟槽栅有源区402的N阱区540的侧部止于沟槽侧壁的栅氧化层531。平面栅有源区403的N阱区540包围P阱区550，且与平面栅极520下方的栅氧化层531相接触。
N+掺杂扩散区570是通过刻蚀位于其对应的P阱区550上方且与该P阱区550相接触的N+掺杂扩散区而保留在栅极区401下方的部分。沟槽栅有源区402的N+掺杂扩散区570止于沟槽侧壁的栅氧化层531。平面栅有源区403的N+掺杂扩散区570与平面栅极520下方的栅氧化层531相接触。为了完全刻蚀有源区下方的N+掺杂扩散区，优选地，N+掺杂扩散区570的底部高于P阱区550经过此次刻蚀而暴露出的表面。需要说明的是，如果能够保证完全刻蚀有源区下方的N+掺杂区，N+掺杂扩散区570的底部也可以与P阱区550经过此次刻蚀而暴露出的表面处于同一平面。
P+掺杂区560位于其对应的P阱区550经过此次刻蚀而暴露出的表面内，P+掺杂区560的侧部通过扩散与其对应的N+掺杂扩散区570相连。
需要说明的是，通过合理设置N阱区540、P阱区550以及N+掺杂扩散区570的掺杂剂量和结深，使得沟槽栅极510的沟道和平面栅极520的沟道的阈值电压相同，从而能够使沟槽栅极510的沟道和平面栅极520的沟道同时开启和同时关断。在本实施例中，N阱区540中注入的N型杂质的剂量小于N+掺杂扩散区570中注入的N型杂质的剂量。P阱区550中注入的P型杂质的剂量小于P+掺杂区560中注入的P型杂质的剂量。
优选地，复合栅单元还包括覆盖隔离保护层530、沟槽栅有源区402的P+掺杂区560和平面栅有源区403的P+掺杂区560的金属层580。N+掺杂扩散区570与金属层580相接触。可选地，在栅极区隔离保护层30上表面与金属层570之间还可以包括其他膜层结构，此处不作具体限定。在本实施例中，在有源区P+掺杂区560上覆盖有金属层580，并通过高温退火(400～450度)以使P+掺杂区560与金属层570之间形成欧姆接触。
需要注意的是，晶圆基片500背面可以采用穿通型结构、非穿通型结构或软穿通型结构。
可选地，本发明第一实施例中还可以采用如图6所示的方形元胞或如图7所示的条形元胞结构来实现，使平面栅极和沟槽栅极共存于同一芯片。具体地，如图6所示，每个元胞610为方形元胞结构，并且多个元胞610矩阵式地排布在晶圆基片上。每个元胞610包括栅极区601和位于栅极区601两侧的沟槽栅有源区602和平面栅有源区603。如图7所示，每个元胞710为条形元胞结构，并且多个元胞710并排地分布在晶圆基片上。每个元胞710包括栅极区701和位于栅极区701两侧的沟槽栅有源区702和平面栅有源区703。
在本实施例中，平面栅极和沟槽栅极共存于同一芯片，相当于在具有平面栅结构的IGBT芯片的薄弱区域引入沟槽栅，或者在具有沟槽栅结构的IGBT芯片的非工作区引入平面栅，可以发挥平面栅结构和沟槽栅结构的优点并减弱各自的弱点，从而大幅度提升IGBT芯片密度，并保留沟槽栅结构低通耗、高电流密度和平面栅结构宽安全工作区的特性。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (10)

1.一种具有折叠型复合栅结构的IGBT芯片，其特征在于，包括晶圆基片和形成于所述晶圆基片正面的若干个依次排列的复合栅单元，每一所述复合栅单元包括栅极区和位于所述栅极区两侧的有源区；
所述栅极区包括：
在所述栅极区的指定位置向下刻蚀形成的沟槽，所述沟槽内设置有沟槽栅极；
位于所述栅极区的表面上的平面栅极，所述平面栅极与沟槽栅极相连；
以及隔离所述沟槽栅极和平面栅极与所述晶圆基片的栅氧化层，和覆盖所述平面栅极外表面的隔离保护层；
所述有源区包括位于所述栅极区两侧的沟槽栅有源区和平面栅有源区，其中，所述沟槽栅有源区和平面栅有源区均包括自下而上分布的N阱区、P阱区、P+掺杂区和N+掺杂扩散区。
2.根据权利要求1所述的IGBT芯片，其特征在于，所述平面栅极和沟槽栅极的材料均为多晶硅，所述平面栅极的多晶硅和沟槽栅极的多晶硅相连。
3.根据权利要求1所述的IGBT芯片，其特征在于，
所述P阱区位于其所属的所述有源区下方和所述平面栅极中与其所属的有源区相接触的边缘的下方的区域；
所述N阱区位于其对应的所述P阱区下方且与该P阱区相接触；
所述N+掺杂扩散区是位于其对应的所述P阱区上方且与该P阱区相接触的N+掺杂区经刻蚀而保留在所述平面栅极下方的部分，所述N+掺杂扩散区的底部高于其对应的P阱区经过此次刻蚀而暴露出的表面；
所述P+掺杂区位于其对应的所述P阱区经过此次刻蚀而暴露出的表面内，所述P+掺杂区的侧部通过扩散与其对应的所述N+掺杂扩散区相连；
其中，所述沟槽栅有源区的N阱区、P阱区以及N+掺杂扩散区的侧部止于所述沟槽栅极侧壁的栅氧化层。
4.根据权利要求3所述的IGBT芯片，其特征在于，还包括覆盖所述隔离保护层、所述沟槽栅有源区的P+掺杂区和所述平面栅有源区的金属层。
5.根据权利要求4所述的IGBT芯片，其特征在于，所述N+掺杂扩散区与所述金属层相连。
6.根据权利要求1所述的IGBT芯片，其特征在于，每两个所述复合栅单元以镜像对称的方式组成一个元胞。
7.根据权利要求6所述的IGBT芯片，其特征在于，所述元胞为六角形元胞结构，并且多个所述元胞以蜂窝状分布在所述晶圆基片上。
8.根据权利要求6所述的IGBT芯片，其特征在于，所述元胞为方形元胞结构，并且多个所述元胞矩阵式地分布在所述晶圆基片上。
9.根据权利要求6所述的IGBT芯片，其特征在于，所述元胞为条形元胞结构，并且多个所述元胞并排地分布在所述晶圆基片上。
10.根据权利要求1-9中任一项所述的IGBT芯片，其特征在于，所述IGBT芯片还包括形成在所述晶圆基片背面的背部结构，所述背部结构为穿通型、非穿通型或软穿通型。
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