CN108598076A - A kind of adjustable ESD protective device of trigger voltage based on Ge-Si heterojunction technique - Google Patents
A kind of adjustable ESD protective device of trigger voltage based on Ge-Si heterojunction technique Download PDFInfo
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- CN108598076A CN108598076A CN201810314659.2A CN201810314659A CN108598076A CN 108598076 A CN108598076 A CN 108598076A CN 201810314659 A CN201810314659 A CN 201810314659A CN 108598076 A CN108598076 A CN 108598076A
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- 230000001681 protective effect Effects 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 title claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- 238000002955 isolation Methods 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 11
- 239000013078 crystal Substances 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 125000006850 spacer group Chemical group 0.000 claims description 8
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 5
- 230000004224 protection Effects 0.000 abstract description 19
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 238000007667 floating Methods 0.000 abstract description 10
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 20
- 238000013461 design Methods 0.000 description 15
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
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- H01L27/0259—
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- H01L29/1008—
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- H01L29/735—
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- H01L29/737—
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- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
The invention belongs to integrated circuit electrostatic discharges (Electrostatic Discharge, ESD) to protect field, specifically provide a kind of adjustable ESD protective device of the trigger voltage based on Ge-Si heterojunction technique；The present invention is based on HBT device architectures; it is designed using base stage floating, as ESD protective device in use, emitter (cathode) ground connection of HBT; base stage floating, collector (anode) connect the input/output terminal (I/O) or power end of chip；HBT devices are designed using base stage floating in the present invention, make the avalanche breakdown voltage that triggering HBT devices are opened by existing nonadjustable BVCBOBecome adjustable open base emitter junction avalanche breakdown voltage BVCEO, junction area can be emitted by adjusting and effectively adjust trigger voltage；Also, due to base stage floating, the chip area of esd protection circuit can be reduced, when used in parallel especially with multiple HBT devices, more particularly to effectively reduce the chip area of esd protection circuit.
Description
Technical field
The invention belongs to integrated circuit electrostatic discharges (Electrostatic Discharge, ESD) to protect field, specifically
It is related to a kind of adjustable ESD protective device of trigger voltage being based on germanium silicon (SiGe) Heterojunction.
Background technology
Electrostatic and static discharge are a kind of phenomenons being widely present in nature, it can cause integrated circuit device sternly
The integrity problem of weight.In current IC industry, as constantly reducing for device size is continuous with chip-scale
Increase, influence of the electrostatic to integrated circuit is more and more significant.Since the ESD protections between different process have huge difference, make
The electrostatic protection for obtaining IC products is more difficult and complicated.
The place that esd event occurs is very extensive, is likely to will produce ESD during transport, encapsulation, use, from
And integrated circuit device is made to fail.This not only adds costs, waste resource, also bring product reliability problem, so
The research of ESD protections seems most important.For the research of ESD protections, we be usually input/output port and power supply it
Between be added esd clamp bit location, effect be：1. discharge ESD electric currents, 2. lose esd pulse voltage part clamper to circuit minimum
Voltage is imitated hereinafter, more than operating voltage.This requires clamping units enough fast opening speed and suitable trigger voltage.
The design and optimization that ESD protective device is realized in a particular semiconductor technique first have to protect in view of ESD
Protect the required working range of device, i.e. ESD design windows (as shown in Figure 1).As shown in the I-V curve of Fig. 1, defines and protected
The normal operation region of unit is protected, the normal working voltage of protected location is designated as V=0V to V=VDD(supply voltage)；
The maximum voltage BV that can bear under from supply voltage VDD to protected location internal core circuit normal conditionOXIt is exactly that ESD is protected
The voltage request of the design window of device is protected, the trigger voltage of ESD protective device will be less than BVOX, it is ensured that it is unloaded in ESD protective device
Protected location internal core circuit is not damaged before amplification electric current, meanwhile, the clamp voltage of ESD protective device is higher than VDD,
To avoid generation latch-up.The ESD design windows of a typical ESD protective device as shown in Fig. 1, wherein Vt1 and
It1 is the trigger voltage and trigger current of ESD protective device, and Vh and Ih are the maintenance voltage and maintenance electric current of ESD protective device,
Vt2 and It2 is the secondary breakdown voltage and secondary breakdown current of ESD protective device.
Heterojunction Bipolar Transistors (HBT) technique can control electronics by changing the energy gap of semi-conducting material
The migration and distribution in hole pair.Compared with simple silicon (Si) material, the working performance of SiGe Heterojunction Bipolar Transistors (HBT)
Want high more, while sige material has extraordinary compatibility with Si techniques, as long as carrying out improvement slightly to Si techniques,
It can obtain the good more devices of performance ratio traditional Si processing performance.So it is new to explore ESD protection of the design based on SiGe techniques
Structure is conducive to improve the reliability of the integrated circuit based on SiGe techniques.
Under SiGe techniques, generally use SiGe Heterojunction Bipolar Transistors HBT device architectures carry out ESD protections.
Traditional single HBT device architectures are as shown in Fig. 2, include：
P-type silicon substrate 110；
A N-shaped buried layer 120 is formed on the p-type silicon substrate 110；
A n-type area 130 is formed on the N-shaped buried layer 120；
130 both sides of the n-type area form a N-shaped heavily doped region 141 and a N-shaped heavily doped region 142, and two weights
Doped region is connected with the collector of HBT；
Shallow trench isolation region there are one being set near the height junction face that the N-shaped heavily doped region 141 is formed with n-type area 130
150；
Shallow trench isolation region there are one being set near the height junction face that the N-shaped heavily doped region 142 is formed with n-type area 130
250；
It is described from shallow trench isolation region 150 to forming a p-type SiGe on the silicon face of the n-type area 130 of shallow trench isolation region 250
Area 160, and the SiGe on shallow trench isolation region 150 and 250 is connected with the base stage of HBT；
A N-shaped is formed on 160 surface of p-type SiGe between shallow trench isolation region 150 and shallow trench isolation region 250
Heavily doped polysilicon area 170, and the multi-crystal silicon area is connected with the emitter of HBT；
170 both sides of N-shaped multi-crystal silicon area form an oxide sidewall spacers 180 and an oxide sidewall spacers 280.
When the device as ESD protection locations in use, base stage and the emitter ground connection of HBT, collector connects and protected
The input and output port (I/O) of circuit or power port (VDD)；As the I/O for coming chip for positive esd pulse relative to ground
When port or power port, the collector junction of HBT is reverse-biased, emitter junction zero bias；When esd pulse voltage is more than the base stage collector junction of HBT
Avalanche breakdown voltage BVCBOWhen, a large amount of electron hole pair generates near the collector junction of HBT；Wherein, electronics passes through n-type area
130, N-shaped buried layer 120, N-shaped heavily doped region 141 and 142 flow out collector, and hole is then flowed out by base stage；Work as base current
Sufficiently large, emitter junction positively biased, HBT devices are in magnifying state, and a large amount of electric current can be connected.In this way, ESD electric currents just pass through
HBT devices are released.
In actual esd protection circuit, in order to realize larger current drain ability, multiple HBT devices are generally used
In parallel method realizes higher ESD robustness.It is illustrated in figure 3 the multiple SiGe Heterojunction Bipolar Transistors of a tradition
The schematic diagram of HBT device architecture parallel connections, structure include：
P-type silicon substrate 110；
A N-shaped buried layer 120 is formed on the p-type silicon substrate 110；
A n-type area 130 is formed on the N-shaped buried layer 120；
130 both sides of the n-type area form a N-shaped heavily doped region 141 and a N-shaped heavily doped region 142, and two weights
Doped region is connected with the collector of HBT；
Between the height junction face that the N-shaped heavily doped region 141 and N-shaped heavily doped region 142 and n-type area 130 are formed
Equipped with N+1 shallow trench isolation region 150,250,350 ..., N50 and (N+1) 50；(N=1,2,3 ... ..., k, k are positive integer)
A p-type is formed on 130 silicon face of n-type area of (N+1) 50 from shallow trench isolation region N50 to shallow trench isolation region
SiGe 160, and the SiGe on shallow trench isolation region N50 and (N+1) 50 is connected with the base stage of HBT；
It is formed on 160 surface of p-type SiGe between shallow trench isolation region N50 and shallow trench isolation region (N+1) 50
One N-shaped multi-crystal silicon area N70, and the multi-crystal silicon area is connected with the emitter of HBT；
The N-shaped polysilicon layer area both sides N70 form an oxide sidewall spacers N80 and an oxide sidewall spacers (N+1) 80.
When the structure is used for esd protection circuit, base stage and the emitter ground connection of HBT, collector connects by the defeated of protection circuit
Enter the output port (I/O) or power port, operation principle is identical as the single HBT device architectures of tradition shown in FIG. 1, triggering
Voltage is by BVCBOIt determines.
But in a specific semiconductor technology, due to base stage collector junction avalanche breakdown voltage BVCBOIt is non-adjustable, it leads
It causes the trigger voltage of above-mentioned traditional SiGe hetero-junctions HBT to be fixed as constant, cannot be adjusted.However, in design ESD protections
When unit, the required working range of ESD protection locations, i.e. ESD design windows (as shown in Figure 1) are considered；For difference
Protected location, the ESD design windows of internal core circuit are often different, this has resulted in the difference of same chip
Uniquely it is necessary to have the ESD devices of different trigger voltages for the ESD design windows of port to protect different ports, this is just
Challenge is brought to the design of ESD protection locations.
Invention content
It is an object of the invention in view of the above-mentioned problems, a kind of trigger voltage based on Ge-Si heterojunction technique of offer is adjustable
ESD protective device；The structure can not only realize that the trigger voltage of ESD protective device is adjustable by the adjustment of domain, also
The chip area of esd protection circuit can be reduced.
To achieve the above object, the technical solution adopted by the present invention is：
A kind of adjustable ESD protective device of trigger voltage based on Ge-Si heterojunction technique, which is characterized in that including：
One the first conduction type silicon substrate,
Second of conduction type buried layer is formed on the first described conduction type silicon substrate,
Second of conductivity regions are formed on second of conduction type buried layer,
Second of conductivity regions both sides respectively form second of conduction type heavily doped region, second of conductive-type
A shallow trench isolation region, and two second are respectively formed at height junction face between type heavily doped region and second of conductivity regions
Kind conduction type heavily doped region is connected with ESD protective device anode,
The first conduction type germanium silicon area is formed on described two shallow trench isolation regions and second of conductivity regions surface,
Formed on the first described conduction type germanium silicon area surface second of the conduction type heavily doped polysilicon area K, K >=
1, each second of conduction type heavily doped polysilicon area both sides are respectively formed oxide sidewall spacers, and each second of conduction type is heavily doped
Miscellaneous multi-crystal silicon area is connected with the cathode of ESD protective device.
The beneficial effects of the present invention are：
The present invention provides a kind of adjustable ESD protective device of the trigger voltage based on Ge-Si heterojunction technique, is protected as ESD
Device is protected in use, the emitter (cathode) of HBT is grounded, base stage floating, collector (anode) meets the input/output terminal (I/ of chip
) or power end O；In the present invention HBT devices using base stage floating design, make triggering HBT devices open avalanche breakdown voltage by
Existing nonadjustable BVCBOBecome adjustable open base emitter junction avalanche breakdown voltage BVCEO, can be by adjusting emitter junction
Area effectively adjusts trigger voltage；Also, due to base stage floating, the chip area of esd protection circuit can be reduced, is especially adopted
When used in parallel with multiple HBT devices, more particularly to effectively reduce the chip area of esd protection circuit.
Description of the drawings
Fig. 1 is typical ESD design windows.
Fig. 2 is traditional single HBT device architecture schematic diagrames.
Fig. 3 is the schematic diagram of the multiple SiGe Heterojunction Bipolar Transistors HBT device parallel-connection structures of tradition.
Fig. 4 is the adjustable ESD protective device structural schematic diagram of the trigger voltage based on Ge-Si heterojunction technique of the present invention.
Specific implementation mode
The present invention is described in detail with reference to the accompanying drawings and examples.
The present embodiment provides a kind of adjustable ESD protective device of the trigger voltage based on Ge-Si heterojunction technique, structures
As shown in figure 4, constituted using the adjustable HBT devices parallel connection of multiple trigger voltages, including：
P-type silicon substrate 110；
A N-shaped buried layer 120 is formed on the p-type silicon substrate 110；
A n-type area 130 is formed on the N-shaped buried layer 120；
130 both sides of the n-type area form a N-shaped heavily doped region 141 and a N-shaped heavily doped region 142, and two weights
Doped region is connected with the collector of HBT；
Shallow-trench isolation there are one being set near the height junction face that the N-shaped heavily doped region 141 and n-type area 130 are formed
Area 150；
Shallow-trench isolation there are one being set near the height junction face that the N-shaped heavily doped region 142 and n-type area 130 are formed
Area 250；
A p-type SiGe is formed on 130 silicon face of n-type area from shallow trench isolation region 150 to shallow trench isolation region 250
160；
K N-shaped multi-crystal silicon area 170,270,370 ... ..., N70, and the K are formed on 160 surface of p-type SiGe
A multi-crystal silicon area is connected with the emitter of HBT, (K is positive integer)；
The N-shaped polysilicon layer area both sides N70 form an oxide sidewall spacers N80 and an oxide sidewall spacers (N+1) 80.
From operation principle, the adjustable ESD protective device of the above-mentioned trigger voltage based on Ge-Si heterojunction technique, as
For ESD protective device in use, the emitter of HBT is grounded, base stage floating, collector connects the input/output terminal (I/O) or electricity of chip
Source.When being that positive esd pulse comes the input/output port or power port of chip relative to ground, n-type region 130 and p
The PN junction that type SiGe 160 is formed is reverse-biased, the PN junction positively biased that p-type SiGe 160 is formed with N-shaped polysilicon region N70, N-shaped
The PN junction that buried layer area 120 and p-substrate floor 110 are formed is reverse-biased, when the open base that esd pulse voltage is more than HBT devices emits
Tie avalanche breakdown voltage BVCEOWhen, a large amount of electron hole pair generates near the base stage of HBT and collector interface to be formed
Current channel, ESD electric currents are just released by the HBT devices；The base stage floating design of HBT devices, makes triggering HBT in the present invention
Device open avalanche breakdown voltage by conventional method nonadjustable BVCBOBecome adjustable BVCEO。
Known BVCEOSize be that can be realized by adjusting the transmitting junction area of HBT；When HBT transmitting junction areas reduce
When, the common base direct-current short circuit current amplification factor α of HBT increases, so that BVCEOReduce；In this way, the ESD protective device
Trigger voltage Vt1 is reduced；Identical reason can increase touching for the ESD protective device by increasing the area of HBT emitter junctions
Power generation pressure Vt1；Therefore, the design based on HBT base stage floatings emits junction area by adjusting and may be implemented to adjust ESD protections
The purpose of device trigger voltage Vt1, to meet different ESD design window requirements.
Meanwhile the multiple SiGe Heterojunction Bipolar Transistors HBT devices parallel-connection structures (as shown in Figure 3) of tradition are compared, this
The adjustable ESD protective device of a kind of trigger voltage based on Ge-Si heterojunction technique that invention proposes can be not brought up base stage company
Line need not be isolated between Heterojunction Bipolar Transistors in parallel, can effectively save chip area.
The above description is merely a specific embodiment, any feature disclosed in this specification, except non-specifically
Narration, can be replaced by other alternative features that are equivalent or have similar purpose；Disclosed all features or all sides
Method or in the process the step of, other than mutually exclusive feature and/or step, can be combined in any way.
Claims (1)
1. a kind of adjustable ESD protective device of trigger voltage based on Ge-Si heterojunction technique, which is characterized in that including：
One the first conduction type silicon substrate,
Second of conduction type buried layer is formed on the first described conduction type silicon substrate,
Second of conductivity regions are formed on second of conduction type buried layer,
Second of conductivity regions both sides respectively form second of conduction type heavily doped region, second of conduction type weight
It is respectively formed a shallow trench isolation region at height junction face between doped region and second of conductivity regions, and two are led for second
Electric type heavily doped region is connected with ESD protective device anode,
The first conduction type germanium silicon area is formed on described two shallow trench isolation regions and second of conductivity regions surface,
K second conduction type heavily doped polysilicon area, K >=1 are formed on the first described conduction type germanium silicon area surface, often
A second of conduction type heavily doped polysilicon area both sides are respectively formed oxide sidewall spacers, and each second of conduction type heavy doping is more
Crystal silicon area is connected with the cathode of ESD protective device.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810314659.2A CN108598076A (en) | 2018-04-10 | 2018-04-10 | A kind of adjustable ESD protective device of trigger voltage based on Ge-Si heterojunction technique |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810314659.2A CN108598076A (en) | 2018-04-10 | 2018-04-10 | A kind of adjustable ESD protective device of trigger voltage based on Ge-Si heterojunction technique |
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| CN108598076A true CN108598076A (en) | 2018-09-28 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1354517A (en) * | 2000-11-20 | 2002-06-19 | 国际商业机器公司 | Channel limited silicon-germanium static discharge diode network |
| US20070070564A1 (en) * | 2005-09-19 | 2007-03-29 | Yintat Ma | Esd protection circuits for rf input pins |
| US20090032814A1 (en) * | 2007-08-02 | 2009-02-05 | Vladislav Vashchenko | SiGe DIAC ESD protection structure |
| CN105374816A (en) * | 2015-12-23 | 2016-03-02 | 电子科技大学 | Bidirectional ESD protection device based on germanium-silicon heterojunction proces |
-
2018
- 2018-04-10 CN CN201810314659.2A patent/CN108598076A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1354517A (en) * | 2000-11-20 | 2002-06-19 | 国际商业机器公司 | Channel limited silicon-germanium static discharge diode network |
| US20070070564A1 (en) * | 2005-09-19 | 2007-03-29 | Yintat Ma | Esd protection circuits for rf input pins |
| US20090032814A1 (en) * | 2007-08-02 | 2009-02-05 | Vladislav Vashchenko | SiGe DIAC ESD protection structure |
| CN105374816A (en) * | 2015-12-23 | 2016-03-02 | 电子科技大学 | Bidirectional ESD protection device based on germanium-silicon heterojunction proces |
Non-Patent Citations (2)
| Title |
|---|
| 严向阳，淮永进，孙茂友: "InGaP异质结双极晶体管ESD特性研究", 《微电子学》 * |
| 王邦麟，苏庆，金峰，李平梁，徐向明: "SiGe工艺中HBT结构ESD保护电路设计", 《半导体技术》 * |
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Application publication date: 20180928 |