CN108538913B - 用于纳米线半导体器件的内间隔 - Google Patents

用于纳米线半导体器件的内间隔 Download PDF

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CN108538913B
CN108538913B CN201810175021.5A CN201810175021A CN108538913B CN 108538913 B CN108538913 B CN 108538913B CN 201810175021 A CN201810175021 A CN 201810175021A CN 108538913 B CN108538913 B CN 108538913B
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nanowire
gap
dielectric material
dielectric
sacrificial
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CN108538913A (zh
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K·沃斯汀
H·梅尔腾斯
L·维特斯
A·西卡维
堀口直人
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Interuniversitair Microelektronica Centrum vzw IMEC
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Abstract

一种在纳米线之间形成内间隔的方法(100):提供(110)鳍片,所述鳍片包含交替的牺牲材料(4)的层与纳米线材料(3)的层的堆叠;选择性地除去(130)部分牺牲材料(4),从而形成凹陷(5);将电介质材料(10)沉积(140)到凹陷(5)中,形成在凹陷(5)中的电介质材料和在凹陷(5)外的多余的电介质材料,其中在各凹陷(5)中的电介质材料中保持缝隙(11);使用第一蚀刻剂除去(150)多余的电介质材料;使用第二蚀刻剂扩大(160)缝隙(11),形成间隙(12),使得余下的电介质材料仍然覆盖牺牲材料并部分覆盖纳米线材料,使得外端可接近;在外端上生长(170)电极材料,使得从相邻外端生长的电极材料合并,从而覆盖间隙(12)。

Description

用于纳米线半导体器件的内间隔
技术领域
本发明涉及纳米线半导体器件如纳米线FET的领域。本发明更具体涉及在半导体器件中的纳米线之间形成内间隔的方法,以及包含内间隔的纳米线半导体器件。本发明更具体涉及用于栅极全包围器件的内间隔的形成。
发明背景
形成堆叠纳米线是降低半导体器件特征尺寸的重要步骤。
必须解决的一个重要问题是减小由于晶体管栅极和源漏区之间的重叠引起的寄生电容。
为了最大程度地减小寄生电容,形成内部间隔必须是纳米线集成方案中的一个集成部分。
但是,形成内间隔可能是耗费工艺和/或材料的。因此,形成内间隔的方法还有改善的空间。
发明内容
本发明实施方式的一个目的是提供在半导体器件的纳米线之间形成内间隔的良好方法。
上述目的是通过本发明所述的一种方法和器件实现的。
在第一方面,本发明的实施方式涉及在半导体器件的纳米线之间形成内间隔的方法。该方法包括以下步骤:
-提供至少一个鳍片,所述鳍片包含交替的牺牲材料层与纳米线材料层的堆叠,
-选择性地除去纳米线材料之间的部分牺牲材料,从而在纳米线材料层之间形成凹陷,
-将电介质材料沉积到凹陷中,形成在凹陷中的电介质材料和在凹陷外的多余的电介质材料,其中在各凹陷中的电介质材料中保持缝隙,
-使用第一蚀刻剂除去多余的电介质材料,
-然后,使用第二蚀刻剂扩大缝隙,形成间隙,使得余下的电介质材料仍然覆盖牺牲材料并部分覆盖纳米线材料,
-其中,在扩大缝隙后,纳米线材料的外端是可接近的,
-在纳米线材料的外端上生长电极材料,使得从相邻外端生长的电极材料合并,从而覆盖间隙,其中内间隔包含间隙。
在本发明的一些实施方式中,对第二蚀刻剂进行选择,使得该第二蚀刻剂能比第一蚀刻剂更好地穿透到缝隙中。
当电介质材料在凹陷中生长时,从凹陷的两面都生长的电介质材料的表面生长,直到它们彼此触碰,或者直到在电介质材料的表面上它们相互之间的间距小于3nm,或者甚至小于1nm,或者甚至小于0.5nm,或者甚至小于0.1nm。该触碰区域或间距减小的区域称为缝隙。在本发明的一些实施方式中,在保形沉积以及非保形沉积的情况中,都形成该缝隙。在保形沉积的情况中,朝向彼此生长的表面在整个长度上触碰,但是可仍然被蚀刻剂穿透。在此情况中,能够被蚀刻剂穿透的缝隙称为接缝。
本发明实施方式的一个优点在于形成具有低k值的内间隔。可获得低k值是因为内间隔包含间隙。所述间隙可例如是空气间隙或真空间隙。
本发明实施方式的优点在于,使用第一蚀刻处理除去多余的电介质材料,但是不会扩大缝隙。因此,使用第一蚀刻处理,其在缝隙中的穿透性略差于用于扩大缝隙的第二蚀刻处理。由此带来的优点是在除去多余的电介质材料(除去纳米线材料之间部分牺牲材料后形成的不在凹陷中的电介质材料)时不会除去全部电介质材料。
本发明实施方式的优点在于,使用第二蚀刻处理来扩大缝隙。对该处理加以选择,使得其在缝隙中的蚀刻比第一蚀刻处理中更有效。该处理能够在电介质材料中蚀刻开口,在抵靠纳米线材料的侧壁上以及抵靠牺牲材料的底壁上留下电介质材料。由于蚀刻是从缝隙内进行的,所以仍然有电介质材料留在抵靠纳米线材料的侧壁上。
在缝隙扩大后,使电极材料(例如源极或漏极材料)在纳米线材料的外端上生长。由此,电极材料开始在纳米线材料的除去了电介质材料的这些部分上生长。因此,有利的是,并非全部电介质材料都从侧壁上除去。电介质材料开始生长的位置距离底部越远,由电极材料和余下的电介质材料形成的间隙越大。纳米线之间的各内间隔均包含这种间隙。这种间隙可以是空气间隙。本发明实施方式的优点在于,通过使用两种不同的蚀刻处理来除去电介质材料可以增大这种间隙的体积。一种蚀刻处理用于除去多余的电介质材料(在凹陷外和纳米线材料外端上的材料),另一种蚀刻处理用于扩大缝隙。
在本发明的一些实施方式中,伪栅极部分地覆盖所提供的鳍片的层堆叠,所述方法包括通过除去牺牲材料和紧邻伪栅极的纳米线材料来在至少一个鳍片中提供沟槽,其中,纳米线材料之间的牺牲材料从所述沟槽开始被选择性地除去。
在本发明的一些实施方式中,使用保形填充来沉积电介质材料。
在本发明的一些实施方式中,使用非保形填充来沉积电介质材料。
本发明一些实施方式的一个优点在于,在非保形沉积电介质材料后,在电介质材料中可能存在气泡。可使用扩大缝隙的第二蚀刻处理接近并加宽该气泡。
在本发明的一些实施方式中,提供至少一个鳍片包括提供其中纳米线材料是Ge且牺牲层材料是Si1-xGex的鳍片。
在本发明的一些实施方式中,提供至少一个鳍片包括提供其中Si1-xGex中Ge含量低于80%的鳍片。
本发明实施方式的优点在于,在牺牲材料和纳米线材料之间存在最小差异。这种差异是选择性蚀刻所需要的。
在本发明的一些实施方式中,提供至少一个鳍片包括提供其中纳米线材料是Si且牺牲层材料是Si1-xGex的鳍片。
在本发明的一些实施方式中,提供至少一个鳍片包括提供其中Si1-xGex中Ge含量最高达50%的鳍片。
本发明实施方式的一个优点在于,通过降低Ge含量,可以增加偏置(bias)。
在本发明的一些实施方式中,沉积电介质材料包括沉积氮化物。
在本发明的一些实施方式中,沉积电介质材料包括沉积氧化物。
在第二方面,本发明的实施方式涉及纳米线晶体管堆叠。各纳米线晶体管包含纳米线,在纳米线端部的源极或漏极,控制栅极,以及在相邻晶体管的纳米线之间和在源极或漏极与栅极之间的内间隔。内间隔包含空气间隙和电介质材料,其中电介质材料存在于栅极和空气间隙之间,以及/或者存在于纳米线和空气间隙之间,其中电介质材料的厚度小于3nm,其中源极或漏极材料从纳米线材料的端部外延生长,形成纳米线之间的桥,并封闭空气间隙。
本发明实施方式的优点在于,纳米线晶体管的内间隔包含空气间隙。这种空气间隙的优点在于,可以实现低k值的内间隔。本发明实施方式的优点在于,在空气间隙侧的源极或漏极材料上不存在电介质材料,因为源极或漏极材料是从纳米线材料的端部外延生长,形成纳米线之间的桥以封闭空气间隙。因为在空气间隙侧的源极或漏极材料上不存在电介质材料,所以空气间隙的尺寸比存在电介质材料的情况中的尺寸大。间隙越大,内间隔的k值越低。
在本发明的一些实施方式中,纳米线包含Ge。
在本发明的一些实施方式中,纳米线包含Si。
本发明特定和优选的方面在所附独立和从属权利要求中阐述。可以将从属权利要求中的特征与独立权利要求中的特征以及其它从属权利要求中的特征进行适当组合,而并不仅限于权利要求书中明确所述的情况。
本发明的这些和其它方面将参考下文所述的实施方式披露并阐明。
附图简要说明
图1显示依据本发明实施方式的在鳍片中设置沟槽后得到的鳍片的纵向截面示意图。
图2示意性地显示依据本发明实施方式的方法的步骤。
图3显示纳米线堆叠的示意图,该纳米线堆叠具有在纳米线材料的层之间的凹陷以及通过非保形沉积而沉积在这些凹陷中的电介质材料,其中在电介质中存在液滴形状的空气间隙。
图4显示依据本发明实施方式的使用一种方法形成间隙,在该方法中,第一蚀刻处理与第二蚀刻处理相同。
图5显示依据本发明实施方式的仅在顶部部分不含电介质材料的纳米线上的EPI生长。
图6显示依据本发明实施方式的纳米线材料堆叠的示意图,在该纳米线材料堆叠中,交替的层堆叠的顶层是纳米线材料层。
图7显示依据本发明实施方式的纳米线材料堆叠的示意图,在该纳米线材料堆叠中,交替的层堆叠的顶层是牺牲材料层。
图8显示依据本发明实施方式的方法的流程图。
权利要求书中的任何引用符号不应理解为限制本发明的范围。
在不同的图中,相同的附图标记表示相同或类似的元件。
示例性实施方式的详细描述
将就具体实施方式并参照某些附图对本发明进行描述,但本发明并不受此限制,仅由权利要求书限定。描述的附图仅是说明性的且是非限制性的。在附图中,一些元素的尺寸可能被夸大且未按比例尺绘画以用于说明目的。所述尺寸和相对尺寸不与本发明实践的实际减小相对应。
在说明书和权利要求书中的术语第一、第二等用来区别类似的元件,而不一定是用来描述时间、空间、等级顺序或任何其它方式的顺序。应理解,如此使用的术语在合适情况下可互换使用,本发明所述的实施方式能够按照本文所述或说明的顺序以外的其它顺序进行操作。
此外,在说明书和权利要求书中,术语顶、之下等用于描述目的,而不一定用于描述相对位置。应理解,如此使用的术语在合适情况下可互换使用,本发明所述的实施方式能够按照本文所述或说明的取向以外的其它取向进行操作。
应注意,权利要求中使用的术语“包含”不应解释为被限制为其后列出的部分,其不排除其它元件或步骤。因此,其应被理解为指出所述特征、集成、步骤或组分的存在,但这并不排除一种或多种其它特征、集成、步骤或组分或其组合的存在或添加。因此,表述“包括部件A和B的装置”的范围不应被限制为所述装置仅由组件A和B构成。其表示对于本发明,所述装置的相关组件仅为A和B。
说明书中提及的“一个实施方式”或“一种实施方式”是指连同实施方式描述的具体特征、结构或特性包括在本发明的至少一个实施方式中。因此,在说明书中各处出现的短语“在一个实施方式中”或“在一种实施方式中”不一定全部指同一个实施方式,但可能全部都指同一个实施方式。此外,具体特征、结构或特性可以任何合适方式在一个或多个实施方式中组合,这对于本领域普通技术人员而言是显而易见的。
类似地,应理解,在本发明的示例性实施方式的描述中,本发明的不同特征有时组合成一个单一实施方式、特征或其描述,这是为了简化公开内容并帮助理解本发明的一个或多个不同方面。然而,本公开内容中的方法不应被理解为反映一项发明,请求保护的本发明需要比各权利要求中明确引用的具有更多的特征。并且,如同所附权利要求所反映的那样,发明方面包括的特征可能会少于前述公开的一个单一实施方式的全部特征。因此,具体说明之后的权利要求将被明确地纳入该具体说明,并且各权利要求本身基于本发明独立的实施方式。
此外,当本文所述的一些实施方式包括一些但不包括其它实施方式中所包括的其它特征时,不同实施方式的特征的组合应意在包括在本发明范围内,并且形成不同的实施方式,这应被本领域技术人员所理解。例如,在之后的权利要求中,所请求保护的任何实施方式可以任何组合形式使用。
本文的描述中阐述了众多的具体细节。然而应理解,本发明的实施方式可不用这些具体细节进行实施。在其它情况中,为了不混淆对该说明书的理解,没有详细描述众所周知的方法、步骤和技术。
在本发明的实施方式中,提及纳米线材料,就是提及制成纳米线的材料。
在第一方面,本发明的实施方式涉及在半导体器件的纳米线之间形成内间隔的方法100。
该方法100包括提供110至少一个鳍片,所述鳍片包含交替的牺牲材料4的层与纳米线材料3的层的堆叠,在本发明的一些实施方式中,伪栅极7可以部分地覆盖至少一个鳍片的层堆叠。
图1显示在鳍片中提供120沟槽后得到的鳍片的纵向截面示意图。该鳍片包含牺牲材料4的层和纳米线材料3的层交替排列的堆叠。在该例子中,伪栅极7部分地覆盖至少一个鳍片的层堆叠。在伪栅极7和鳍片的层堆叠之间,存在伪电介质8。紧邻伪栅极7,存在伪间隔物1。在该鳍片中,紧邻伪间隔物1在鳍片中形成沟槽2。该沟槽与纳米线材料层正交。
依据本发明实施方式的方法的步骤如图2的示意图所示,并在下文中进行说明。这些步骤的流程图如图8所示。
该方法包括选择性地除去130紧邻伪栅极7的纳米线材料3之间的部分牺牲材料4,从而在纳米线材料3的层之间形成凹陷5。
选择性地除去130牺牲材料可在于至少一个鳍片中设置120沟槽2之后,通过除去紧邻伪栅极7的牺牲材料4和纳米线材料3来进行。
在本发明的一些实施方式中,纳米线材料之间的牺牲材料4是从沟槽2开始被选择性地除去130。
在纳米线材料3的层之间形成凹陷5之后,电介质材料10被沉积140到通过选择性除去牺牲层材料而产生的凹陷5中。由此形成在凹陷5内的电介质材料以及在凹陷5外和在纳米线材料3外端上的多余的电介质材料。在各凹陷5的高度上的电介质材料中保持缝隙11。当沉积电介质材料时,该缝隙(例如接缝)11形成于纳米线之间。
可使用保形沉积进行电介质材料10的沉积。在沉积过程中,电介质材料10的表面从两侧生长,直到凹陷被填充。例如,可使用等离子体增强原子层沉积(PEALD)沉积氧化硅。
还可以使用非保形沉积进行电介质材料10的沉积。在使用非保形沉积法沉积140电介质材料后,在凹陷5的电介质材料中可保持存在气泡15(液滴形状的体积)。其示例如图3的示意图所示。可通过控制沉积特征以及凹陷5的纵横比来控制气泡的尺寸和形式。例如,可使用化学气相沉积(CVD)或使用等离子体增强化学气相沉积来进行非保形沉积。在使用第一蚀刻剂除去150多余的电介质材料之后,缝隙11被扩大160,并且气泡15也被扩大,形成间隙12。
在本发明的一些实施方式中,电介质可以例如是氮化物或氧化物。例如,可沉积氮化硅或氧化硅。可沉积的电介质材料的其它例子是氧化硅碳(SiCO)和SiN。可使用可流动化学气相沉积(FCVD)进行氧化物的非保形沉积。
在本发明的一些实施方式中,使用第一蚀刻处理除去150多余的电介质材料。在本发明的一些实施方式中,对第一蚀刻处理进行选择,使得该处理不会或不容易穿透密封。第一蚀刻处理可以例如是气相NF3/NH3基化学蚀刻。在氧化硅蚀刻以及氮化硅蚀刻的情形中可以使用该类型的蚀刻。这种气相NF3/NH3基蚀刻处理的例子可以例如是AMAT(应用材料(Applied Materials))SiConiTM.SiConiTM是等离子体辅助的干蚀刻方法。取决于需要被蚀刻的电介质材料,可以使用不同的方案。目前,TEL(东京电子有限公司(Tokyo ElectronLimited))和SCREEN(斯科睿半导体科技研究有限公司(SCREEN semiconductor solutionsCo.,Ltd.))也具有类似的可用系统。气相NF3/NH3基化学蚀刻见述于“先进原位预-Ni硅化物(Siconi)在65清洁以解决NiSix模块的缺陷(Advanced in situ pre-Ni silicide(Siconi)cleaning at65nm to resolve defects in NiSix modules)”,Yang等,出版于2010年1月7日,美国真空学会(Journal of Vacuum Science&Technology B,Nanotechnology and Microelectronics:Materials,Processing,Measurement,andPhenomena 28,56(2010);识别码(doi):10.1116/1.3271334)。该文献通过引用结合于此。在本发明的一些实施方式中,还可以例如使用一些含F的各向同性等离子体进行第一蚀刻处理。
在除去多余的电介质材料之后,缝隙(例如接缝)11扩大160,形成间隙12。使用第二蚀刻处理进行该扩大操作。在本发明的一些实施方式中,对第二蚀刻处理进行选择,使得该第二蚀刻处理能比第一蚀刻处理更好地穿透到缝隙(例如接缝)11中。
当电介质材料是氧化硅时,第二蚀刻处理可以是湿氧化物蚀刻。第二蚀刻处理例如可包含HF,其容易穿透到缝隙11中(与第一蚀刻处理相比)。也可以使用BHF溶液作为第二蚀刻剂。
当电介质材料是氮化物时,第二蚀刻处理可例如包含磷酸,或者例如可包含HF水溶液。
在本发明的一些实施方式中,第一蚀刻处理可以与第二蚀刻处理相同。第一和第二蚀刻处理可例如是气相NF3/NH3蚀刻(例如SICONI)。在此情况中,形成的间隙12可具有图4所示的V形截面。在此情况中,在紧邻牺牲线的角落中存在多余的电介质。这说明具有比第一蚀刻剂更好地穿透到缝隙中的第二蚀刻剂是有利的,因为可以产生体积更大的间隙12。
在扩大缝隙后,形成间隙12。该间隙12可完全由第二蚀刻处理产生,或者液滴形状的空气间隙在电介质沉积后可能已经存在于电介质中。存在于电介质中的液滴形状的间隙可通过扩大缝隙而被打开。这种液滴形状的空气间隙可能在非保形沉积电介质材料后存在。这种气泡可通过在气泡顶部扩大缝隙而被打开。
缝隙应该被扩大,而一些电介质材料应该被保留。对第二蚀刻处理加以控制,使得余下的电介质材料仍然覆盖牺牲材料并部分覆盖纳米线材料。间隙应该尽可能宽,因为这样导致低k值。余下的电介质材料应该尽可能薄。厚度应该足以使得氧化物能承受RMG(替代金属栅极)工艺。电介质材料确保纳米线能够以纳米线材料与牺牲层之间的高选择性在RMG模块中被释放。
本发明实施方式的优点在于,通过使用两种不同的回蚀步骤来使电介质材料中存在缝隙(例如接缝)。第一步骤150,其中多余的电介质材料被除去,以及第二步骤160,其中缝隙被扩大。在第二步骤中,可使用比第一步骤中所用的蚀刻剂更容易穿透到缝隙中的蚀刻剂。通过使用这些不同的蚀刻剂可以产生更大的间隙。通过使用第一蚀刻剂,可以防止在第一步骤中除去全部电介质。通过使用第二蚀刻剂,凹陷中的电介质可从缝隙内开始被除去。
在第一蚀刻处理和第二蚀刻处理之后,纳米线的外端不含电介质材料。因此,它们是可接近的(accessible),源极或漏极材料可以在纳米线材料3的外端上生长170,使得从相邻外端生长的源极或漏极材料合并。由此,间隙12被一侧上的漏极或源极材料和另一侧上的余下电介质封闭。内间隔包含间隙12和余下的电介质材料。
在本发明的一些实施方式中,不含电介质材料的纳米线材料外端包含一部分的侧壁。这种情况如图2所示,其中凹陷距离d表明纳米线材料的侧壁被暴露了多少。在本发明的另一些实施方式中,不含电介质材料的纳米线材料外端仅包含纳米线材料的顶部。其示例如图5所示。在所示的两个例子中,EPI仅仅从暴露的纳米线表面生长。因此,电介质凹陷d决定了源/漏极形状。当d不是零时(如图2所示),生长可以例如是钻石形生长,或者当不存在电介质凹陷时(如图5所示),生长可以是金字塔形生长。如图5所示,与钻石形生长相比,金字塔形生长导致空气间隙减小,EPI中的缺陷增多。因此,有利的是具有非零的凹陷d。优选地,凹陷应使得EPI生长为钻石形生长。
本发明实施方式的优点在于,源极或漏极材料从纳米线材料的外端以小切面方式外延生长(例如,钻石形形式)。EPI从相邻的外端生长并合并。这样可以在两个纳米线3之间形成桥,留下空气间隙内间隔。空气间隙例如可通过外延S/D(例如SiGe或Si:P)的各向异性生长而被封闭。
本发明实施方式的优点在于,在扩大缝隙后,至少一些氧化物材料保留在角落、底部以及纳米线的至少一部分侧壁上。S/D从纳米线材料的外端生长。因为一些氧化物材料留在角落中并且留在纳米线材料至少一部分侧壁上,S/D大多从纳米线顶部生长。因此,可以获得较大的空气间隙内间隔。事实上,如果在角落中不存在电介质材料,S/D将从角落开始生长,导致更小的空气间隙,或者甚至完全不产生空气间隙。
在本发明的一些实施方式中,在源极或漏极材料生长后,纳米线被释放,伪栅极被真栅极代替。
纳米线材料3之间的部分牺牲材料4的选择性去除130可以是各向同性或各向异性的。
各向异性蚀刻将导致内间隔/栅极界面的歪斜形状。歪斜形状是由于各向异性蚀刻导致的,其中牺牲材料不是沿着直面蚀刻,而是形成歪斜形状的表面。
各向同性蚀刻将产生内间隔/栅极界面的直轮廓,因此在沉积电介质后形成更清楚限定的缝隙。例如,在保形沉积电介质材料后,接缝11保留,它在电介质材料10中延伸深入到凹陷5中。原因在于在使用各向同性蚀刻进行选择性除去130后牺牲材料的表面是平坦表面。因此,电介质的保形沉积从平坦表面开始,得到清楚限定的接缝。
在第二方面,本发明的实施方式涉及纳米线晶体管堆叠。各纳米线晶体管包含纳米线3,在纳米线3端部的源极或漏极14(例如,在纳米线一端的源极,在纳米线另一端的漏极),栅极37,以及在纳米线3之间和在源极或漏极14与栅极37之间的内间隔。内间隔包含空气间隙12和电介质材料(10),其中电介质材料(10)存在于栅极(37)和空气间隙(12)之间,以及/或者存在于纳米线(3)和空气间隙(12)之间,其中电介质材料(10)的厚度小于3nm,或者甚至小于2nm,或者甚至小于1nm。电介质的厚度越小,间隙越大,内间隔的k值越低。
电介质的厚度应该厚到足以在纳米线释放过程中停止选择性蚀刻。在考虑Si纳米线并使用HCl(g)作为选择性蚀刻处理的情况中,1nm电介质(例如氧化物或氮化物)足以停止选择性蚀刻处理,因为HCl(g)对电介质(例如氧化物或氮化物)的选择性极高。而在碱性溶液用于选择性蚀刻/纳米线释放的情况中,1nm电介质(例如氧化物)足以释放SiGe纳米线。在Ge纳米线的情况中,可能需要电介质具有更大的厚度,因为选择性蚀刻剂对电介质(例如氧化物)的选择性更有限。在此情况中,在使用第二蚀刻剂扩大缝隙后,应该保持2nm(或更厚)。
例如,空气间隙12的尺寸(最大尺寸)可以为3–15nm或5–10nm。空气间隙的高度可以例如为5-15nm(例如12nm)。空气间隙的宽度可以例如为5-10nm(例如6nm)。在本发明的一些实施方式中,纳米线的截面不必需是圆形的。还可以是例如矩形(例如片状形状的纳米线)。在此情况中,空气间隙的宽度可以较大。宽度可以最大为20nm,或者甚至最大为30nm,或者甚至最大为40nm。例如,宽度可以为12nm。在本发明的一些实施方式中,空气间隙的深度,即从S/D到栅极的方向上尺寸,可以例如为5-10nm,或者甚至为3-15nm。
这种纳米线晶体管堆叠的两个示例性实施方式如图6和图7所示。在这些图中,左侧的图显示包含牺牲材料4的层与纳米线材料3的层交替排列的堆叠的原始鳍片,右侧的图显示其中纳米线晶体管的内间隔包含空气间隙12的纳米线晶体管堆叠。
在图6中,交替层堆叠的顶层是纳米线材料3的层。在图7中,该层是牺牲材料4的层。在图6和图7的左图中,伪栅极7均部分地覆盖鳍片的层堆叠。在伪栅极7和鳍片的层堆叠之间,存在伪电介质8。紧邻伪栅极7,存在伪间隔物1。
在纳米线晶体管堆叠30中,各纳米线晶体管包含纳米线3、电极源或漏极14、栅极37和包含空气间隙12的内间隔。左图中的伪栅极7和牺牲材料层4被栅极37代替。在栅极37和纳米线3之间,存在电介质38。而且,源/漏极14存在于纳米线3的外端。在鳍片顶部,间隔物31紧邻栅极37,层间电介质(ILD0)39紧邻该间隔物。内间隔位于相邻晶体管的纳米线3之间以及S/D14与栅极37之间。
在图6中,顶层由纳米线材料3制成,因此该例子中的伪间隔物1决定了顶部纳米线的栅极长度。在该例子中,其它纳米线的长度由内间隔12决定。
在图7中,顶层由牺牲材料4制成,因此内间隔12决定了所有纳米线3的栅极长度。
在本发明的一些实施方式中,纳米线材料可以例如包含Si,或Ge,或SiGe,III-V化合物材料。这种III-V化合物材料可以是二元的,例如GaAs或GaP,或者可以是三元的,例如InGaAs。
在本发明的一些实施方式中,纳米线材料是Si,牺牲层材料是Si1-xGex。Si1-xGex中的Ge含量优选在20%-50%之间,可以最高达50%。
在本发明的一些实施方式中,纳米线材料是Ge,牺牲层材料是Si1-xGex。Si1-xGex中的Ge含量低于80%,例如在50%-75%之间。这种差异是选择性蚀刻所需要的。

Claims (17)

1.一种在半导体器件的纳米线之间形成内间隔的方法,该方法包括:
提供至少一个鳍片,所述鳍片包含交替的牺牲材料层与纳米线材料层的堆叠;
选择性地除去纳米线材料之间的部分牺牲材料,从而在纳米线材料层之间形成多个凹陷;
将电介质材料沉积到各凹陷中,形成在凹陷中的电介质材料和在凹陷外的多余的电介质材料,其中在各凹陷中的电介质材料中保持缝隙;
使用第一蚀刻剂除去多余的电介质材料;
使用第二蚀刻剂扩大缝隙来形成间隙,使得余下的电介质材料仍然覆盖牺牲材料并至少部分地覆盖纳米线材料,其中,在形成间隙后,纳米线的外端是可接近的;和
在纳米线材料的外端上生长电极材料,使得从相邻外端生长的电极材料合并,从而使间隙被一侧上的电极材料和另一侧上的余下的电介质材料封闭,其中内间隔包含间隙。
2.如权利要求1所述的方法,其特征在于,对第二蚀刻剂进行选择,使得该第二蚀刻剂能比第一蚀刻剂更好地穿透到缝隙中。
3.如权利要求1所述的方法,其特征在于,伪栅极部分地覆盖所提供的鳍片的层堆叠,所述方法还包括:
通过除去牺牲材料和紧邻伪栅极的纳米线材料来在至少一个鳍片中提供沟槽。
4.如权利要求3所述的方法,其特征在于,纳米线材料之间的牺牲材料从所述沟槽开始被选择性地除去。
5.如权利要求3所述的方法,其特征在于,在伪栅极和至少一个鳍片的层堆叠之间存在伪电介质。
6.如权利要求1所述的方法,其特征在于,纳米线材料的外端包含纳米线材料的侧壁的一部分,其中凹陷距离d表明在外端中包含了多少纳米线材料的侧壁。
7.如权利要求6所述的方法,其特征在于,电极材料的生长是钻石形生长。
8.如权利要求1所述的方法,其特征在于,使用保形填充沉积电介质材料。
9.如权利要求1所述的方法,其特征在于,使用非保形填充沉积电介质材料。
10.如权利要求1所述的方法,其特征在于,提供至少一个鳍片包括提供纳米线材料是Ge且牺牲层材料是Si1-xGex的鳍片。
11.如权利要求10所述的方法,其特征在于,Si1-xGex的Ge含量低于80%。
12.如权利要求1所述的方法,其特征在于,提供至少一个鳍片包括提供纳米线材料是Si且牺牲材料是Si1-xGex的鳍片。
13.如权利要求12所述的方法,其特征在于,Si1-xGex的Ge含量最高达50%。
14.如权利要求1所述的方法,其特征在于,沉积电介质材料包括沉积氮化物。
15.如权利要求1所述的方法,其特征在于,沉积电介质材料包括沉积氧化物。
16.如权利要求1所述的方法,其特征在于,部分牺牲材料的选择性去除是各向同性的。
17.如权利要求1所述的方法,其特征在于,间隙是空气间隙或真空中的一种。
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