CN108511406A - 具有增强的散热性的电子组件 - Google Patents
具有增强的散热性的电子组件 Download PDFInfo
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- CN108511406A CN108511406A CN201810024632.XA CN201810024632A CN108511406A CN 108511406 A CN108511406 A CN 108511406A CN 201810024632 A CN201810024632 A CN 201810024632A CN 108511406 A CN108511406 A CN 108511406A
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- Prior art keywords
- electronic building
- semiconductor devices
- building brick
- metal
- bonding layer
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- 239000002184 metal Substances 0.000 claims abstract description 126
- 239000004065 semiconductor Substances 0.000 claims abstract description 118
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 57
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Abstract
根据本公开的一个方面,一种电子组件包括半导体器件,该半导体器件具有第一侧以及与第一侧相反的第二侧。第一侧具有第一导电垫。第二侧具有第一金属表面。第一基板(例如引线框架)通过第一金属结合层结合到第一导电垫。第二基板(例如热沉电路板)通过第二金属结合层结合到第一金属表面。在一种构造中,第二金属结合层由例如焊料和铜构成。
Description
技术领域
本公开涉及具有增强的散热性的电子组件。
背景技术
某些现有技术使用粘合漆包线来将半导体器件的引线连接到半导体封装或基板。然而,由于粘合漆包线的连接方式,半导体器件的散热、工作温度范围或最高工作温度可能受到限制。一些半导体器件可能使用碳化硅,这是由于碳化硅的优越的功率处理能力。然而,就提供足够的散热性而言,碳化硅在半导体封装方面面临挑战。因此,需要具有增强的散热性的电子组件。
发明内容
根据本公开的一个方面,一种电子组件包括半导体器件,所述半导体器件具有第一侧以及与第一侧相反的第二侧。所述第一侧具有第一导电垫。所述第二侧具有第一金属表面。第一基板(例如引线框架)通过第一金属结合层结合到第一导电垫。第二基板(例如热沉电路板)通过第二金属结合层结合到至少第一金属表面。在一种构造中,所述第二金属结合层由例如焊料和铜构成。
附图说明
图1是表示本公开的电子组件的剖面的框图的一个实施例。
图2是沿着图3A中的参考线2-2观察到的电子组件的剖面的另一个实施例。
图3A是根据图2的半导体器件的一个说明性实施例的第一侧(例如上侧)的平面图。
图3B是与图2及图3A一致的半导体器件的一个说明性实施例的第二侧(例如下侧)的平面图。
图4是电子组件的替代性实施例的剖面,该替代性实施例的特征在于半导体器件和热沉之间的附加基板(例如电路板)。
图5是适用于电子组件的多个说明性引线框架的平面图。
图6是用于制造具有增强的散热性的组件的方法的流程图的一个实施例。
图7是第二基板的平面图,第二基板例如是热沉,其中,导电构件上设有焊膏,用以与一个或多个半导体器件上的相应的导电垫配合。
图8是多个半导体器件的平面图,其中,这些半导体器件各自的导电垫上设有焊膏。
图9是完全组装的电子组件的一个实施例的平面图。
图10是沿着图11A中的参考线10-10观察到的电子组件的剖面的一个替代性实施例。
图11A是根据图10的半导体器件的一个说明性实施例的第一侧(例如上侧)的平面图。
图11B是与图10及图11A一致的半导体器件的一个说明性实施例的第二侧(例如下侧)的平面图。
在任何一组附图中,相同的附图标记表示相同的元件、特征、过程或步骤。
具体实施方式
图1是表示本公开的电子组件11的一个实施例的剖面的框图。根据图1,电子组件11包括半导体器件14,半导体器件14具有第一侧42以及与第一侧42相反的第二侧44。第一侧42具有第一导电垫34。第二侧44具有第一金属表面22。第一基板10(例如引线框架)通过第一金属结合层12结合到第一导电垫34。第二基板18(例如热沉或热沉电路板)通过第二金属结合层16结合到第一金属表面22。
第一结合层12提供第一导电垫34与第一基板10(例如一个或多个引线框架)之间的电连接和机械连接。替代性地,第一结合层12为对应的第一导电垫34、对应的第二导电垫38和对应的第三导电垫40提供通向引线框架的不同端子的一组相应的电连接和机械连接。
第二接合层16提供第一金属表面22与第二基板18(例如热沉或热沉电路板)之间的电连接和机械连接。替代性地,第二结合层16提供第一金属表面22、第二金属表面23和第二基板(例如热沉或热沉电路板)之间的电连接和机械连接。
在一个实施例中,第一结合层12由焊料构成;第二结合层16由焊料或者焊料和铜材料两者构成。然而,在替代性实施例中,第一结合层12由焊料和铜材料两者构成。
在第一结合层12、第二结合层16或者第一结合层12和第二结合层16两者中,铜含量(例如铜粒)能够增强半导体器件14的散热性。此外,铜含量可以提高一个或多个结合层(12、16)的热机械强度。例如,在一个实施例中,(第一结合层12中的)铜使第一结合层12的同系温度降低,由此提高第一结合层12和第一导电垫34之间的结合的机械强度(例如剪切、拉伸和/或压缩强度)。类似地,在一个实施例中,(第二结合层16中的)铜使第二结合层16的同系温度降低,由此提高第二结合层16和第一金属表面22之间的结合的机械强度(例如剪切、拉伸和/或压缩强度)。
在一种构造中,半导体器件14具有第一热膨胀系数(CTE),而第一基板10(例如引线框架)或第二基板18(例如热沉)具有第二热膨胀系数(CTE),并且其中,第一结合层12或第二结合层16中的铜分别减小第一CTE和第二CTE之间的失配(以及相关联的热应力)。
在一个替代性实施例中,半导体器件14还包括位于第一侧42上的第二导电垫38和第三导电垫40。如图1所示,如虚线所示,第二垫38和第三导电垫40是可选的。类似地,在替代性实施例中,半导体器件14还包括第二金属表面23,如图1中的虚线所示,第二金属表面23是可选的。
导电垫(34、38、40)中的任何一个导电垫或全部导电垫由导电材料构成,导电材料例如是金属(例如铜)、合金或金属材料。
图2是沿着图3A和图3B中的参考线2-2截取的电子组件111的剖面的实施例。图2示出了电子组件111的一个可能的剖面的说明性实例。在图1、图2、图3A和图3B的任意组合中,相同的附图标记表示相同的元件或特征。
第一基板或引线框架
在一个实施例中,第一基板包括一个或多个引线框架110,用以与相应的半导体器件14上的至少第一导电垫34接合。在另一个实施例中,第一基板包括多个引线框架110,用以与相应的多个相应的半导体器件14上对应的第一导电垫34接合。如图2所示,每一个引线框架110与对应的导电垫34、对应的第二导电垫38以及对应的第三导电垫40结合、接合或配准,并且这些导电垫与半导体器件14(例如半导体芯片)的第一侧42相关联。
在一个实施例中,如图2和图3A中最佳地示出的,第一导电垫34可以包括连续的金属构件(例如具有矩形或多边形表面积),其中,焊膏的第一矩阵112被放置在第一导电垫34上的岛的网格、阵列或图案上;第二导电垫38可以包括连续的金属构件(例如具有矩形或多边形表面积),其中,第二焊膏矩阵212被放置在第二导电垫38上的岛的网格、阵列或图案上;第三导电垫40可以包括连续的金属构件(例如具有矩形或多边形表面积),其中,焊膏的第三矩阵312被放置在第三导电垫40上的岛的网格、阵列或图案上。例如,在制造组件111期间,使焊膏回流。总体而言,可以将第一焊膏矩阵112、第二焊膏矩阵212和第三焊膏矩阵312称为第一结合层12。
在替代性实施例中,一组第一导电垫包括由半导体器件14的第一侧42上的横向间隙(例如横向电介质间隙或空气间隙)间隔开的导电金属岛的网格或阵列。类似地,一组第二导电垫包括由半导体器件14的第一侧42上的横向间隙(例如横向电介质间隙或空气间隙)间隔开的导电金属岛的网格或阵列;一组第三导电垫包括由半导体器件14的第一侧42上的横向间隙(例如横向电介质间隙或空气间隙)间隔开的导电金属岛的网格或阵列。在替代性实施例中,第一焊膏矩阵、第二焊膏矩阵和第三焊膏矩阵(112、212、312)与下方的一组第一导电垫、下方的一组第二导电垫以及下方的一组第三导电垫在空间上对齐并且在尺寸和形状上共同扩展。
在一种构造中,每一个引线框架110具有大致平坦部分46,该大致平坦部分46具有下表面和上表面,所述下表面用于与半导体器件14上的第一导电垫34接合,并且所述上表面用于直接地或间接地联接或接收第一热沉20。此外,大致平坦部分46可以与第一导电垫34、第二导电垫38及第三导电垫40接合。例如,每一个第一结合层12可以使一个或多个引线框架110(通过其下表面)与一个或多个相应的半导体器件14的对应的第一导电垫34、对应的第二导电垫38以及对应的第三导电垫40互相连接。此外,第一导电垫34与半导体器件14的对应的第一端子相关联,第二导电垫38与半导体器件14的对应的第二端子相关联,并且第三导电垫40与半导体器件14的第三端子相关联,其中,每一个端子表示半导体器件14的不同的结点或端口(例如输入或输出端口)。尽管端子的其它配置是可能的,但在一种构造中,第一端子包括二极管的阳极,其中,第二端子包括晶体管的发射极或源极,并且第三端子包括晶体管的基极或栅极。
第一结合层12可以包括连续的金属层(例如在焊料或焊料和铜回流之后)或者可以包括被至少一个横向空气间隙或横向隔离间隙隔开的不连续的导电岛的第一矩阵112、第二矩阵212和第三矩阵312(例如一维或二维网格或阵列),以支持用于每一个半导体器件14的不同的引线或端子。在一种构造中,第一端子或第一导电垫34与相应的第一矩阵112相关联,第二端子或第二导电垫38与相应的第二矩阵212相关联,并且第三端子或第三导电垫40与第三矩阵312相关联。
如图所示,热界面层36(例如电介质热界面材料)或其它电介质层被设置在引线框架110(或其上表面)与第一热沉20或其第一基部32之间。在一种构造中,第一热沉20具有大致平坦的配合表面或第一基部32,用以邻接热界面材料36。翅片26、脊部或其它突起部从第一热沉20的与大致平坦的配合表面相反的一侧向外延伸。
在一个实施例中,第一基板包括引线框架110,引线框架110具有大致平坦部分46,大致平坦部分46具有用于与第一结合层12(例如第一金属结合层)接合的一系列孔或孔格(如图5所示)。例如,第一基板包括引线框架110,引线框架110能够横向地扩散或消散热量,以使电子组件111的不同部分内或者电子组件111的多个半导体器件14之间的任何温度差异减小。
第二基板
如图2所示,第二基板包括具有第二基部30的第二热沉24。第二基部30具有大致平坦表面,用以与一个或多个半导体器件14的第一金属表面22、第二金属表面23、或者第一金属表面22及第二金属表面23两者相互连接。第二结合层16促进第二基部30或第二热沉24与一个或多个半导体器件14的第一金属表面22、第二金属表面23、或者第一金属表面22及第二金属表面23两者之间的相互连接。翅片28、脊部或其它突起部从第二热沉24的与大致平坦表面相反的一侧向外延伸。
金属结合层
在一个实施例中,第一结合层12可以包括一个或多个以下焊膏或者焊膏和铜材料的组合的矩阵:第一矩阵112、第二矩阵212或第三矩阵312。在一个实施例中,第一结合层12或第一金属结合层由焊接材料(例如锡和银、铅焊料或者另一合适的无铅焊接材料的组合物)构成。在替代性实施例中,第一结合层12可以包括焊料和铜材料的组合。例如,第一结合层12包括焊接材料(例如无铅焊接材料)和涂覆有例如锡、银或无电镀镍浸金(ENIG)等可焊接的抛光材料的铜粒。
在一个实施例中,焊接材料或焊膏是无铅焊接材料或合金组合物,例如锡-银、锡-银-铜、或锡-金、或锡以及一种或多种其它金属元素,例如锑、铋、铟或锌。例如,锡-银-铜焊料合金组合物可以由约2.5%至4%(质量)的银、约0.25至1%(质量)的铜和其余质量为锡或锡的组合物构成。对于焊膏而言,焊料粉末的尺寸范围应该是:20至38微米,并且焊膏是90%(焊膏中焊料的重量百分比)的金属载荷。
在替代性实施例中,如果根据适用的法律和法规(例如军用规格)许可含铅的焊接材料,则焊膏可以包含铅,例如锡-银-铅或者锡-铅。
在一个实施例中,铜材料或附加铜材料被添加到上述焊接材料或合金组合物中,使得铜含量可以超过第一结合层12或第二结合层16的质量范围的0.25%至1%。例如,除了其它可能性以外,嵌设在焊膏中的铜材料可以呈镀覆有可焊的抛光材料(例如锡、银或ENIG等)的盘体的形式。在一种说明性构造中,盘体的直径和厚度分别为0.025英寸(0.625mm),公差为±0.002英寸,以及0.010英寸(0.25mm),公差为±0.001英寸,并且焊膏/铜复合材料中的体积百分比在约15%至约40%的范围内。在一个实施例中,第二结合层16可以包括焊膏的一个或多个隔开的岛、主体或矩阵(例如图7中的附图标记116所示)或焊料(例如无铅焊料,甚至包括高达1%(质量)的铜)的组合物(例如合金组合物)和铜材料(例如铜粒、铜片、铜丸或铜填料)。在一种构造中,第二结合层16或第二金属结合层由铜材料和焊接材料(例如锡和银、铅焊料或另一种适合的无铅焊接材料的组合物)构成。在一个实施例中,铜包括涂覆有锡、银或无电镀镍浸金的铜丸。铜非常适于降低第二结合层16的同系温度,以提高第二结合层16与第一金属表面22之间的结合的机械强度。
在一种构造中,半导体器件14能够产生热量,第一结合层12和第二结合层16包括金属材料或热界面材料,该金属材料或热界面材料从一个或多个半导体器件14中的每一个半导体器件14的第一侧42以及从每一个半导体器件14的第二侧44同时传导热量离开所述一个或多个半导体器件14。
在某些构造中,半导体器件14具有第一热膨胀系数(CTE),并且第一基板10(例如引线框架110)或第二基板18(例如第二热沉24)具有第二热膨胀系数(CTE);第一结合层12或第二结合层16中的铜分别减少了第一CTE和第二CTE之间的失配(以及相关联的热应力)。
热量的消散
在一个实施例中,电子组件111包括一组半导体器件14。例如,每一个半导体器件14包括半导体芯片,例如位于直接结合的铜载体或半导体基板之上或之中的绝缘栅双极型晶体管(IGBT)或者绝缘栅双极型晶体管和二极管。在正常操作期间,每一个半导体器件14都能够产生热量。第一结合层12和第二结合层16包括热界面材料,该热界面材料从半导体器件14的第一侧42以及从半导体器件14的第二侧44同时传导热量离开半导体器件14。第一基板包括一个或多个引线框架110,引线框架110能够横向地扩散或消散热量,以使电子组件111的不同部分内或者电子组件111的多个半导体器件14之间的任何温度差异减小。
在一个实施例中,第一基板包括引线框架110,引线框架110具有大致平坦部分46,大致平坦部分46具有用于与半导体器件14上对应的第一导电垫34、第二导电垫38和第三导电垫40相接合的下表面。此外,引线框架110的大致平坦部分46具有用于直接地或间接地联接或接收第一热沉20的上表面。例如,(引线框架110的)大致平坦部分46的上表面邻接夹在上表面和第一热沉20或其第一基部32之间的电介质热界面材料36(例如导热粘合剂)。引线框架110终止于第一端子48和第二端子50,第一端子48和第二端子50可以通过焊接点67连接到电路板25上的导电迹线57。如图2所示,电路板25具有开口59,开口59的尺寸和形状适于以存在周边间隙的方式接纳半导体器件14。电路板25可以由具有玻璃填料的陶瓷的、聚合物的、塑料的聚合物构成,例如,电路板25的一侧或两侧上具有导电迹线。
图3A是半导体器件14的一个说明性实施例的第一侧42(例如上侧)的平面图。半导体器件14的第一侧42包括第一导电垫34、第二导电垫38和第三导电垫40,这些导电垫被一个或多个电介质隔离物145彼此横向地隔开。每一个电介质隔离物145代表一个空气间隙、陶瓷绝缘区域、塑料或聚合物绝缘区域、或其它电介质区域。在一个实施例中,每一个第一导电垫34、每一个第二导电垫38和每一个第三导电垫40与相应的半导体器件14的对应的引线或端子相关联。例如,任何一个垫(34、38和40)都可以表示:(1)栅极垫或基极垫,(2)发射极垫或源极垫,(3)阳极垫,或者(4)阴极垫。
用于半导体器件14的对应的垫(34、38、40)或者一组垫的增大的表面积促进了半导体器件14的增强的散热性。如图所示,第一导电垫34、第二导电垫38和第三导电垫40被布置成被电介质隔离物145、电介质中间区域或电介质边界分开的大致矩形的金属垫的网格或阵列,其中,垫(34、38、40)共同占据了半导体器件14的第一侧42的大部分。图8示出了4个半导体器件14的平面图,其中,第一焊膏矩阵112、第二焊膏矩阵212和第三焊膏矩阵312沉积在以下部件中的一个或多个部件上:至少一个第一导电垫34、至少一个第二导电垫38、以及至少一个第三导电垫40。
图3B是与图3A一致的半导体器件14的一个说明性实施例的第二侧44(例如下侧)的平面图。在一个实施例中,半导体器件14的第二侧44包括第一金属表面22、第二金属表面23、或者第一金属表面22及第二金属表面23两者。例如,第一金属表面22可以包括以下金属垫或导电垫中的一个或多个垫:(1)栅极垫或基极垫,(2)集电极垫或漏极垫,(3)阴极垫,以及(4)阳极垫。在一种构造中,与从半导体器件14的相应端子承载目标(例如设计的或峰值负载)电流所需的最小表面积相比,具有用于半导体器件14的相应端子的增大的表面积的金属表面(22、23)促进了增强的散热性。如图所示,第一金属表面22和第二金属表面23被布置成由电介质区域45或电介质边界分开的大致矩形的金属垫的网格或阵列。电介质区域45表示位于第一金属表面22和第二金属表面23之间的中间的或介入的电介质隔离物。例如,电介质区域45可以由空气间隙、陶瓷绝缘区域、聚合物或塑料绝缘区域、或其它绝缘区域限定,其中,与第一金属表面22及第二金属表面23齐平的陶瓷或聚合物区域阻止(例如第二结合层16的)焊料流入垫之间的任何间隙中,否则,垫之间的任何间隙中可能形成短路或不需要的电容耦合。在此,第一金属表面22和第二金属表面23共同占据了半导体器件14的第二侧44的大部分表面积。
图4中的电子组件211类似于图2中的电子组件111,但电子组件211还包括介于第二基板或第二热沉24和半导体器件14之间的附加基板56或电路板。
如图4所示,附加基板56包括具有上表面58的单侧或双侧电路板,上表面58具有用于与半导体器件14上的以下一个或多个表面接合的导电配合表面62和导电迹线64:(1)第一金属表面22,(2)第二金属表面23,或者第一金属表面22及第二金属表面23两者。如图所示,电介质区域66将导电配合表面62分隔成两个独立的区域,这两个区域可以与对应的导电迹线64相关联。每一个独立区域或者导电迹线64都可以与半导体器件14的不同端子相关联,这些端子例如是晶体管的集电极端子和阴极端子、与晶体管相关联的防护性二极管。如图所示,电介质区域45与电介质区域66对齐或配准,以保持电绝缘并且支撑用于第一金属表面22和第二金属表面23的不连续的独立端子。此外,导电迹线64可以终止于导电垫,以便通过焊接点67或其它电连接部而连接到电路板25或电路板25上的导电迹线64。
如图所示,附加基板56的下表面60包括邻接或接触第二热沉24的第二基部30的电介质层65。电介质层65可以在电介质层65与第二热沉24的第二基部30之间具有可选的散热膏或导热粘合剂,用以促进热能远离半导体器件14的热传递。
在替代性实施例中,辅助基板56的下表面60包括导电接地平面(例如金属化外层),并且辅助基板56包括双侧电路板,其中,导电接地平面可以通过焊料或者焊料和铜材料的组合的第三结合层而连接到或结合到第二热沉24。
在另一替代性实施例中,其中,辅助基板56包括双侧电路板,并且导电的过孔或者经过电镀的通孔可以将至少一个配合垫连接到接地平面。
图5是适用于任何电子组件(例如附图标记11、111、211、311)的多个说明性引线框架110的平面图。第一基板可以包括一个或多个引线框架110。在一个实施例中,第一基板包括引线框架110,引线框架110具有大致平坦部分46,大致平坦部分46具有用于与第一结合层12(例如焊料)接合的一系列孔或孔格54。如图5和图9所示,引线框架110的大致平坦部分46被居中地设置,以便通过第一结合层12而与下列部件中的一个或多个部件配准或对准配合:半导体器件14的(1)对应的第一导电垫34、(2)对应的第二导电垫38、以及(3)对应的第三导电垫40。此外,在一些实施例中,虽然引线框架110的大致平坦部分46被分成或者再分成不连续的区段,这些不连续的区段不是电连接和机械地连接的,而是被空气间隙或者电介质间隙隔开,以允许同时支持多个隔开的半导体端子,例如栅极端子或基极端子、发射极端子或源极端子、集电极端子或源极端子、以及阳极端子或阴极端子。
在一个实施例中,引线框架110的平坦部分46中的焊料除气孔54可以连接到一个或多个半导体器件14(例如半导体芯片),例如绝缘栅双极结型晶体管(IGBT)芯片、二极管芯片、或者IGBT芯片和二极管芯片两者。每一个半导体芯片都可以被安装或制造成直接接合式铜基板。
如图5所示,孔54用作焊料除气出口,并且允许在焊接结束时在引线框架110的表面上创建焊料圆角的阵列。液态焊料的除气支撑物使在第一结合层12的固化结合层中形成空隙的机会减少。例如,引线框架110的顶表面上减少的空穴和焊料圆角的存在能够增强第一结合层12的热机械可靠性,由此增强操作中的组件(11、111、211或311)或功率模块的热机械可靠性。
每一个引线框架110都终止于端子(48、50)或指状物52中,所述端子(48、50)或指状物52可以通过导体、电路板25的导电迹线、电线、电缆或者传输线连接到电子组件(11、111、211、311)的其它电路系统。在一个实施例中,(例如,与其它端子相比)引线框架110的具有最大表面积或质量的端子48可以被分配给半导体器件14的集电极或漏极;引线框架110的具有第二最大表面积或质量的端子50可以被分配给半导体器件14的发射极或源极,尽管端子的其它分配方式也是可能的并且落入权利要求的范围内。
替代性地,(例如,与其它端子相比)引线框架的具有最大表面积或质量的端子48可以被分配给半导体器件14的发射极或源极;引线框架110的具有第二最大表面积或质量的端子50可以被分配给半导体器件14的集电极或漏极。
图6是用于制造具有增强的散热性的电子组件(11、111、211或311)的方法的流程图的一个实施例。图6中的方法从步骤S500开始。
在步骤S500中,将焊膏沉积在第二基板18上,第二基板18例如是第二热沉24的第二基部30或者为散热而设计的电路板(例如具有接地平面和一个或多个导电过孔的双侧电路板)。例如,分配器或施加器将焊膏分配或施加到第二基板18上。
在步骤S502中,将铜材料嵌设或设置到所沉积的焊膏中。步骤S502可以在步骤S500之前、之后或期间执行。在一个实例中,在沉积焊膏期间或之后将铜材料添加到焊膏中。在另一个实例中,在步骤S500中将焊膏沉积到第二基板18上之后,将铜丸添加到焊膏中。嵌设或设置铜材料能够降低第二结合层(16或116)的同系温度,以提高第二结合层(16或116)与第一金属表面22之间的结合和/或第二结合层16与第二金属表面23之间的结合的机械强度。
在步骤S504中,分配器或施加器将焊膏(例如以矩阵的样式)沉积在一个或多个半导体器件14的多个上导电垫(34、38、40)上。例如,分配器或施加器将焊膏沉积到第一导电垫34、第二导电垫38和第三导电垫40上。在一种构造中,每一个半导体器件14都具有第一侧42或者上侧,第一侧42或者上侧具有第一导电垫34、第二导电垫38和第三导电垫;每一个半导体器件14都具有与第一侧42相反的第二侧44。
在步骤S506中,将一个或多个半导体器件14放置和对准在第二基板18或第二热沉24上。例如,取放机(pick-and-place machine)将一个或多个半导体器件14(例如半导体芯片)放置和对准在第二基板18上或者放置和对准在第二热沉24的第二基部30的大致平坦表面上。
在步骤S508中,将第一基板10或者一个或多个引线框架110放置和对准在以下部件的一个或多个部件上:对应的第一导电垫34、对应的第二导电垫38、以及对应的第三导电垫40。例如,取放机将第一基板或引线框架110放置和对准在每一个半导体器件14的对应的第一导电垫34上,以便将引线框架110的第一端子分配或指定给第一导电垫34,将引线框架110的第二端子分配或指定给第二导电垫38以及将引线框架110的第三端子分配或指定给第三导电垫40。半导体制造商或设计者为每一个导电垫(34、38、40)分配半导体器件14的特定输入/输出端口或结点,例如栅极、源极或漏极端子。
在步骤S510中,组件(11、111、211、311)在单个热循环中被加热一次(例如在回流炉中仅加热一次),以便在第一基板(例如引线框架110)和上导电垫(34、38、40)之间形成第一结合层12或112、212和312(例如,第一金属结合层)并且在第二基板18(例如第二热沉24)与一个或多个金属表面(22、23或两者)(例如一个或多个下导电垫)之间形成第二结合层16或116(例如第二金属结合层)。
可以根据可以被单独地或累积地应用的各种技术来执行步骤S510。在第一种技术中,组件(11、111、211、311)在单个热循环中被加热一次(例如在回流炉中仅加热一次),以便在一个或多个引线框架110与第一侧42上的上导电垫(34、38、40)之间形成第一结合层12或112、212和312,并且在第二热沉24与在一个或多个半导体器件14的第二侧44上的第一金属表面22(或第一金属表面22和第二金属表面23两者)之间形成第二结合层16或116。
在第二种技术中,回流炉根据热回流工艺在焊接室中加热组件(11、111、211、311),以便在第一基板10(例如引线框架110)与导电垫(34、38、40)之间形成第一结合层12(例如第一金属结合层),并且在第二基板18与在一个或多个半导体器件14的第二侧44上的第一金属表面22之间形成第二结合层(例如第二金属结合层)。
在第三种技术中,组件(11、111、211)的加热在单个加热循环中发生一次。加热组件(11、111、211)一次非常适于减小(结合层12、16中的)焊料层金属间化合物的层厚度,以促进第一结合层12和第二结合层16的完整性。
在第四种技术中,第一结合层12和第二结合层16包括两个金属间化合物(IMC)结合层,这两个金属间化合物结合层在焊接期间通过焊膏材料的熔化、润湿和扩散而同时形成。IMC层既将半导体器件14的第一侧42粘合或结合到引线框架110,又将第二侧44粘合或结合到热沉(例如第二热沉24)或热沉电路板。图9示出了用于逆变器或其它功率电子模块的完全构建的和功能性电子组件(11、111、211)或子组件的平面图。
在第五种技术中,第一结合层12和第二结合层16在单次加热循环或回流工艺期间同时形成,其中,焊接材料(例如无铅焊接材料)的熔化温度范围应当为约217摄氏度至约230摄氏度。
在第六种技术中,第一结合层12和第二结合层16在单次加热循环或回流工艺期间同时形成,其中,焊接材料(例如(合法且实用的)含铅焊膏)的熔化温度范围为约180摄氏度至约190摄氏度。
图7是第二基板18的平面图,第二基板18例如是第二热沉24的第二基部30的大致平坦表面,其中,(具有或不具有铜材料的)焊膏被布置在导电构件上的总体上呈矩形的矩阵116中,用以与一个或多个半导体器件14上相应的第一金属表面22、第二金属表面23、或者第一金属表面22及第二金属表面23两者配合。图7示出了图6的步骤S500的结果或者完成情况。
图8是多个半导体器件14的平面图,其中,焊膏被布置在这些半导体器件各自的导电垫(例如第一导电垫34、第二导电垫38和第三导电垫40)上的矩阵中。导电垫(34、38、40)被示出为总体上呈矩形的区域,这些区域位于焊膏或者焊膏和铜材料的组合的对应矩阵下方。在一个实施例中,焊膏或者组合的焊膏和铜材料的第一矩阵112覆盖在由铜或铜合金构成的对应的第一导电垫34上;焊膏或者组合的焊膏和铜材料的第二矩阵212覆盖在由铜或铜合金构成的对应的第二导电垫38上;焊膏或组合的焊膏和铜材料的第三矩阵312覆盖在由铜或铜合金构成的对应的第三导电垫40上。图8示出了图6的步骤S504的结果或完成情况。
图9是电子组件(11、111或211)的一个实施例的平面图。图9示出了图6的步骤S506、步骤S508、或者步骤S506及步骤S508两者的结果或完成情况。
在传统的制造工艺中,每一个结合层(例如第一结合层12和第二结合层16)的形成都需要一个独立的制造周期或者热循环。因此,根据一些传统工艺,为了创建组件(11、111或211)的两个结合层(12、16),通常需要两个制造周期或热循环。所公开的方法和相关结构将加热循环或制造周期从两个周期减少到一个周期,这可以被称为单程加热工艺或单程回流工艺。这种单程加热工艺能够减少制造成本、制造时间和制造热能输入,或者能够增加制造单元的产量。
图10是沿着图11A中的参考线10-10观察到的电子组件311的剖面的替代性实施例。图10的电子组件311与图2的电子组件111类似,但半导体器件14的第二侧44包括第一金属表面122,第一金属表面122占据了第二侧面44的表面积的大部分,以便形成金属接地平面。如图10所示,在电子组件311中,每一个半导体器件14的第二侧44不具有电介质区域45,并且省略了第二金属表面23。因此,第二结合层16或116形成在第一金属表面122与第二热沉24的第二基部30的大致平坦表面之间。如前文所述,第二结合层16可以由焊料或者焊料和铜材料的组合物构成。
图11A是根据图10的半导体器件的一个说明性实施例的第一侧(例如上侧)的平面图。图10、图11A和图11B中相同的附图标记表示相同的元件或特征。
图11B是与图10及图11A一致的半导体器件的一个说明性实施例的第二侧(例如下侧)的平面图。
本文所公开的方法非常适于使用无铅焊接材料、硅半导体或者碳化硅半导体的制造工艺。焊接材料可能需要遵守环境法规和指令,例如2011年6月8日的欧洲议会和理事会的指令2011/65/EU。电子组件(11、111或211)的方法有利于在严苛的条件下(例如高温、高电压和电流、高冲击和振动以及变化的应用环境)实现电子组件(11、111或211)的成本高效且可靠的操作。本文所公开的方法也非常适于满足或超过高温应用(例如在200摄氏度或以上的那些应用)的增强的双侧散热情况。
虽然已经描述了优选的实施例,但显而易见的是,在不脱离随附的权利要求书所限定的本发明的范围的情况下,可以做出各种修改。
Claims (26)
1.一种电子组件,包括:
半导体器件,所述半导体器件包括第一侧以及与所述第一侧相反的第二侧;所述第一侧具有第一导电垫;所述第二侧具有第一金属表面;
第一基板,所述第一基板通过第一金属结合层结合到所述第一导电垫;以及
第二基板,所述第二基板通过第二金属结合层结合到所述第一金属表面,其中,所述第二金属结合层由焊料和铜构成。
2.根据权利要求1所述的电子组件,其中,所述第一金属结合层由焊料构成。
3.根据权利要求2所述的电子组件,其中,所述第一金属结合层被布置为第一焊料岛矩阵。
4.根据权利要求1所述的电子组件,其中,所述第一金属结合层由焊料和铜构成。
5.根据权利要求1所述的电子组件,其中,所述第一基板包括引线框架,所述引线框架具有大致平坦部分,所述大致平坦部分具有下表面和上表面,所述下表面用于与所述半导体器件上的所述第一导电垫接合,所述上表面用于直接地或间接地联接或接收第一热沉。
6.根据权利要求5所述的电子组件,还包括位于所述引线框架的所述上表面与所述第一热沉之间的电介质热界面材料。
7.根据权利要求1所述的电子组件,其中,所述半导体器件的第一侧具有所述第一导电垫、第二导电垫和第三导电垫,其中,所述第一导电垫与所述半导体器件的相应的第一端子相关联,所述第二导电垫与所述半导体器件的相应的第二端子相关联,并且所述第三导电垫与第三端子相关联。
8.根据权利要求7所述的电子组件,其中,所述第一端子包括二极管的阳极,其中,所述第二端子包括晶体管的发射极或源极,并且所述第三端子包括所述晶体管的基极或栅极。
9.根据权利要求1所述的电子组件,其中,所述半导体器件的第二侧包括所述第一金属表面以及第二金属表面,其中,所述第一金属表面和所述第二金属表面被电介质区域或电介质隔离物隔开和分离,并且其中,所述第一金属表面和所述第二金属表面共同占据所述第二侧的大部分。
10.根据权利要求9所述的电子组件,其中,所述第一金属表面与晶体管的集电极或漏极端子相关联,并且其中,所述第二金属表面与二极管的阴极端子相关联。
11.根据权利要求9所述的电子组件,还包括:
具有基体的第二热沉,其中,所述第一金属表面和所述第二金属表面通过所述第二金属结合层结合到所述基体。
12.根据权利要求9所述的电子组件,还包括:
具有上表面的电路板,所述上表面具有用于与所述第一金属表面及所述第二金属表面接合的导电配合表面,其中,所述导电配合表面被电介质区域分成两个隔开的区域,所述两个隔开的区域与所述半导体器件的不同的端子相关联,并且其中,第二金属结合层形成在所述导电配合表面、所述第一金属表面和所述第二金属表面之间。
13.根据权利要求12所述的电子组件,还包括所述电路板的下表面,所述下表面与所述上表面相反,其中,所述下表面包括金属接地平面,并且其中,第三金属结合层形成在所述金属接地平面与第二热沉之间。
14.根据权利要求1所述的电子组件,其中,所述第一金属表面包括接地平面,所述接地平面占据所述半导体器件的第二侧的大部分;所述电子组件还包括:
具有基体的第二热沉,其中,所述第一金属表面通过所述第一金属结合层结合到所述基体。
15.根据权利要求1所述的电子组件,其中,所述半导体器件包括安装在直接结合的铜载体或半导体基板上的绝缘栅双极型晶体管,或者包括安装在直接结合的铜载体或半导体基板上的绝缘栅双极型晶体管与二极管的组合。
16.根据权利要求1所述的电子组件,其中,所述铜包括涂覆有锡、银或无电镀镍浸金的多个铜粒。
17.根据权利要求1所述的电子组件,其中,所述铜使所述第二金属结合层的同系温度降低,以增大所述第二金属结合层与所述第一金属表面之间的结合的机械强度。
18.根据权利要求1所述的电子组件,其中,所述半导体器件具有第一热膨胀系数(CTE),并且其中,所述第一基板或所述第二基板具有第二热膨胀系数(CTE),并且其中,所述第一金属结合层或所述第二金属结合层中的铜分别减少所述第一热膨胀系数和所述第二热膨胀系数之间的失配。
19.根据权利要求1所述的电子组件,其中,所述第一基板包括引线框架,所述引线框架具有大致平坦部分,所述大致平坦部分具有用于与所述第一金属结合层接合的一系列孔或孔格。
20.根据权利要求1所述的电子组件,其中,所述半导体器件能够产生热量,所述第一金属结合层和所述第二金属结合层同时从所述半导体器件的第一侧和所述半导体器件的第二侧将所述热量传导离开所述半导体器件。
21.根据权利要求1所述的电子组件,其中,所述第一基板包括引线框架,所述引线框架能够横向地扩散或消散热量,以使所述电子组件的不同部分内或者所述电子组件的多个半导体器件之间的任何温度差异减小。
22.一种用于制造电子组件的方法,所述方法包括:
在第二基板上沉积焊膏;
在所沉积的焊膏中嵌设或设置铜材料;
将焊膏沉积在一个或多个半导体器件的多个上导电垫上,每一个半导体器件具有第一侧以及与所述第一侧相反的第二侧,所述第一侧具有上导电垫;
将所述一个或多个半导体器件放置和对准在所述第二基板上;
将第一基板放置和对准在所述上导电垫上;以及
加热所述组件一次,以便在所述第一基板与所述上导电垫之间形成第一金属结合层,并且在所述第二基板与所述一个或多个半导体器件的第二侧上的第一金属表面之间形成第二金属结合层。
23.根据权利要求22所述的方法,其中,加热所述组件一次发生在单次加热循环中。
24.根据权利要求22所述的方法,其中,嵌设或设置铜材料包括嵌设铜粒。
25.根据权利要求22所述的方法,其中,嵌设或设置铜材料使所述第二金属结合层的同系温度降低,以增大所述第二金属结合层与所述第一金属表面之间的结合的机械强度。
26.根据权利要求22所述的方法,其中,加热所述组件一次使焊料层金属间化合物的层厚度减小,以促进所述第一金属结合层和所述第二金属结合层的完整性。
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US20180247885A1 (en) | 2018-08-30 |
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