CN108493096A - 一种退火处理形成电荷存储结构的方法 - Google Patents

一种退火处理形成电荷存储结构的方法 Download PDF

Info

Publication number
CN108493096A
CN108493096A CN201810212709.6A CN201810212709A CN108493096A CN 108493096 A CN108493096 A CN 108493096A CN 201810212709 A CN201810212709 A CN 201810212709A CN 108493096 A CN108493096 A CN 108493096A
Authority
CN
China
Prior art keywords
layer
film
charge storage
storage structure
annealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201810212709.6A
Other languages
English (en)
Other versions
CN108493096B (zh
Inventor
汤振杰
李�荣
胡丹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anyang Normal University
Original Assignee
Anyang Normal University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anyang Normal University filed Critical Anyang Normal University
Priority to CN201810212709.6A priority Critical patent/CN108493096B/zh
Publication of CN108493096A publication Critical patent/CN108493096A/zh
Application granted granted Critical
Publication of CN108493096B publication Critical patent/CN108493096B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02189—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing zirconium, e.g. ZrO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Optics & Photonics (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

本发明公开了一种退火处理形成电荷存储结构的方法，通过退火过程，借助单层多组元金属氧化物(M)x(N)1‑x薄膜退火过程中低结晶温度M析晶、扩散和重新分布的特点，自发形成富N的(M)x(N)1‑x隧穿层/富M的(M)x(N)1‑x存储层/富N的(M)x(N)1‑x阻挡层电荷存储结构，其中M可在ZrO2、HfO2、La2O3、TiO2中任选一种，N可在SiO2、Al2O3中任选一种。

Description

一种退火处理形成电荷存储结构的方法
技术领域
本发明属微电子器件及其材料领域，涉及一种利用退火处理形成电荷存储结构的方法。
背景技术
随着信息社会的不断进步，非易失性半导体存储器获得了前所未有的发展。在非易失性存储器件家族当中，硅-氧化物-氮化物-氧化物-多晶硅(SONOS)型电荷陷阱存储器件以其稳定性高、与半导体工艺兼容性好等优点成为一种极具应用前景的存储结构，其中紧邻硅(Si)衬底的氧化物(SiO2)隧穿层、氮化物(Si3N4)存储层、以及紧挨着多晶硅电极的氧化物(SiO2)阻挡层构成典型的三明治电荷存储结构。器件在编程操作下，电荷穿过隧穿层，进入到存储层，被存储层中的缺陷俘获，从而达到信息存储的目的，其中阻挡层和隧穿层的存在，抑制了存储电荷在数据保持状态下，向衬底和电极方向的泄漏。
对于传统的SONOS型电荷存储器件，通常利用化学气相沉积、物理溅射等方法在衬底材料表面顺序生长隧穿层、存储层、和阻挡层形成电荷存储结构，器件制备过程比较复杂。基于简化非易失性电荷存储器件制备过程的考虑，我们发明了一种退火处理单层多组元金属氧化物薄膜工艺，借助多组元氧化物薄膜结晶过程组分重新分布机理，自发形成具有三明治电荷存储结构。
发明内容
本发明提供了一种退火处理单层多组元金属氧化物薄膜工艺，形成电荷存储结构的方法，操作简单。
所述退火处理形成电荷存储结构的方法具体过程如下：
a)将硅衬底置于丙酮中，超声清洗1分钟，去除衬底表面杂质，然后将衬底置于氢氟酸稀溶液中，去除硅衬底表面的氧化物，然后将硅衬底放置在脉冲激光沉积系统腔内的衬底台上，将多组元金属氧化物(M)x(N)1-x和铝(Al)靶材置于靶材底盘上，其中M可在ZrO2、HfO2、 La2O3、TiO2中任选一种，N可在SiO2、Al2O3中任选一种，x在0.5-0.8范围内取值，沉积腔内压强为1×10-5Pa-5×10-5Pa；
b)利用脉冲激光沉积系统在硅衬底表面沉积一层厚度为20-30nm的(M)x(N)1-x薄膜，如图1(a)所示；
c)将衬底台温度升高到850℃，沉积的(M)x(N)1-x薄膜在850℃下，退火处理1小时，使 (M)x(N)1-x薄膜中发生相分离反应，结晶温度较低的M相趋向在(M)x(N)1-x薄膜中间部位析出，随着退火过程的进行，组分不断扩散和重新分布，晶粒逐渐粗化和长大，造成(M)x(N)1-x薄膜中间部位M组元较多，N组元较少，形成富M的(M)x(N)1-x，而(M)x(N)1-x薄膜两侧M组元较少，N组元较多，形成富N的(M)x(N)1-x，单层(M)x(N)1-x薄膜在退火过程中自发形成三明治电荷存储结构，其中靠近硅衬底的富N的(M)x(N)1-x层作为隧穿层，富M的(M)x(N)1-x层作为电荷存储层，远离硅衬底的富N的(M)x(N)1-x层作为阻挡层，如图1(b)所示；
d)利用脉冲激光沉积系统在(M)x(N)1-x薄膜表面沉积一层100-200nm的Al金属作为电极，如图1(c)所示；
上述方法的原理是基于单层(M)x(N)1-x薄膜退火处理过程的组分重新分布，由于M较N 具有更低的结晶温度，在退火过程中析出，并随着退火时间延长，M向薄膜中间部位扩散， N向薄膜两边扩散，导致M晶粒在薄膜中间部位聚集并长大。因此，单层(M)x(N)1-x薄膜在退火处理过程中会自发形成富N的(M)x(N)1-x/富M的(M)x(N)1-x/富N的(M)x(N)1-x三明治电荷存储结构。图2(a)为未退火处理的单层(M)x(N)1-x薄膜能带图，由于薄膜组分均匀，因此薄膜能带一致。经过退火处理，薄膜组分扩散和重新分布，M趋向聚集于薄膜中间，而N趋向聚集于薄膜两侧。M较N具有更小的禁带宽度，所以M含量越多，禁带宽度越小，N含量越多，禁带宽度越大，如图2(b)所示。
优选(ZrO2)0.8(Al2O3)0.2薄膜，厚度为20nm，依据上述方法得到的结构，可用高分辨透射电子显微截面图表征，如图3所示：
从图3(a)中可以看出，未实施退火处理的(ZrO2)0.8(Al2O3)0.2为单层结构，而经过850℃， 1小时的退火处理后(图3(b))，低结晶温度的ZrO2趋于在接近薄膜中间部位结晶长大，形成富ZrO2的(ZrO2)x(Al2O3)1-x，厚度约为10nm，由于ZrO2大部分扩散到薄膜中间部位结晶，薄膜两侧形成富Al2O3的(ZrO2)x(Al2O3)1-x。通过退火处理单层(ZrO2)0.8(Al2O3)0.2薄膜，利用退火过程中组分的扩散和重新分布，实现了典型的三明治电荷存储结构，其中薄膜中间富ZrO2的(ZrO2)x(Al2O3)1-x薄膜层对应电荷存储结构的存储层，富Al2O3的(ZrO2)x(Al2O3)1-x薄膜层分别对应隧穿层和阻挡层。
上述方法所得电荷存储结构的存储性能可用不同栅极扫描电压下，电容-电压变化曲线表征，如图4所示：
从图中可以看出，未经过退火处理的薄膜，在不同栅极扫描电压下，没有表现出电容- 电压存储窗口，表明没有电荷存储性能，如图4(a)所示；而经过退火处理的薄膜，在±6V和±8V的栅极扫描电压下，分别具有2V和4V的存储窗口，表明该结构具有电荷存储性能。这主要是因为(ZrO2)0.8(Al2O3)0.2薄膜经过退火处理，薄膜组分重新分布，自发形成典型的三明治电荷存储结构。当Al电极施加正向电压时，电场指向硅衬底方向，衬底当中的电子在电场力的作用下穿过富Al2O3的(ZrO2)x(Al2O3)1-x隧穿层进入富ZrO2的(ZrO2)x(Al2O3)1-x存储层，被存储层中的缺陷俘获，引起平带电压向正向的偏移；当Al电极施加负向电压时，电场指向Al电极，富ZrO2的(ZrO2)x(Al2O3)1-x存储层俘获的电荷在电场力的作用下，穿过富Al2O3的 (ZrO2)x(Al2O3)1-x隧穿层回到衬底，引起平带电压向负向的偏移，从而表现出电容-电压存储窗口。
附图说明
图1：a)利用脉冲激光沉积系统在硅衬底表面沉积(M)x(N)1-x薄膜；b)退火处理后由于组分扩散和重新分布，(M)x(N)1-x薄膜自发形成三明治电荷存储结构；c)利用脉冲激光系统沉积 Al电极。
图2：单层(M)x(N)1-x薄膜退火处理前后能带排列示意图，a)退火处理前，b)退火处理后。
图3：单层(ZrO2)0.8(Al2O3)0.2薄膜退火处理前后薄膜的高分辨透射电子显微结构截面图，a)退火处理前，b)退火处理后。
图4：单层(ZrO2)0.8(Al2O3)0.2薄膜退火处理前后的电荷存储性能，a)退火处理前，b)退火处理后。
具体实施方式
实施例1：单层(ZrO2)0.8(Al2O3)0.2薄膜制备过程如下：
a)将硅衬底置于丙酮中，超声清洗1分钟，去除衬底表面杂质，然后将衬底置于氢氟酸稀溶液中，去除硅衬底表面的氧化物，然后将硅衬底放置在脉冲激光沉积系统腔内的衬底台上，将多组元金属氧化物(ZrO2)0.8(Al2O3)0.2和铝(Al)靶材置于靶材底盘上，沉积腔内压强为1 ×10-5Pa；
b)利用脉冲激光沉积系统在Si衬底表面沉积一层厚度为20nm的(ZrO2)0.8(Al2O3)0.2薄膜；
c)利用脉冲激光沉积系统在(ZrO2)0.8(Al2O3)0.2薄膜表面沉积一层100的Al金属作为电极；
实施例2：退火处理单层(ZrO2)0.8(Al2O3)0.2薄膜制备过程如下：
a)将硅衬底置于丙酮中，超声清洗1分钟，去除衬底表面杂质，然后将衬底置于氢氟酸稀溶液中，去除硅衬底表面的氧化物，然后将硅衬底放置在脉冲激光沉积系统腔内的衬底台上，将多组元金属氧化物(ZrO2)0.8(Al2O3)0.2和铝(Al)靶材置于靶材底盘上，沉积腔内压强为1 ×10-5Pa；
b)利用脉冲激光沉积系统在Si衬底表面沉积一层厚度为20nm的(ZrO2)0.8(Al2O3)0.2薄膜；
c)将衬底台温度升高到850℃，沉积的(ZrO2)0.8(Al2O3)0.2薄膜在850℃下，退火处理1 小时，使(ZrO2)0.8(Al2O3)0.2薄膜中发生相分离反应，结晶温度较低的ZrO2趋向在(ZrO2)0.8(Al2O3)0.2薄膜中间部位析出，随着退火过程的进行，组分不断扩散和重新分布，晶粒逐渐粗化和长大，造成薄膜中间部位ZrO2组元较多，Al2O3组元较少，形成富ZrO2的(ZrO2)x(Al2O3)1-x，而(ZrO2)0.8(Al2O3)0.2薄膜两侧ZrO2组元较少，Al2O3组元较多，形成富Al2O3的(ZrO2)x(Al2O3)1-x，单层(ZrO2)0.8(Al2O3)0.2薄膜在退火过程中自发形成三明治电荷存储结构，其中靠近硅衬底的富Al2O3的(ZrO2)x(Al2O3)1-x层作为隧穿层，富ZrO2的(ZrO2)x(Al2O3)1-x层作为电荷存储层，远离硅衬底的富Al2O3的(ZrO2)x(Al2O3)1-x层作为阻挡层；
d)利用脉冲激光沉积系统在(ZrO2)0.8(Al2O3)0.2薄膜表面沉积一层100的Al金属作为电极。

Claims (5)

1.一种退火处理形成电荷存储结构的方法，其特征在于具体步骤如下：
a)将硅衬底置于丙酮中，超声清洗1分钟，去除衬底表面杂质，然后将衬底置于氢氟酸稀溶液中，去除硅衬底表面的氧化物，然后将硅衬底放置在脉冲激光沉积系统腔内的衬底台上，将多组元金属氧化物(M)x(N)1-x和铝(Al)靶材置于靶材底盘上，其中M可在ZrO2、HfO2、La2O3、TiO2中任选一种，N可在SiO2、Al2O3中任选一种，x在0.5-0.8范围内取值，沉积腔内压强为1×10-5Pa-5×10-5Pa；
b)利用脉冲激光沉积系统在硅衬底表面沉积一层厚度为20-30nm(M)x(N)1-x薄膜；
c)将衬底台温度升高到850℃，沉积的(M)x(N)1-x薄膜在850℃下，退火处理1小时，使(M)x(N)1-x薄膜中发生相分离反应，结晶温度较低的M趋于在(M)x(N)1-x薄膜中间部位析出，随着退火过程的进行，组分不断扩散和重新分布，晶粒逐渐粗化和长大，造成(M)x(N)1-x薄膜中间部位M组元较多，N组元较少，形成富M的(M)x(N)1-x，而(M)x(N)1-x薄膜两侧M组元较少，N组元较多，形成富N的(M)x(N)1-x，单层(M)x(N)1-x薄膜在退火过程中自发形成三明治电荷存储结构，其中靠近硅衬底的富N的(M)x(N)1-x层作为隧穿层，富M的(M)x(N)1-x层作为电荷存储层，远离硅衬底的富N的(M)x(N)1-x层作为阻挡层；
d)利用脉冲激光沉积系统在(M)x(N)1-x薄膜表面沉积一层100-200nm的Al金属作为电极。
2.如权利要求1所述的退火处理形成电荷存储结构的方法，其特征在于单层(M)x(N)1-x薄膜经过退火处理自发形成隧穿层/存储层/阻挡层电荷存储结构。
3.如权利要求1所述的退火处理形成电荷存储结构的方法，其特征在于退火处理形成的隧穿层/存储层/阻挡层结构为富N的(M)x(N)1-x/富M的(M)x(N)1-x/富N的(M)x(N)1-x。
4.如权利要求1所述的退火处理形成电荷存储结构的方法，其特征在于利用脉冲激光沉积方法制备(M)x(N)1-x薄膜和金属Al电极。
5.如权利要求1-4所述的退火处理形成的电荷存储结构在信息存储中的应用。
CN201810212709.6A 2018-03-06 2018-03-06 一种退火处理形成电荷存储结构的方法 Active CN108493096B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810212709.6A CN108493096B (zh) 2018-03-06 2018-03-06 一种退火处理形成电荷存储结构的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810212709.6A CN108493096B (zh) 2018-03-06 2018-03-06 一种退火处理形成电荷存储结构的方法

Publications (2)

Publication Number Publication Date
CN108493096A true CN108493096A (zh) 2018-09-04
CN108493096B CN108493096B (zh) 2020-04-14

Family

ID=63339278

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810212709.6A Active CN108493096B (zh) 2018-03-06 2018-03-06 一种退火处理形成电荷存储结构的方法

Country Status (1)

Country Link
CN (1) CN108493096B (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020037624A1 (en) * 2000-09-01 2002-03-28 Yoshihiro Mori Capacitor and method for fabricating semiconductor device
US20020086470A1 (en) * 2000-12-29 2002-07-04 Lg.Philips Lcd Co., Ltd. Method for crystallizing amorphous silicon and fabricating thin film transistor using crystallized silicon
CN101170135A (zh) * 2006-10-23 2008-04-30 海力士半导体有限公司 具有电荷陷捕层的非易失性存储器件及其制造方法
CN102208346A (zh) * 2011-04-22 2011-10-05 南京大学 非易失性电荷捕获型存储器件、其制备方法及应用
CN102231365A (zh) * 2010-12-09 2011-11-02 南京大学 不挥发电荷存储器件的制备方法、所得不挥发电荷存储器件及其应用

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020037624A1 (en) * 2000-09-01 2002-03-28 Yoshihiro Mori Capacitor and method for fabricating semiconductor device
US20020086470A1 (en) * 2000-12-29 2002-07-04 Lg.Philips Lcd Co., Ltd. Method for crystallizing amorphous silicon and fabricating thin film transistor using crystallized silicon
CN101170135A (zh) * 2006-10-23 2008-04-30 海力士半导体有限公司 具有电荷陷捕层的非易失性存储器件及其制造方法
CN102231365A (zh) * 2010-12-09 2011-11-02 南京大学 不挥发电荷存储器件的制备方法、所得不挥发电荷存储器件及其应用
CN102208346A (zh) * 2011-04-22 2011-10-05 南京大学 非易失性电荷捕获型存储器件、其制备方法及应用

Also Published As

Publication number Publication date
CN108493096B (zh) 2020-04-14

Similar Documents

Publication Publication Date Title
CN102208442B (zh) 一种适合于半导体闪存器件的栅叠层结构及制备方法
JP4486309B2 (ja) 量子ドットを備えたメモリ素子の製造方法
CN105206615A (zh) 一种高介电系数复合氧化物电荷存储介质薄膜及应用
CN101692463A (zh) 一种混合纳米晶存储器的电容结构及其制备方法
CN102208346B (zh) 非易失性电荷捕获型存储器件、其制备方法及应用
Lu et al. Nanocrystalline silicon embedded zirconium-doped hafnium oxide high-k memory device
CN101383379A (zh) 多介质复合隧穿层的纳米晶浮栅存储器及其制作方法
CN104952712B (zh) NH4F制造n掺杂石墨烯和电气器件的方法及该石墨烯和器件
CN101312212A (zh) 利用高k介质和纳米晶浮栅的非易失存储器及其制作方法
CN108493096A (zh) 一种退火处理形成电荷存储结构的方法
Verrelli et al. Nickel nanoparticle deposition at room temperature for memory applications
Pan et al. A high-k Y2O3 charge trapping layer for nonvolatile memory application
JP2010226037A (ja) 半導体装置
CN101399289A (zh) 双层隧穿介质结构的纳米晶浮栅非易失存储器及制作方法
CN108538850A (zh) 一种高抗疲劳性的铁电栅场效应晶体管存储器及制备工艺
JP2006245583A (ja) 金属窒化物をトラップサイトとして利用したメモリ素子及びその製造方法
FI20175587A1 (en) Silicon-on-insulator construction with crystalline silica
CN110047842A (zh) 一种硅基电荷俘获型存储器件及制备方法
Kim et al. Dual dielectric tunnel barrier in silicon-rich silicon nitride charge-trap nonvolatile memory
TW200818408A (en) Non-volatile memory and method of manufacturing the same
CN107863349A (zh) 基于HfxSi1‑xO2多元氧化物存储材料的电荷存储器件及其制备方法
Tang et al. The charge storage characteristics of ZrO2 nanocrystallite-based charge trap nonvolatile memory
Maikap et al. Low voltage operation of high-κ HfO2/TiO2/Al2O3 single quantum well for nanoscale flash memory device applications
Wang et al. Thickness dependence of Al2O3/HfO2/Al2O3 stacked tunneling layers on gadolinium oxide nanocrystal nonvolatile memory
Kang et al. Effect of nitrogen plasma treatment on electrical characteristics for Pd nanocrystals in nonvolatile memory

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant