CN108461474A - 半导体器件、制作其的方法和加强其中的管芯的方法 - Google Patents

半导体器件、制作其的方法和加强其中的管芯的方法 Download PDF

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Publication number
CN108461474A
CN108461474A CN201810105995.6A CN201810105995A CN108461474A CN 108461474 A CN108461474 A CN 108461474A CN 201810105995 A CN201810105995 A CN 201810105995A CN 108461474 A CN108461474 A CN 108461474A
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interarea
tube core
insulator
conductive post
semiconductor devices
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CN201810105995.6A
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E.迈尔斯
V.维瓦雷斯
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Infineon Technologies AG
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Infineon Technologies AG
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明涉及半导体器件、制作其的方法和加强其中的管芯的方法。一种半导体器件可包括：管芯，所述管芯包括第一主面、第二主面和侧面，所述侧面连接第一主面和第二主面；至少一个传导柱，所述至少一个传导柱布置在所述管芯的第一主面上并且电耦合到所述管芯；以及绝缘体，所述绝缘体布置在所述管芯的第一主面上，所述绝缘体包括上主面和侧面，其中所述至少一个传导柱被暴露在所述绝缘体的上主面上，并且其中所述管芯的侧面和所述绝缘体的侧面是共面的。

Description

半导体器件、制作其的方法和加强其中的管芯的方法
技术领域
本公开内容涉及到一种半导体器件、一种用于制作半导体器件的方法和一种用于加强半导体器件中的管芯的方法。
背景技术
半导体器件制造商不断努力改进其产品的性能，例如不断努力减小电阻或改进散热特性。改进性能可能包括减小类似例如半导体管芯的半导体器件的尺寸。这转而可能引起处置（handling）问题，因为较小的产品可能不太耐用。此外，可能更难以将较小的半导体器件电连接到例如电路板。可能期望将半导体器件的改进的性能与良好的耐用性以及容易处置相组合。
发明内容
多个方面涉及一种半导体器件，该半导体器件包括：管芯，该管芯包括第一主面、第二主面和侧面，所述侧面连接第一主面和第二主面；至少一个传导柱，所述至少一个传导柱布置在该管芯的第一主面上并且电耦合到该管芯；以及绝缘体，所述绝缘体布置在该管芯的第一主面上，所述绝缘体包括上主面和侧面，其中所述至少一个传导柱被暴露在该绝缘体的上主面上，并且其中该管芯的侧面和该绝缘体的侧面是共面的。
多个方面涉及一种制作半导体器件的方法，该方法包括：提供包括第一主面、第二主面以及侧面的管芯，所述侧面连接第一主面和第二主面；在该管芯的第一主面上布置至少一个传导柱，并且将所述至少一个传导柱电耦合到该管芯；以及在该管芯的第一主面上布置绝缘体，该绝缘体包括上主面和侧面，其中该管芯的侧面和该绝缘体的侧面是共面的。
多个方面涉及一种使用绝缘体来加强半导体器件中的管芯的方法，其中该管芯包括第一主面、第二主面以及侧面，所述侧面连接第一主面和第二主面，其中至少一个传导柱布置在该管芯的第一主面上并且电耦合到该管芯，其中所述绝缘体包括上主面和侧面，其中所述至少一个传导柱被暴露在所述绝缘体的上主面上，并且其中该管芯的侧面和所述绝缘体的侧面是共面的。
附图说明
附图图解说明了实例并且与描述一起用于解释本公开内容的原理。本公开内容的其他实例和许多预期的优点将容易被领会到，因为通过参考以下详细描述，本公开内容的这些其他实例和许多预期的优点变得更好理解。附图的要素不一定相对于彼此成比例。相似的参考数字指定相对应的类似部分。
图1示出了根据本公开内容的半导体器件的示意性侧视图。
图2示出了根据本公开内容的包括布置在衬底上的半导体器件的装置的示意性侧视图。
图3A至图3I示出了在根据用于制作半导体器件的方法的实例的各种制作阶段中的半导体器件的示意性侧视图。
图4A至图4H示出了在根据用于制作半导体器件的方法的另一实例的各种制作阶段中的半导体器件的示意性侧视图。
图5示出了根据本公开内容的用于制作半导体器件的方法的流程图。
具体实施方式
虽然可关于若干实现方式中的仅一个公开了实例的特定特征或方面，但是除非具体地另外指出或除非在技术上受到限制，如对于任何给定的或特定的应用可能是期望的和有利的那样，这样的特征或方面可与其他实现方式的一个或多个其他特征或方面相组合。此外，就在详细描述或权利要求书中使用术语“包含”、“具有”、“带有”或这些术语的其他变型而言，这样的术语意图以类似于术语“包括”的方式而是包含性的。可使用术语“耦合的”和“连接的”连同这些术语的衍生词。应该理解的是，这些术语可用于指示两个元件彼此协作或相互作用，而不管这两个元件是直接物理接触或电接触，还是这两个元件彼此不直接接触；可在“接合的”、“附接的”或“连接的”元件之间提供介入的元件或层。而且，术语“示例性的”仅仅意味着作为实例，而不是最好的或最佳的。
下面进一步描述的（一个或多个）半导体管芯可以是不同类型的，可通过不同的技术来制造，并且可包括例如集成电气电路、电光电路或机电电路和/或无源的、逻辑集成电路、控制电路、微处理器、存储器件等。（一个或多个）半导体管芯可包括水平晶体管结构或垂直晶体管结构。
（一个或多个）半导体管芯可以由例如Si、SiC、SiGe、GaAs、GaN的特定半导体材料来制造，或者由任何其他半导体材料来制造。本发明中考虑的（一个或多个）半导体管芯可以是薄的。
半导体管芯可具有接触垫（或电极），所述接触垫（或电极）允许与包含在半导体管芯中的集成电路进行电接触。这些接触垫可全部布置在半导体管芯的仅一个主面处，或者布置在半导体管芯的两个主面处。这些接触垫可包括施加到半导体管芯的半导体材料的一个或多个接触垫金属层。接触垫金属层可被制造成具有任何期望的几何形状和任何期望的材料成分。例如，这些接触垫金属层可包括如下材料或者由如下材料制成：所述材料选自Cu、Ni、NiSn、Au、Ag、Pt、Pd、这些金属中的一种或多种的合金、导电有机材料或导电半导体材料构成的组。
半导体管芯可用如下面进一步描述的绝缘体来覆盖。绝缘体可被配置为加强半导体管芯。绝缘体可以是电绝缘的。绝缘体可包括如下材料或者由如下材料制成：任何适当的模制化合物或环氧树脂或塑料或聚合物材料、诸如例如硬塑（duroplastic）、热塑或热固材料或层压材料（预浸材料）；并且可例如包含填充材料。可采用各种技术来用绝缘体覆盖半导体管芯，例如采用模制或层压。可使用热和/或压力来施加绝缘体。
在下文中，描述了布置在半导体管芯上的传导柱。传导柱可以是导电的，并且可包括任何合适的材料或由任何合适的材料构成。例如，传导柱可包括类似Cu、Sn或Ag的金属或由类似Cu、Sn或Ag的金属构成。传导柱可包括焊料或由焊料构成。传导柱可包括石墨烯或由石墨烯构成。传导柱可使用任何合适的制作方法来制作。例如，可使用光刻工艺和镀敷工艺。根据另一实例，可使用焊接工艺。下面进一步描述示例性制作方法。
在若干实例中，层或层堆叠被施加到彼此，或者材料被施加或沉积到层上。应该领会到的是，任何如“施加的”或“沉积的”这样的术语意味着在字面上涵盖将层施加到彼此上的所有种类和技术。特别地，这些术语意味着涵盖其中层作为整体立即被施加的技术，类似例如层压技术，以及涵盖其中层以顺序方式沉积的技术，类似例如溅射、镀敷、模制、CVD、3D打印等。
图1示出了根据本公开内容的半导体器件100的实例。半导体器件100包括管芯或半导体管芯110、绝缘体120和至少一个传导柱130。管芯110包括第一主面111、第二主面112以及侧面113，所述侧面113连接第一主面111和第二主面112。绝缘体包括上主面121、下主面122以及侧面123，所述侧面123连接上主面121和下主面122。传导柱130包括顶面131和底面132。
管芯110的第一主面111和绝缘体120的下主面122可以是共面的。第一主面111和下主面122中的一个或多个与传导柱130的底面可以是共面的。绝缘体120的上主面121和传导柱130的顶面131可以是共面的。管芯的侧面113和绝缘体120的侧面123可以是共面的。
半导体器件100可具有任何合适的长度l，例如具有大约2mm的长度l、具有大约4mm的长度l、具有大约6mm的长度l、具有大约8mm的长度l、具有大约1cm的长度l、具有大约1.5cm的长度l、具有大约2cm的长度l或具有大于2cm的长度l。管芯110可具有任何合适的厚度t1，例如具有小于或大约20μm的厚度t1、具有小于或大约30μm的厚度t1、具有小于或大约40μm的厚度t1、具有小于或大约50μm的厚度t1、具有小于或大约60μm的厚度t1或具有大于60μm的厚度t1。厚度t1不大于60μm的管芯可被称为“薄”管芯。然而，管芯110也可以是“厚”管芯，意味着厚度大于60μm的管芯，例如厚度大于或大约100μm的管芯、厚度大于或大约150μm的管芯、厚度大于或大约200μm的管芯、厚度大于或大约400μm的管芯、厚度大于或大约600μm的管芯、厚度大于或大约725μm的管芯、厚度大于或大约800μm的管芯或厚度大于800μm的管芯。绝缘体120（和传导柱130）可具有任何合适的厚度，例如具有小于或大约30μm的厚度t2、具有小于或大约60μm的厚度t2、具有小于或大约75μm的厚度t2、具有小于或大约90μm的厚度t2、具有小于或大约120μm的厚度t2、具有小于或大约150μm的厚度t2、具有小于或大约180μm的厚度t2或者具有大于180μm的厚度t2。传导柱130可具有任何合适的直径d，例如具有小于或大约50μm的直径d、具有小于或大约80μm的直径d、具有小于或大约100μm的直径d、具有小于或大约120μm的直径d、具有小于或大约150μm的直径d或者具有大于150μm的直径d。
传导柱130可具有任何合适的形状。例如，传导柱130如从顶部看可以是圆形的、方形的或矩形的。
半导体器件100还可包括布置在管芯110的第二主面112上的背侧金属化层（图1中未示出）。背侧金属化层可以是管芯110的背侧金属化。背侧金属化层可包括任何合适的一种或多种金属，并且可包括一个单层或若干层。背侧金属化层可例如包括具有Au或Ag涂饰（finish）的一个或多个金属层。
背侧金属化层还可包括氧化防止层（oxidation prevention layer）。背侧金属化层可具有任何合适的厚度，并且与厚度t1或t2相比可以是薄的。例如，背侧金属化层可具有小于5μm的厚度、具有小于1μm的厚度或具有小于600nm的厚度。
半导体器件100还可包括布置在传导柱130的顶面131上的附加层（图1中未示出）。附加层可仅仅布置在顶面131上，或者该附加层可既布置在柱130的顶面131上又布置在绝缘体120的上主面121上。附加层可薄于500nm、薄于300nm、薄于200nm、或者薄于100nm。
附加层可被配置为充当防止传导柱130的氧化的氧化防止层。附加层可被配置为充当允许类似夹子或线接合的电连接元件耦合（例如焊接）到传导柱130的顶面131的粘合促进层（adhesion promotion layer）。根据实例，附加层可以是焊料层。附加层可以是金属层。附加层可包括单个金属层或多于一个金属层。
管芯110可在其第一主面111上包括至少一个接触垫（图1中未示出）。至少一个接触垫可布置在传导柱130的底面132下面，并且可电耦合到传导柱130。因此，传导柱130可充当针对接触垫的电连接器。根据实例，传导柱130被布置在管芯的第一主面111上的每个接触垫上。
根据半导体器件100的实例，绝缘体120和一个或多个传导柱130不是布置在第一主面111上方，而是布置在第二主面112上方，并且可特别地布置在背侧金属化层上方。（一个或多个）传导柱130可电耦合到背侧金属化层。因此，根据半导体器件100的这个实例，包括接触垫的第一主面111被暴露，并且可选地包括背侧金属化层的第二主面112被绝缘体120和（一个或多个）传导柱130覆盖。
根据半导体器件100的又一实例，第一主面111被第一绝缘体和一个或多个第一传导柱覆盖，并且第二主面112被第二绝缘体和一个或多个第二传导柱覆盖。
由于绝缘体120的存在，并且由于传导柱130充当针对在管芯的第一主面111上的电极的连接器，所以半导体器件100基本上可类似厚度为t1+t2的裸管芯地来处置，意味着可以使用与用于厚度为t1+t2的裸管芯的那些工艺相同的工艺来将半导体器件100附接到板以及将半导体器件100电耦合到板。然而，由于管芯110的厚度较小，所以管芯110（以及因此半导体器件100）的电特性可能比厚度为t1+t2的裸管芯的那些电特性更好（例如，更低的电阻）。同时，绝缘体加强了薄管芯110，使得该薄管芯110展现出与厚裸管芯（厚度为t1+t2的管芯）相当的耐用性。因此，半导体器件100将薄管芯的改进的电性能与厚管芯的易用性相组合。
图2示出了装置200，该装置200包括衬底210和半导体器件220，该半导体器件220布置在衬底210上并且通过连接器230电连接到衬底210，其中连接器230附接到传导柱130，特别地附接到传导柱130的顶面131。半导体器件220可以是半导体器件100的实例，并且为了简洁起见，避免了特征的重复。
图2中所示出的连接器230是接合线，然而，可使用任何其他合适的连接器，例如使用夹子。
传导柱130可以任何合适的间距p间隔开，例如以大约200μm的间距p间隔开。间距p可与在管芯110的第一主面111上的接触垫之间的距离相对应，其中传导柱130被布置在接触垫上。
半导体器件220可使用粘合层240安装在衬底210上，所述粘合层240布置在管芯110的第二主面112和衬底210之间。粘合层240可例如包括胶或焊料，并且可被配置为允许在管芯110中产生的热通过粘合层240有效地耗散到衬底210中。
根据实例，装置200包括包封半导体器件220的包封体（图2中未示出）。包封体还可包封连接器230。可在半导体器件220已经附接到衬底210之后并且在半导体器件220已经使用连接器230电连接到衬底210之后形成包封体。包封体可例如包括模制物或层压件，或者由模制物或层压件构成。
在下文中，关于图3A至图3I，示出了根据本公开内容的用于制作类似半导体器件100的半导体器件的方法300的实例。
图3A示出了管芯110，该管芯110在该管芯110的第一主面111上包括接触垫114。在第一主面111上制作一个或多个金属化层115。一个或多个金属化层115可以是凸点下金属化层（UBM，under bump metallization）。
然后可执行光刻工艺（图3B）。例如，在一个或多个金属化层115上面提供光致抗蚀剂层。使用合适的光掩模对光致抗蚀剂层进行曝光，并且随后对光致抗蚀剂层进行显影，以便制作光致抗蚀剂结构310，该光致抗蚀剂结构310在要制作传导柱的地方包括孔311。
图3C示出了在图3B的孔311中制作的传导柱130。制作传导柱130可包括镀敷工艺，例如Cu镀敷。
图3D示出了在去除光致抗蚀剂结构310之后的管芯110和传导柱130。
然后（图3E），可使用合适的刻蚀工艺来刻蚀一个或多个金属化层115，使得一个或多个金属化层115仅保留在传导柱130的底面132下面。
图3F示出了绝缘体120的制作，所述绝缘体120例如可使用模制工艺或层压工艺而被施加到管芯的第一主面111上。如在图3F中所示出的那样，绝缘体120最初可覆盖传导柱130的顶面131。然而，绝缘体120也可以使得该绝缘体120不覆盖传导柱130的顶面131这样的方式来制作。
如在图3G中所示出的那样，可使用去除工艺来去除过量的绝缘体材料和过量的传导柱材料中的一个或多个。去除工艺可包括在绝缘体120的上主面121和传导柱130的顶面131处的平坦化工艺或研磨工艺。也可将包括上主面121和顶面131的表面称为半导体器件的正侧。
如在图3H中所示出的那样，可在管芯的第二主面112处例如使用背侧研磨工艺来使管芯110变薄。在变薄之后，管芯110可具有如关于图1所描述的厚度t1。在变薄之前，管芯可具有任何合适的厚度，例如具有标准晶片的厚度。在变薄之前，管芯可例如具有大约725μm的厚度。
图3I示出了可选地可在管芯的第二主面112上制作背侧金属化层140。背侧金属化层140的施加可例如包括物理气相沉积（PVD）工艺。
方法300还可包括在传导柱130的顶面131上形成附加层。在已经执行了关于图3G所描述的去除工艺之后、但是例如在执行图3H中所示出的工艺之前，或者在执行图3I中所示出的工艺之前，或者在执行图3I中所示出的工艺之后，可形成该附加层。
根据实例，方法300的各个单独的工艺步骤可按时间顺序以在图3A至图3I中所示出的次序来执行。根据另一实例，一些工艺步骤可比关于图3A至图3I所示出的工艺步骤更早或者更晚地执行。例如，关于图3H所示出的变薄工艺步骤可更早地执行，例如作为方法300的第一工艺步骤来执行。
根据实例，方法300是在整个晶片上而不是在单片化的管芯110上执行的成批处理方法。换句话说，管芯110在执行方法300之前可尚未被单片化，而是仍然可以是晶片的部分，并且在晶片的管芯110的部分或全部上执行方法300。根据另一实例，在单片化的管芯110上执行方法300的步骤中的一些或全部。
关于图4A至图4H，示出了用于制作类似半导体器件100的半导体器件的另一示例性方法400。方法400可与方法300相对应，并且可包括相同或类似的工艺步骤。
图4A：管芯110被提供，并且被布置在第一临时载体410上，其中管芯的第一主面111面向第一临时载体。第一临时载体410可包括粘合带，并且管芯110可附接到该粘合带。根据实例，管芯110也可以是整个晶片，并且方法400可以是在整个晶片上执行的成批处理方法。
图4B：可在管芯的第二主面112上执行变薄工艺、类似背侧研磨工艺。在变薄之前，管芯110可例如具有大约725μm的厚度t1，并且在变薄之后，管芯110可具有大约60μm的厚度t1。
图4C：可在管芯的第二主面112上制作背侧金属化层140。
图4D：管芯110可被布置在（例如附接到）第二临时载体420（例如，包括粘合箔的第二临时载体420）上，其中管芯的第二主面112面向第二临时载体420，并且管芯110可（随后）从第一临时载体410去除。
图4E：可使用光刻工艺来在管芯的第一主面111上制作光致抗蚀剂结构310。
图4F：可在管芯的第一主面111上，例如在管芯110的接触垫上方，形成传导柱130。可去除光致抗蚀剂结构310。
图4G：可在管芯的第一主面111上形成绝缘体120。可使用平坦化工艺来从绝缘体的上主面121和传导柱的顶面131去除过量材料。
图4H：可在传导柱的顶面131上形成附加层430。半导体器件100可被单片化。可从第二临时载体420去除半导体器件100。
根据实例，方法400的工艺步骤可以在图4A至图4H中所示出的按时间顺序的次序来执行。根据另一实例，可使用工艺步骤的任何其他合适的按时间顺序的次序。
根据实例，可在已经实现了关于图4G所描述的绝缘体形成之后执行关于图4B所描述的变薄工艺和关于图4C所描述的制作背侧金属化层140的工艺。
图5示出了用于制作类似半导体器件100的半导体器件的示例性方法500的流程图。方法500可与方法300或400相对应。
方法500包括：第一方法步骤501，提供包括第一主面、第二主面以及侧面的管芯，所述侧面连接第一主面和第二主面；第二方法步骤502，在管芯的第一主面上布置至少一个传导柱，并且将至少一个传导柱电耦合到管芯；以及第三方法步骤503，在管芯的第一主面上布置绝缘体，该绝缘体包括上主面和侧面。
方法步骤501、502和503可按照所描述的次序来执行。方法500可包括附加的方法步骤，例如包括关于图3A至图3I和图4A至图4H所描述的方法步骤。
虽然已经关于一个或多个实现方式图解说明和描述了本公开内容，但是在不背离所附权利要求的精神和范围的情况下，可对所图解说明的实例做出更改和/或修改。特别地，对于由上面描述的部件或结构（组件、器件、电路、系统等）执行的各种功能，除非另外指示，否则用于描述这样的部件的术语（包含提及“装置”）意图对应于执行所描述的部件的指定功能的任何部件或结构（例如，在功能上等同的任何部件或结构），即使在结构上不等同于执行本公开内容的在本发明所图解说明的示例性实现方式中的功能的公开结构也如此。

Claims (20)

1.一种半导体器件，其包括：
管芯，所述管芯包括第一主面、第二主面和侧面，所述侧面连接所述第一主面和所述第二主面；
至少一个传导柱，所述至少一个传导柱布置在所述管芯的所述第一主面上，所述至少一个传导柱通过镀敷工艺来沉积并且电耦合到所述管芯；以及
绝缘体，所述绝缘体布置在所述管芯的所述第一主面上，其中所述绝缘体包括上主面和侧面，并且所述绝缘体的所述上主面与所述至少一个传导柱的顶面共面；以及
布置在所述至少一个传导柱的所述顶面上的金属层；
其中，所述管芯的所述侧面和所述绝缘体的所述侧面是共面的。
2.根据权利要求1所述的半导体器件，其中，所述至少一个传导柱包括Cu、Sn、Ag或石墨烯中的一种或多种，或者由Cu、Sn、Ag或石墨烯中的一种或多种制成。
3.根据权利要求1或权利要求2所述的半导体器件，其中，所述至少一个传导柱电耦合到所述管芯的接触垫。
4.根据前述权利要求中的一项所述的半导体器件，其中，所述绝缘体包括聚合物、模制化合物、环氧树脂和填充材料中的一种或多种。
5.根据前述权利要求中的一项所述的半导体器件，其中，所述至少一个传导柱具有垂直于所述管芯的所述第一主面来测量为大约75μm的厚度，以及具有平行于所述管芯的所述第一主面来测量为大约100μm的直径。
6.根据前述权利要求中的一项所述的半导体器件，其中，所述绝缘体具有垂直于所述管芯的所述第一主面来测量为大约75μm的厚度。
7.根据前述权利要求中的一项所述的半导体器件，其中，所述金属层薄于200nm。
8.根据前述权利要求中的一项所述的半导体器件，还包括布置在所述管芯的所述第二主面上的背侧金属化层。
9.根据权利要求8所述的半导体器件，其中，所述背侧金属化层包括Au和Ag中的一种或多种。
10.根据前述权利要求中的一项所述的半导体器件，其中所述金属层通过镀敷工艺来沉积或通过CVD来沉积。
11.根据权利要求1所述的半导体器件，其中，所述金属层是被配置为防止所述至少一个传导柱氧化的氧化防止层。
12.一种用于制作半导体器件的方法，其包括：
提供包括第一主面、第二主面和侧面的管芯，所述侧面连接所述第一主面和所述第二主面；
在所述管芯的所述第一主面上通过镀敷工艺沉积至少一个传导柱，并且将所述至少一个传导柱电耦合到所述管芯；
在所述管芯的所述第一主面上布置绝缘体，其中所述绝缘体包括上主面和侧面，并且所述绝缘体的所述上主面与所述至少一个传导柱的顶面共面；以及
在所述至少一个传导柱的所述顶面上沉积金属层；
其中，所述管芯的所述侧面和所述绝缘体的所述侧面是共面的。
13.根据权利要求12所述的方法，还包括：
使所述绝缘体的所述上主面和所述至少一个传导柱的顶面平坦化。
14.根据权利要求12或13所述的方法，还包括：
使所述管芯变薄。
15.根据权利要求14所述的方法，其中，使所述管芯变薄包括研磨所述管芯的所述第二主面。
16.根据权利要求12至15中的一项所述的方法，还包括：
在所述管芯的所述第二主面上形成背侧金属化层。
17.根据权利要求12至16中的一项所述的方法，其中沉积所述金属层包括镀敷工艺或CVD。
18.根据权利要求12至17中的一项所述的方法，其中，在所述管芯的所述第一主面上布置所述至少一个传导柱包括光刻工艺。
19.一种用于在使用绝缘体的情况下加强半导体器件中的管芯的方法，
其中，所述管芯包括第一主面、第二主面和侧面，所述侧面连接所述第一主面和所述第二主面；
其中，至少一个传导柱通过镀敷工艺沉积在所述管芯的所述第一主面上并且电耦合到所述管芯；
其中，所述绝缘体包括上主面和侧面，并且所述绝缘体的所述上主面与所述至少一个传导柱的顶面共面；
其中，在所述至少一个传导柱的所述顶面上布置金属层；并且
其中，所述管芯的所述侧面和所述绝缘体的所述侧面是共面的。
20.根据权利要求19所述的方法，其中，所述金属层通过镀敷工艺沉积，或者通过CVD沉积。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5986338A (en) * 1995-08-03 1999-11-16 Nissan Motor Co., Ltd. Assembly of semiconductor device
US20130241071A1 (en) * 2012-03-16 2013-09-19 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Compliant Conductive Interconnect Structure in Flipchip Package
US20140346669A1 (en) * 2012-08-14 2014-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of manufacturing the same
CN104620378A (zh) * 2012-03-05 2015-05-13 康宁股份有限公司 包括玻璃中间层的三维集成电路及其制备方法
CN105990291A (zh) * 2015-03-16 2016-10-05 台湾积体电路制造股份有限公司 用于管芯探测的结构

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3423245B2 (ja) 1999-04-09 2003-07-07 沖電気工業株式会社 半導体装置及びその実装方法
DE102004030042B4 (de) 2004-06-22 2009-04-02 Infineon Technologies Ag Halbleiterbauelement mit einem auf einem Träger montierten Halbleiterchip, bei dem die vom Halbleiterchip auf den Träger übertragene Wärme begrenzt ist, sowie Verfahren zur Herstellung eines Halbleiterbauelementes
JP5141076B2 (ja) 2006-06-05 2013-02-13 株式会社デンソー 半導体装置
US9202715B2 (en) * 2010-11-16 2015-12-01 Stats Chippac Ltd. Integrated circuit packaging system with connection structure and method of manufacture thereof
JP2013149834A (ja) 2012-01-20 2013-08-01 Toyota Motor Corp 半導体装置
US9177899B2 (en) * 2012-07-31 2015-11-03 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
US10068844B2 (en) * 2015-09-30 2018-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure and method of forming

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5986338A (en) * 1995-08-03 1999-11-16 Nissan Motor Co., Ltd. Assembly of semiconductor device
CN104620378A (zh) * 2012-03-05 2015-05-13 康宁股份有限公司 包括玻璃中间层的三维集成电路及其制备方法
US20130241071A1 (en) * 2012-03-16 2013-09-19 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Compliant Conductive Interconnect Structure in Flipchip Package
US20140346669A1 (en) * 2012-08-14 2014-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of manufacturing the same
CN105990291A (zh) * 2015-03-16 2016-10-05 台湾积体电路制造股份有限公司 用于管芯探测的结构

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