CN108369955A - 用于场效应晶体管的经组合源极与基极触点 - Google Patents

用于场效应晶体管的经组合源极与基极触点 Download PDF

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CN108369955A
CN108369955A CN201780004314.0A CN201780004314A CN108369955A CN 108369955 A CN108369955 A CN 108369955A CN 201780004314 A CN201780004314 A CN 201780004314A CN 108369955 A CN108369955 A CN 108369955A
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base stage
source electrode
implantation material
effect transistor
electrode implantation
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格雷戈里·迪克斯
丹·格里姆
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Microchip Technology Inc
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Abstract

本发明涉及半导体装置。本发明的教示可以金属氧化物半导体场效应晶体管MOSFET及其制造方法来体现。一些实施例可包含：在外延层内形成基极；植入延伸到所述基极中的源极植入物，其中所述外延层、所述基极及所述源极植入物形成连续平面表面；在所述连续平面表面上沉积绝缘层，形成与所述外延层及所述基极两者接触的栅极；穿过所述绝缘层打通触点凹槽以暴露所述源极植入物的中心部分；在所述绝缘层的顶部上所述源极植入物的经暴露部分上方沉积一层光致抗蚀剂；在所述光致抗蚀剂中图案化出一组条带，每一条带垂直于所述触点凹槽；用对所述绝缘层具选择性的蚀刻化学品蚀刻半导体；及用导电材料填充所述触点凹槽，形成基极‑源极触点凹槽，所述基极‑源极触点凹槽穿过所述绝缘层到达所述源极植入物的表面且包括彼此间隔开、穿过所述源极植入物到达所述基极中的多个区段。

Description

用于场效应晶体管的经组合源极与基极触点
相关专利申请案
本申请案主张2016年3月29日提出申请的第62/314,870号美国临时专利申请案的优先权，所述美国临时专利申请案据此出于所有目的以引用的方式并入本文中。
技术领域
本发明涉及半导体装置。本发明的教示可以金属氧化物半导体场效应晶体管(MOSFET)及其制造方法来体现。
背景技术
功率MOSFET包含经沉积以使源极元件彼此通常并联连接且使漏极元件彼此通常并联连接的金属导线。通常，金属膜沉积在半导体晶片上的电介质层上方。金属膜经图案化且经蚀刻以留下所需金属导线。金属导线使用通孔来与各种作用区域(例如，漏极区域、源极区域及/或栅极)接触。通孔是预先蚀刻于电介质层中接着用例如钨的导体填充(例如，使用化学气相沉积或CVD)的孔。针对较复杂连接，额外金属层可通过额外绝缘层而分离且通过穿过其的其它通孔而彼此连接。标题为“具有经改进金属触点的功率MOS晶体管(PowerMOS Transistor with Improved Metal Contact)”的第8,937,351号美国专利与MOSFET有关且据此以其全文引用的方式并入。
图1A是展示穿过现有技术MOSFET 100的一部分截取的横截面的图式，所述现有技术MOSFET具有N型外延层110、安置在N型外延层中的P型基极120及植入到基极120中的N型源极植入物130。MOSFET 100还包含栅极140及连接基极120与源极植入物130的触点150。触点150包括填充穿过层160及源极植入物130延伸到基极120中的通孔的导体。
图1B展示沿着图1A的线1B的侧视图，其是垂直于图1A的横截面所截取的MOSFET100的另一横截面。如图1B中可见，每一触点150沿着触点150的底部156且沿着触点150的侧的下部部分154与基极120连接。触点150与源极植入物130之间的连接是在触点150的侧部分152处、沿着源极植入物130的厚度。
发明内容
本发明的教示可以金属氧化物半导体场效应晶体管(MOSFET)及其制造方法来体现。一些实施例可包含用于制造具有晶体管单元的场效应晶体管的方法。
在一些实施例中，一种方法可包含：在外延层内沉积基极；植入延伸到所述基极中的源极植入物，其中所述外延层、所述基极及所述源极植入物形成连续平面表面；在所述连续平面表面上沉积绝缘层，形成与所述外延层及所述基极两者接触的栅极；穿过所述绝缘层打通触点凹槽以暴露所述源极植入物的中心部分；在所述绝缘层的顶部上、所述源极植入物的经暴露部分上方沉积一层光致抗蚀剂；在所述光致抗蚀剂中图案化出一组条带，每一条带垂直于所述触点凹槽；用对所述绝缘层具选择性的蚀刻化学品蚀刻所述组条带；及用导电材料填充所述触点凹槽，形成基极-源极触点凹槽，所述基极-源极触点凹槽穿过所述绝缘层到达所述源极植入物的表面且包括彼此间隔开、穿过所述源极植入物到达所述基极中的多个区段。
在一些实施例中，所述多个区段中的每一者等距间隔开。
在一些实施例中，所述导电材料是金属。
在一些实施例中，所述多个区段包括穿过所述源极植入物到达所述基极中的通孔。
在一些实施例中，所述多个区段各自具有矩形占用面积。
在一些实施例中，所述多个区段各自具有圆形占用面积。
在一些实施例中，所述基极包括p型半导体且所述源极植入物包括n型半导体。
在一些实施例中，所述场效应晶体管包括功率金属氧化物半导体场效应晶体管。
一些实施例可包含一种具有晶体管单元的场效应晶体管。所述场效应晶体管可包含：基极，其沉积在外延层内；源极植入物，其延伸到所述基极中，其中所述外延层、所述基极及所述源极植入物形成连续平面表面；栅极，其与所述外延层及所述基极两者接触；及触点凹槽，其填充有导电材料，形成基极-源极触点凹槽，所述基极-源极触点凹槽穿过绝缘层到达所述源极植入物的表面且包括彼此间隔开、穿过所述源极植入物到达所述基极中的多个区段。
在一些实施例中，所述多个区段中的每一者等距间隔开。
在一些实施例中，所述导电材料是金属。
在一些实施例中，所述多个区段包括穿过所述源极植入物到达所述基极中的通孔。
在一些实施例中，所述多个区段各自具有矩形占用面积。
在一些实施例中，所述多个区段各自具有圆形占用面积。
一些实施例可包含一种装置，所述装置包括：壳体，其含有微控制器及至少一个场效应晶体管，所述至少一个场效应晶体管可包括多个单元，所述单元包含：基极，其沉积在外延层内；源极植入物，其延伸到所述基极中，其中所述外延层、所述基极及所述源极植入物形成连续平面表面；栅极，其与所述外延层及所述基极两者接触；及触点凹槽，其填充有导电材料，形成基极-源极触点凹槽，所述基极-源极触点凹槽穿过绝缘层到达所述源极植入物的表面且包括彼此间隔开、穿过所述源极植入物到达所述基极中的多个区段。
在一些实施例中，所述微控制器形成于第一芯片上；所述至少一个场效应晶体管形成于第二芯片上；且所述第一芯片及所述第二芯片通过线接合而与所述壳体连接。
在一些实施例中，所述微控制器及所述至少一个场效应晶体管形成于单个芯片上。
在一些实施例中，所述多个区段中的每一者等距间隔开。
在一些实施例中，所述多个区段包括穿过所述源极植入物到达所述基极中的通孔。
附图说明
图1A是展示穿过现有技术MOSFET的一部分截取的横截面的图式；
图1B是展示穿过现有技术MOSFET的一部分垂直于图1A的横截面所截取的横截面的图式；
图2A是展示穿过实例性MOSFET的一部分的横截面的图式，其中在触点与源极植入物之间具有增大的连接；
图2B是展示穿过实例性MOSFET的一部分垂直于图2A的横截面所截取的横截面的图式；
图3A是展示根据本发明的教示的穿过实例性MOSFET的一部分的横截面的图式，其中在触点与源极植入物之间具有增大的连接；
图3B是展示穿过实例性MOSFET的一部分垂直于图3A的横截面所截取的横截面的图式；
图4A-4C是展示可用于制造图3A及3B中所展示的实例性MOSFET的中间工艺步骤的图式；且
图5是展示根据本发明的教示的用于制造MOSFET的实例性方法的流程图。
具体实施方式
本发明的教示可以金属氧化物半导体场效应晶体管(MOSFET)及其制造方法来体现。
图2A是展示穿过实例性MOSFET 200的一部分的横截面的图式，其中在触点与源极植入物之间具有增大的连接区域。图2B是展示穿过实例性MOSFET的一部分垂直于图2A的横截面所截取的横截面的图式。如所展示，触点250延伸穿过通孔以与基极220及源极植入物230两者接触。与MOSFET 100相比，通孔具有不规则形状，从而导致触点250的端部256处的阶梯式下降部分。
通孔形状的改变提供触点250与源极230之间的较大连接区域。触点250(如触点150)在触点250的底部256处且沿着触点250的侧的下部部分254连接到基极220。然而，区域252在触点250上提供明显较大表面区域用于与源极230连接。对于MOSFET100，仅触点150的侧152沿着源极130的厚度连接。相比之下，MOSFET 200还包含沿着源极230的顶部表面的连接。连接表面区域252的增加可需要额外工艺步骤来打通通孔(如所展示)，并且在MOSFET的最终设计中还消耗触点230的额外表面区域。
图3A是展示根据本发明的教示的穿过实例性MOSFET 300的一部分的横截面的图式，其中在触点350与源极植入物330之间具有增大的连接。图3B是展示穿过实例性MOSFET300的一部分垂直于图3A的横截面所截取的横截面的图式。用于制造MOSFET300的通孔具有穿过绝缘层370的凹槽的形状，其中通孔从源极植入物330的表面穿过源极植入物330向下延伸到基极320中，而不是如图2A及2B中所展示对通孔添加步骤。
当用导电材料填充时，所得基极-源极触点凹槽350提供与基极320接触的增大的表面区域。图3B展示沿着源极植入物330的顶部表面的额外表面区域352。在一些实施例中，触点凹槽350沿着每一组邻近通孔之间的源极植入物330的完整范围连接到源极植入物330。MOSFET 300包含具有两个不同高度的单触点凹槽350(例如，填充有钨)，所述单触点凹槽与基极320及源极330两者电连接。与MOSFET 300接触的表面区域不仅是在垂直侧中且组合垂直与水平范围352两者。
图4A-4C是展示可用于制造图3A及3B中所展示的实例性MOSFET 300的中间工艺步骤的图式。
图4A展示在图案化及蚀刻触点凹槽之后的中间状态的一部分。为提供穿过源极植入物330且进入到基极320中的通孔，图案化出并向硅中蚀刻正交凹槽以暴露基极区域。为图案化正交凹槽，可如图4A-4C中所展示使用光致抗蚀剂360。蚀刻工艺与触点凹槽和正交凹槽的交叉点自对准。在蚀刻正交凹槽之后，存在沿着触点凹槽向上及向下的阶梯。图3B展示在用导体350填充之后的具有向上及向下的阶梯的触点凹槽。
图4C展示相同中间状态的俯视图。在图中如所展示，暴露源极植入物330的触点凹槽水平延展且抗蚀剂条带垂直延伸。将执行对硅的选择性蚀刻，其中氧化物与凹部自对准而不需要工艺设备的确切对准。与其它方法相比，本文中所揭示的程序不需要用以增大源极330与触点之间的连接的额外区域。另外，所述程序在提供到源极330的更好连接的同时可对掩模对准不敏感。
在一些实施例中，场效应晶体管包含至少一个或多个晶体管单元。每一单元包括：基极，其在外延层内；源极植入物，其延伸到基极中；绝缘层，其配置于外延层的顶部上且包括覆盖源极植入物与外延层之间的基极的表面区域的至少一个栅极；及基极-源极触点凹槽，其穿过绝缘层到达源极植入物的表面并且包括彼此间隔开且穿过源极植入物到达基极中的多个区段。
在一些实施例中，所述多个区段等距间隔开。可用导电材料填充基极-源极触点凹槽。导电材料可为金属。在一些实施例中，多个区段包括到达基极中的通孔。通孔可各自具有匹配占用面积(例如，正方形、矩形或圆形占用面积)。
图5是展示根据本发明的教示的用于制造MOSFET的实例性方法500的流程图。下文所描述及图5中所展示的实例性实施例不必确切地以所述次序执行且可视需要包含更多或更少步骤。
方法500可包含步骤502，步骤502包含在外延层310内沉积基极320。基极320可包括P型半导体。外延层310可包含N-epi/N+++衬底。
方法500可包含步骤504，步骤504包含植入延伸到基极320中的源极植入物330。源极植入物330可包括N型半导体。在一些实施例中，在步骤504完成之后，外延层310、基极320及源极植入物330形成连续平面表面。
方法500可包含步骤506，步骤506包含在连续平面表面上沉积绝缘层370，形成与外延层310及基极320两者接触的栅极340。
方法500可包含步骤508，步骤508包含穿过绝缘层370打通触点凹槽以暴露源极植入物330的中心部分。
方法500可包含步骤510，步骤510包含在于源极植入物330的经暴露部分上方延伸的绝缘层370的顶部上沉积一层光致抗蚀剂360。
方法500可包含步骤512，步骤512包含在光致抗蚀剂360中图案化出一组条带360a到360f，每一条带垂直于触点凹槽。
方法500可包含步骤514，步骤514包含用对绝缘层370具选择性的蚀刻化学品蚀刻所述组条带。
方法500可包含步骤516，步骤516包含用导电材料填充触点凹槽，形成基极-源极触点凹槽350，所述基极-源极触点凹槽穿过绝缘层370到达源极植入物330的表面且包括彼此间隔开、穿过源极植入物330到达基极320中的多个区段。
尽管已关于各图中所描绘的实施例详细地描述本发明的教示，但所属领域的技术人员将能够在不背离本发明的发明范围的情况下应用除那些实施例之外的这些教示。所述实施例仅是实例且因此不限制所述教示而仅图解说明所述教示。

Claims (26)

1.一种用于制造具有晶体管单元的场效应晶体管的方法，所述方法包括：
在外延层内沉积基极；
植入延伸到所述基极中的源极植入物；
其中所述外延层、所述基极及所述源极植入物形成连续平面表面；
在所述连续平面表面上沉积绝缘层，形成与所述外延层及所述基极两者接触的栅极；
穿过所述绝缘层打通触点凹槽以暴露所述源极植入物的中心部分；
在所述绝缘层的顶部上所述源极植入物的经暴露部分上方沉积一层光致抗蚀剂；
在所述光致抗蚀剂中图案化出一组条带，每一条带垂直于所述触点凹槽；
用对所述绝缘层具选择性的蚀刻化学品蚀刻所述组条带；及
用导电材料填充所述触点凹槽，形成基极-源极触点凹槽，所述基极-源极触点凹槽穿过所述绝缘层到达所述源极植入物的表面且包括彼此间隔开、穿过所述源极植入物到达所述基极中的多个区段。
2.根据权利要求1或3到8中任一权利要求所述的方法，其中所述多个区段中的每一者等距间隔开。
3.根据权利要求1到2或4到8中任一权利要求所述的方法，其中所述导电材料是金属。
4.根据权利要求1到3或5到8中任一权利要求所述的方法，其中所述多个区段包括穿过所述源极植入物到达所述基极中的通孔。
5.根据权利要求1到4或6到8中任一权利要求所述的方法，其中所述多个区段各自具有矩形占用面积。
6.根据权利要求1到4或6到8中任一权利要求所述的方法，其中所述多个区段各自具有圆形占用面积。
7.根据权利要求1到6或8中任一权利要求所述的方法，其中所述基极包括p型半导体且所述源极植入物包括n型半导体。
8.根据权利要求1到7中任一权利要求所述的方法，其中所述场效应晶体管包括功率金属氧化物半导体场效应晶体管。
9.一种具有晶体管单元的场效应晶体管，所述场效应晶体管包括：
基极，其沉积在外延层内；
源极植入物，其延伸到所述基极中；
其中所述外延层、所述基极及所述源极植入物形成连续平面表面；
栅极，其与所述外延层及所述基极两者接触；及
触点凹槽，其填充有导电材料，形成基极-源极触点凹槽，所述基极-源极触点凹槽穿过绝缘层到达所述源极植入物的表面且包括彼此间隔开、穿过所述源极植入物到达所述基极中的多个区段。
10.根据权利要求9或11到16中任一权利要求所述的场效应晶体管，其中所述多个区段中的每一者等距间隔开。
11.根据权利要求9到10或12到16中任一权利要求所述的场效应晶体管，其中所述导电材料是金属。
12.根据权利要求9到11或13到16中任一权利要求所述的场效应晶体管，其中所述多个区段包括穿过所述源极植入物到达所述基极中的通孔。
13.根据权利要求9到12或15到16中任一权利要求所述的场效应晶体管，其中所述多个区段各自具有矩形占用面积。
14.根据权利要求9到12或15到16中任一权利要求所述的场效应晶体管，其中所述多个区段各自具有圆形占用面积。
15.根据权利要求9到14或16中任一权利要求所述的场效应晶体管，其中所述基极包括p型半导体且所述源极植入物包括n型半导体。
16.根据权利要求9到15中任一权利要求所述的场效应晶体管，其进一步为功率金属氧化物半导体场效应晶体管。
17.一种装置，其包括：
壳体，其含有微控制器及至少一个场效应晶体管；
其中所述至少一个场效应晶体管包括多个单元，所述单元包含：
基极，其沉积在外延层内；
源极植入物，其延伸到所述基极中；
其中所述外延层、所述基极及所述源极植入物形成连续平面表面；
栅极，其与所述外延层及所述基极两者接触；及
触点凹槽，其填充有导电材料，形成基极-源极触点凹槽，所述基极-源极触点凹槽穿过绝缘层到达所述源极植入物的表面且包括彼此间隔开、穿过所述源极植入物到达所述基极中的多个区段。
18.根据权利要求17或19到26中任一权利要求所述的装置，其中：
所述微控制器形成于第一芯片上；
所述至少一个场效应晶体管形成于第二芯片上；且
所述第一芯片及所述第二芯片通过线接合而与所述壳体连接。
19.根据权利要求17到18或19到26中任一权利要求所述的装置，其中所述微控制器及所述至少一个场效应晶体管形成于单个芯片上。
20.根据权利要求17到19或21到26中任一权利要求所述的装置，其中所述多个区段中的每一者等距间隔开。
21.根据权利要求17到20或22到26中任一权利要求所述的装置，其中所述多个区段包括穿过所述源极植入物到达所述基极中的通孔。
22.根据权利要求17到21或21到26中任一权利要求所述的装置，其中所述导电材料是金属。
23.根据权利要求17到19或21到26中任一权利要求所述的装置，其中所述多个区段各自具有矩形占用面积。
24.根据权利要求17到19或21到26中任一权利要求所述的装置，其中所述多个区段各自具有圆形占用面积。
25.根据权利要求17到24或26中任一权利要求所述的装置，其中所述基极包括p型半导体且所述源极植入物包括n型半导体。
26.根据权利要求17到25中任一权利要求所述的装置，其中所述场效应晶体管包括功率金属氧化物半导体场效应晶体管。
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