CN108365066B - Light emitting diode and manufacturing method thereof - Google Patents

Light emitting diode and manufacturing method thereof Download PDF

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CN108365066B
CN108365066B CN201810358160.1A CN201810358160A CN108365066B CN 108365066 B CN108365066 B CN 108365066B CN 201810358160 A CN201810358160 A CN 201810358160A CN 108365066 B CN108365066 B CN 108365066B
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layer
sublayer
semiconductor layer
semiconductor
emitting diode
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CN108365066A (en
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林予尧
柯淙凯
曾建元
陈彦志
游俊达
凌硕均
颜政雄
吴欣显
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Epistar Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

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Abstract

The invention discloses a light emitting diode and a manufacturing method thereof. The light emitting diode includes a first semiconductor layer, an active layer on the first semiconductor layer, a second semiconductor layer on the active layer, and a semiconductor contact layer on the second semiconductor layer. The second semiconductor layer comprises a first sublayer and a second sublayer formed on the first sublayer, wherein the material of the second sublayer comprises AlxGa1‑xN(0<x<1) And the surface of the second semiconductor comprises a plurality of irregularly distributed hexagonal holes.

Description

Light emitting diode and manufacturing method thereof
The invention relates to divisional application of Chinese invention patent application (application number: 201310049983.3, application date: 2013, 02 and 08, invention name: a light-emitting diode and a manufacturing method thereof).
Technical Field
The present invention relates to a light emitting diode and a method for manufacturing the same, and more particularly, to improving photoelectric characteristics of a light emitting diode.
Background
Light-emitting diodes (LEDs) used in solid-state lighting devices have good photoelectric characteristics, such as low power consumption, low heat generation, long operating life, shock resistance, small size, fast response speed, and stable output light wavelength, and are therefore widely used in various lighting applications. When the led is turned on, the current passing through the led is called forward operating current (If), and the voltage across the led measured by the forward operating current is called forward voltage (Vf).
The light emitting diode has an advantage of low power consumption, but is more required to have sufficient brightness in daily life. In addition to increasing the number of LEDs used, the operating current of the LEDs can be increased to increase the light intensity of each LED. However, when the forward current of the led is increased, the product of the forward voltage and the forward current is increased, which increases the energy consumed as heat energy. In order to enable the led to be used in a low power consumption condition, and at the same time, to maintain a sufficient light emitting intensity of the led, and to reduce the forward voltage of the led to avoid an excessive product of the forward voltage and the forward current, and to consume excessive energy as heat energy, the led has become an important research direction for promoting the led to be widely used.
The aforementioned light emitting diode may be combined with other elements to form a light emitting device, and the elements in the light emitting device include a submount having a circuit, a solder bonding the light emitting diode to the submount and electrically connecting the substrate of the light emitting diode to the circuit on the submount, and an electrical connection structure electrically connecting the electrode of the light emitting diode to the circuit of the submount. The sub-carrier can be a lead frame or a large-size embedded substrate, so that the circuit planning of the light-emitting device is facilitated and the heat dissipation effect of the light-emitting diode is improved.
Disclosure of Invention
In order to solve the above problems, the present invention provides a light emitting diode, which includes a first semiconductor layer, an active layer on the first semiconductor layer, a second semiconductor layer on the active layer, and a semiconductor contact layer on the second semiconductor layer. The second semiconductor layer comprises a first sublayer and a second sublayer formed on the first sublayer, wherein the material of the second sublayer comprises AlxGa1-xN (0< x <1), and the surface of the second sublayer comprises an irregularly distributed pore structure.
The invention discloses a method for manufacturing a light emitting diode, which comprises the steps of providing a substrate, forming a first semiconductor layer on the substrate, then forming an active layer on the first semiconductor layer, and then forming Al-containing epitaxial layerxGa1-xN(0<x<1) A second semiconductor layer on the active layer; wherein, the surface of the second semiconductor layer comprises irregularly distributed hole structures.
Drawings
FIG. 1 illustrates a first LED stack embodiment disclosed herein;
FIG. 2 illustrates an embodiment of a second semiconductor layer disclosed herein;
FIG. 3 shows a second LED stack embodiment of the present disclosure;
fig. 4 shows an embodiment of a third led stack according to the present disclosure.
Description of the main elements
100. 200, 300 light emitting diode stack
102 substrate
104 superlattice layer
106 first semiconductor layer
108 strained layer
110 active layer
112 electron blocking layer
114 second semiconductor layer
1141 first sublayer
1142 first sublayer
1143 second sublayer
1144 third time layer
1146 second sublayer
116. 118 semiconductor contact layer
120 transparent conductive oxide layer
Detailed Description
FIG. 1 is a cross-sectional view of a first LED stack 100 according to a first embodiment of the present invention, the first LED stack 100 comprising a substrate 102, a superlattice layer 104, a first semiconductor layer 106, an active layer 110, and a second semiconductor layerA semiconductor layer 114, a semiconductor contact layer 116, and a transparent conductive oxide layer 120. The material of the substrate 102 may include Ga, As, Si, C, P, Al, N,
Figure BDA0001635254400000031
Elements such as Zn, O, Li, or combinations thereof, but not limited to these elements, the substrate 102 may be a conductive substrate, an insulating substrate, or a composite substrate, wherein the conductive substrate may be a metal substrate, such as a substrate containing aluminum or silicon; the insulating substrate can be a Sapphire (Sapphire) substrate or a ceramic substrate with heat conduction and insulation; or a composite substrate, for example, combining a conductive material and an insulating material to achieve the purpose of changing the current distribution to solve the current crowding (current crowding) phenomenon or improving the reflection effect on the substrate to reduce the internal light absorption. In addition, the substrate 102 may be a patterned substrate having a pattern on a surface thereof. The superlattice layer 104 is disposed between the substrate 102 and the first semiconductor layer 106, and the superlattice layer 104 is a buffer layer used for reducing stress caused by a difference in lattice constants between the substrate 102 and the first semiconductor layer 106, so as to prevent the epitaxial structure from being damaged or unstable due to the stress between the substrate 102 and the first semiconductor layer 106. In other embodiments, an adhesive layer (not shown) is further included between the substrate 102 and the first semiconductor layer 106 for bonding to strengthen the bonding between the substrate 102 and the first semiconductor layer 106. When the first semiconductor layer 106 is a p-type semiconductor, the second semiconductor layer 114 is an n-type semiconductor with different electrical properties; on the contrary, when the first semiconductor layer 106 is an n-type semiconductor, the second semiconductor layer 114 is a p-type semiconductor with different electrical properties, wherein the first semiconductor layer 106 and the second semiconductor layer 114 can be used as confinement layers. The active layer 110 is located between the first semiconductor layer 106 and the second semiconductor layer 114, and may be a single layer structure or a multiple quantum well layer structure composed of a plurality of well layers and barrier layers to emit light of a specific wavelength. In the present embodiment, the active layer 110 emits a blue light with a dominant wavelength between 440 nm and 470nm, and is a non-coherent light.
A first sub-layer 1141 within the second semiconductor layer 114 and a second sub-layer 1141 over the first sub-layer 1141A sublayer 1143, and a semiconductor contact layer 116 overlying the second sublayer 1143, wherein the composition of the second semiconductor layer 114 comprises a group III-V material, and the material of the second sublayer 1143 is AlxGa1-xN, wherein 0<x<1. The side between the adjacent second sublayer 1143 and the semiconductor contact layer 116 is an irregular surface, as shown in fig. 1, and there is an irregular pore structure on the irregular surface. The irregular surface and irregularly distributed pores are formed by Al in an epitaxial mannerxGa1-xThe second sublayer 1143 of N is formed simultaneously, and the holes are distributed on the irregular surface in an irregular and non-uniform depth pattern. In the present embodiment, Al is formed by epitaxial growthxGa1-xThe N and simultaneously created hole structures are not only distributed on the surface, but also include a plurality of hexagonal hole structures extending downward, wherein at least one of the hexagonal holes extends into the second semiconductor layer 114 (not shown) as a confinement layer.
Above the semiconductor contact layer 116 is a transparent conductive oxide layer 120, and above the transparent conductive oxide layer 120 is an electrode layer (not shown). The material used for the transparent conductive oxide layer 120 may be ITO; the material of the semiconductor contact layer 116 includes a material having a lower energy gap than the second semiconductor layer, such as AlGaN or InGaN, and the energy gap of the semiconductor contact layer 116 can be reduced by heavily doping carriers, so that the semiconductor contact layer 116 forms a good Ohmic contact (Ohmic contact) between the transparent conductive oxide layer 120 and the second semiconductor layer 114.
In this embodiment, the first semiconductor layer 106 has a first lattice constant, the active layer 110 on the first semiconductor layer 106 has a second lattice constant, and the second semiconductor layer 114 on the active layer 110 has a third lattice constant. Since the second lattice constant is larger than the first lattice constant, the active layer 110 is stressed outward from the first semiconductor layer 106, and the epitaxial quality is poor. To improve the stress on the active layer 110, the second semiconductor layer 114 is formed by selecting different materials to have a third lattice constant smaller than the first lattice constant, so as to form the active layer 110The inward stress balances the stress inside the first led stack 100, improving epitaxial quality. In other words, the first semiconductor layer 106 has a first lattice constant between the second lattice constant of the active layer 110 and the third lattice constant of the second semiconductor layer 114 to form a good epitaxial quality and reduce the forward voltage (V) of the first LED stack 100 during operationf)。
In the present embodiment, the second semiconductor layer 114 located above the active layer 110 includes a plurality of sub-layers having different impurity concentrations but the same electrical property, as shown in fig. 2. Of these multiple sublayers, the first sublayer 1142 is closest to the active layer 110, the second sublayer 1146 is on top of the first sublayer 1142, and the third sublayer 1144 is between the first sublayer 1142 and the second sublayer 1146. Wherein the second sublayer 1146 is closest to the semiconductor contact layer 116 and comprises an irregular distribution of pore structures on the outer surface of the second sublayer 1146 closest to the semiconductor contact layer 116. The material of the first and second sub-layers 1142 and 1146 comprises Al, wherein the first and second sub-layers 1142 and 1146 comprise AlyGa1-yN, wherein 0<y<0.3; in another embodiment, in order to match the different lattice constants of the active layer 110 and the semiconductor contact layer 116 adjacent to the second semiconductor layer 114, for example, when the lattice constants of the active layer 110 and the semiconductor contact layer 116 are larger, a smaller value of y is selected to be between 0 and 0.1, so that the first sublayer 1142 and the second sublayer 1146 have larger lattice constants to reduce the relative stress between the two stacked layers. The sub-layers have different impurity concentrations although having the same conductivity, wherein the third sub-layer 1144 has a third impurity concentration between the first impurity concentration of the first sub-layer 1142 and the second impurity concentration of the second sub-layer 1146. In this embodiment, the first impurity concentration is about 5 x 1018㎝3A third impurity concentration of about 3 x 1019㎝3The second impurity concentration is about 1 x 1020㎝3. In addition, the thicknesses of the three sublayers are also different, and the thickness of the third sublayer 1144 is greater than the thicknesses of the first sublayer 1142 and the second sublayer 1146. In another embodiment, the third sub-layer 1144 is made of a material containing no aluminum componentThe material composition, and the first and second sub-layers 1142 and 1146 comprise a composition of aluminum.
As shown in fig. 3, a second led stack 200 according to another embodiment of the present invention includes a substrate 102, a superlattice layer 104, a first semiconductor layer 106, a strained layer 108, an active layer 110, a second semiconductor layer 114, an electron blocking layer 112, a semiconductor contact layer 116, and a transparent conductive oxide layer 120. In the present embodiment, the stress generated between the second semiconductor layer 106 and the substrate 102 due to lattice constant mismatch is reduced by the superlattice layer 104, so as to avoid deformation caused by stress during subsequent formation of a semiconductor stack. When the active layer 110 is a multiple quantum well, a barrier layer closest to the second semiconductor layer 114 includes indium gallium nitride, that is, a barrier layer closest to the first sub-layer 1142 includes indium gallium nitride.
In the present embodiment, a strained layer 108 is formed on the first semiconductor layer 106 before the multiple quantum wells are formed, and in the present embodiment, the material of the strained layer 108 and the active layer 110 are also made of III-V materials, but the impurity concentration of the strained layer 108 is less than that of the active layer 110, so as to reduce the stress generated by dislocation between the multiple quantum wells in the active layer 110 and the first semiconductor layer 106 due to different lattice constants, thereby improving the epitaxial quality of the active layer 110. In this embodiment, the active layer 110 emits a blue light with a dominant wavelength between 440 nm and 470nm, and is a non-coherent light. In the embodiment, the materials of the first semiconductor layer 106, the active layer 110, the second semiconductor layer 114 and the strained layer 108 are selected from stacks of different group III-V materials including Al, In, Ga, N, etc., such as a stack of InGaN and GaN or a stack of AlGaN and InGaN, so that the lattice constant difference between the stacks is within a predetermined range, thereby achieving the effect of reducing the stress between the stacks. The material of the strained layer 108 is a III-V material similar to the active layer 110, but the composition of the composition is different from that of the active layer 110, such that the lattice constant of the strained layer 108 is between the active layer 110 and the first semiconductor layer 106, thereby improving the epitaxial quality of the epitaxial stack grown on the first semiconductor layer 106 and improving the light emitting efficiency.
In this embodiment, the firstThe semiconductor layer 106 is an n-type semiconductor, the second semiconductor layer 114 is a p-type semiconductor, and the electron blocking layer 112 is formed between the active layer 110 and the second semiconductor layer 114, so as to prevent electrons moving from the first semiconductor layer 106 to the active layer 110 from overflowing to the second semiconductor layer 114, which causes the electrons to combine at a position other than the active layer 110 and reduce the light emitting efficiency. To achieve this, the impurity concentration of the electron blocking layer 112 must be higher than that of the second semiconductor layer 114 or the second impurity concentration of the second sub-layer 1146 included in the second semiconductor layer 114, and the material of the electron blocking layer 112 may include a III-V material such as AlzGa1-zN, wherein 0.15<z<0.4, the effect of blocking electrons can be increased by increasing the content of Al.
In fig. 3, the second semiconductor layer 114 may further include a plurality of sublayers made of AlGaN with different Al concentrations, and the sublayers have different lattice constants. The lattice constant of the second semiconductor layer 114 is between the lattice constants of the electron blocking layer 112 and the active layer 110, and the lattice constant of the active layer 110 is greater than the lattice constants of the electron blocking layer 112 and the second semiconductor layer 114, so that the active layer 110 is prevented from directly contacting the second semiconductor layer 114 with a larger lattice constant difference, and the stress caused by the larger lattice constant difference between the active layer 110 and the second semiconductor layer 114 can be improved by the electron blocking layer 112. The stress between the sub-layers with different lattice constants contained in the second semiconductor layer 114 and the adjacent electron blocking layer 112 is not too large, so that the epitaxial quality can be improved and the forward voltage (Vf) of the second led stack 200 can be reduced.
Fig. 4 is a cross-sectional view of a third light emitting diode stack 300, the third light emitting diode stack 300 having a similar structure to the second light emitting diode stack 200 of fig. 3, but with the substrate 102, the first semiconductor layer 106, and the superlattice layer 104 having a larger area than the other layers, such that the other layers cover only a portion of the area of the first semiconductor layer 106, according to another embodiment of the invention. In the third led stack 300, the semiconductor contact layer 118 is formed on the second semiconductor layer 114 and covers at least a portion of the first semiconductor layer 106, and an electrode layer (not shown) may be formed on the semiconductor contact layer 118.
The process of fabricating the led stack 100 according to the embodiment of the invention includes providing a substrate 102, selecting a material having a lattice constant between the lattice constants of the first semiconductor layer 106 and the substrate 102 as a superlattice layer 104 formed on the substrate 102 before forming the first semiconductor layer 106, and in the embodiment of the invention, selecting a III-V material to fabricate the first semiconductor layer 106 and the superlattice layer 104, and adding the superlattice layer 104 to relieve the stress between the substrate 102 and the first semiconductor layer 106. A first semiconductor layer 106 is formed on the superlattice layer 104, and an active layer 110 is formed on the first semiconductor layer 106, wherein the active layer 110 may also be a multiple quantum well structure. Then, a material Al is formed on the active layer 110xGa1-xN, and 0 therein<x<1. Then, a semiconductor contact layer 116 is formed on the second semiconductor layer 114, and a transparent conductive oxide layer 120 is formed on the semiconductor contact layer 116. Wherein the side of the second semiconductor layer 114 closest to the semiconductor contact layer 116 comprises AlxGa1-xN(0<x<1) And irregular planar and planar void-like structures are formed between the second semiconductor layer 114 and the semiconductor contact layer 116, wherein the irregular void-like structures are formed simultaneously when the second semiconductor layer 114 is epitaxially formed and include a hexagonal void structure, wherein at least one of the hexagonal voids extends to the second semiconductor layer 114 (not shown). In this embodiment, the active layer 110 emits a blue light with a dominant wavelength between 440 nm and 470nm, and is a non-coherent light.
As shown in the structure diagram of fig. 2, the second semiconductor layer 114 includes a first sub-layer 1142, a second sub-layer 1146 and a third sub-layer 1144, and the step of forming the second semiconductor layer 114 includes introducing a gas containing Ga and N and an aluminum-containing organometallic gas at a predetermined flow rate to form AlGaN, wherein the process condition of introducing the aluminum-containing organometallic gas is between an ambient temperature of 900 to 1100 ℃ and a pressure rangeAn organic metal gas of 30 to 300sccm is introduced under the condition of 300 to 500Torr, and the organic metal gas containing aluminum may be trimethyl aluminum ((CH) containing aluminum)3)3Al, TMAl). As described above, the first, second, and third sub-layers 1142, 1146, 1144 have different impurity concentrations, so that the concentration of the gas containing the impurities introduced when the second sub-layer 1146 is formed is greater than the concentration of the gas introduced when the first sub-layer 1142 is formed, and then the concentration of the gas containing the impurities introduced when the third sub-layer 1144 is formed is further increased, so that the impurity concentration of each sub-layer increases in a direction away from the active layer 110. In the embodiment of the invention, the second semiconductor layer 114 is a p-type semiconductor, so magnesium dicocene (Mg (C)) is introduced when forming the second semiconductor layer 1145H5)2Magnesocene) to provide magnesium as a doping impurity.
Then, a semiconductor contact layer 116 and a transparent conductive oxide layer 120 are formed on the second semiconductor layer 114, wherein the transparent conductive oxide layer 120 is made of ITO and can serve as a window layer to increase light emission. Then, an electrode layer (not shown) is formed on the transparent conductive oxide layer 120, and when the substrate 102 is made of conductive material, an electrode layer (not shown) is formed on the other side of the substrate 102 opposite to the grown semiconductor stack; alternatively, the substrate 102 is removed, and then the conductive substrate is bonded to the superlattice layer 104, and an electrode layer is formed on the other side of the conductive substrate.
In fig. 3, the difference between the second led stack 200 and the led stack 100 in fig. 1 is that before the active layer 110 of the second led stack 200 is formed, the strained layer 108 is formed on the first semiconductor layer 106, and then the grown epitaxy has better quality because the lattice constant difference between the strained layer 108 and the active layer 110 is smaller when the active layer 110 is formed. Another difference is that the electron blocking layer 112 is formed after the active layer 110 is formed, and then the second semiconductor layer 114 is formed, such that the electron blocking layer 112 is interposed between the active layer 110 and the second semiconductor layer 114, wherein the material of the electron blocking layer 112 may be AlyGa1-yN and 0.15<y<0.4. As previously described, by electron blockingThe addition of layer 112 allows the lattice constant of active layer 110 to be close to that of second semiconductor layer 114, reducing stress between epitaxial layers to improve epitaxial quality and reduce forward voltage of the led layer.
The third led stack 300 of fig. 4 is formed after the second led stack 200 of fig. 3 is formed, and the light emitting stack is etched until a portion of the first semiconductor layer 106 is exposed. Then, a semiconductor contact layer 118 is formed on the exposed portion of the first semiconductor layer 106, such that the semiconductor contact layer 118 at least covers a portion of the first semiconductor layer 106. Then, two electrode layers (not shown) are formed on the transparent conductive oxide layer 120 and the semiconductor contact layer 118 of the third led stack 300 in fig. 4, respectively.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify and change the above-described embodiments without departing from the technical principles and spirit of the present invention. The scope of the invention is therefore indicated by the appended claims.

Claims (10)

1. A light emitting diode, comprising:
a first semiconductor layer;
an active layer on the first semiconductor layer; and
a second semiconductor layer, located over the active layer, comprising:
a first sublayer;
a second sublayer located above the first sublayer; and
a third sublayer located between the first sublayer and the second sublayer,
wherein the material of the second sublayer comprises AlxGa1-xN, wherein 0<x<1, the first sublayer and the second sublayer have the same conductivity, the third sublayer does not contain an aluminum component and the first sublayer and the second sublayer contain an aluminum component, and the surface of the second semiconductor layer comprises a plurality of irregularly distributed hexagonal shapesA cavity.
2. The light emitting diode of claim 1, further comprising a semiconductor contact layer over the second semiconductor layer, wherein the second semiconductor layer comprises a conductivity that is p-type.
3. The light emitting diode of claim 1, wherein the third sublayer has the same conductivity as the second sublayer; and the first sublayer has a first impurity concentration, the second sublayer has a second impurity concentration, the third sublayer has a third impurity concentration, and the second impurity concentration is greater than the first impurity concentration, the third impurity concentration is between the first impurity concentration and the second impurity concentration.
4. The light emitting diode of claim 1, wherein the thickness of the third sublayer is greater than the thickness of the first sublayer and greater than the thickness of the second sublayer.
5. The light-emitting diode of claim 1, further comprising an electron blocking layer interposed between the active layer and the second semiconductor layer, wherein a material of the electron blocking layer comprises AlzGa1-zN, wherein 0.15<z<0.4。
6. The light emitting diode of claim 1, wherein the first sublayer comprises AlyGa1-yN, wherein 0<y<0.3。
7. The light emitting diode of claim 1, wherein 0< x < 0.3.
8. The light emitting diode of claim 1, further comprising a strained layer between the first semiconductor layer and the active layer, the strained layer comprising a group III-V material.
9. The light emitting diode of claim 8, wherein the strained layer has an impurity concentration less than an impurity concentration of the active layer.
10. The light-emitting diode according to claim 2, wherein the second semiconductor layer and the semiconductor contact layer have irregular planes in a cross-sectional view.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102842657A (en) * 2011-06-20 2012-12-26 丰田合成株式会社 Method for producing group III nitride semiconductor light-emitting device
CN102867894A (en) * 2011-07-06 2013-01-09 三星电子株式会社 Nitride semiconductor light emitting device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6657300B2 (en) * 1998-06-05 2003-12-02 Lumileds Lighting U.S., Llc Formation of ohmic contacts in III-nitride light emitting devices
TWI236160B (en) * 2003-11-25 2005-07-11 Super Nova Optoelectronics Cor GaN light emitted diode with high luminescent efficiency and the manufacture method
TWI229464B (en) * 2004-02-04 2005-03-11 South Epitaxy Corp Structure of light emitting diode
US7462884B2 (en) * 2005-10-31 2008-12-09 Nichia Corporation Nitride semiconductor device
US8013320B2 (en) * 2006-03-03 2011-09-06 Panasonic Corporation Nitride semiconductor device and method for fabricating the same
US20080277678A1 (en) * 2007-05-08 2008-11-13 Huga Optotech Inc. Light emitting device and method for making the same
KR101459752B1 (en) * 2007-06-22 2014-11-13 엘지이노텍 주식회사 Semiconductor light emitting device and fabrication method thereof
JP5310604B2 (en) * 2010-03-05 2013-10-09 豊田合成株式会社 Semiconductor light emitting device manufacturing method, semiconductor light emitting device, lamp, electronic device, and mechanical device
CN102157654B (en) * 2011-03-30 2013-09-25 重庆大学 Inverted mounting LED chip based on double-faced shrinkage pool substrate and component gradual change buffer layer
US8648384B2 (en) * 2011-07-25 2014-02-11 Lg Innotek Co., Ltd. Light emitting device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102842657A (en) * 2011-06-20 2012-12-26 丰田合成株式会社 Method for producing group III nitride semiconductor light-emitting device
CN102867894A (en) * 2011-07-06 2013-01-09 三星电子株式会社 Nitride semiconductor light emitting device

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