CN108352403A - 一种提高抗单粒子烧毁能力的槽栅mos器件 - Google Patents

一种提高抗单粒子烧毁能力的槽栅mos器件 Download PDF

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CN108352403A
CN108352403A CN201680057865.9A CN201680057865A CN108352403A CN 108352403 A CN108352403 A CN 108352403A CN 201680057865 A CN201680057865 A CN 201680057865A CN 108352403 A CN108352403 A CN 108352403A
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任敏
林育赐
谢驰
苏志恒
李泽宏
张金平
高巍
张波
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University of Electronic Science and Technology of China
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Abstract

一种应用于半导体领域的提高抗单粒子烧毁能力的槽栅MOS器件，该器件在外延层(3)中设置与源极(10)相连的第二导电类型半导体柱(11)和第二导电类型的电流引导区(13)，藉此改变单粒子效应诱发的电子空穴对径迹，避免发生寄生晶体管开启造成的单粒子烧毁现象，提高槽栅MOS器件的抗单粒子烧毁能力。

Description

一种提高抗单粒子烧毁能力的槽栅MOS器件 技术领域
本发明属于半导体技术领域，涉及一种提高抗单粒子烧毁能力的槽栅MOS器件。
背景技术
随着电力电子技术向高频大功率应用领域的快速发展，VDMOS成为电力电子领域中的不可替代的重要器件之一。该结构器件通常采用二次扩散或离子注入技术形成，是多元胞器件，易于集成，功率密度大，且多子导电，频率特性好。但由于功率VDMOS中存在较大的栅源电容，限制了器件的开关速率。同时，由于VDMOS器件内部存在结型场效应晶体管(JFET)，JFET电阻限制了器件内部饱和电流密度。在低压低功耗MOS器件领域，槽栅MOS器件得到迅速发展。槽栅MOS器件结构与VDMOS相比的优点是沟道密度更大，功耗更低，元胞的尺寸可以做的更小。而且，槽栅MOS没有JFET电阻，使得槽栅MOS的单元密度可以随着工艺特征尺寸的降低而迅速提高。
半导体器件的辐照效应是一个复杂的问题，因为不同类型的辐照，对半导体器件的影响是不同的。主要有四种类型的辐照能够对半导体器件产生辐照效应，它们分别是质子、电子、中子和γ射线。对微电子器件产生重要影响且研究最多的因素主要有γ总剂量辐射、γ剂量率辐射、中子辐射及单粒子效应。
槽栅MOS的单粒子效应主要为单粒子烧毁(SEB)。槽栅MOS的N+源、Pbody区和轻掺杂的N-漂移区之间，存在着一个寄生晶体管结构，它们分别构成寄生晶体管的发射区、基区和集电区。一般情况下，寄生晶体管的发射极和基极通过源极金属实现短路，从而对器件的外部特性不产生影响。在辐照环境下，入射粒子沿着入射径迹在槽栅MOS器件内产生大量电子空穴对，在漂移场和扩散双重作用下，形成瞬发电流。关断时，漏极加正电压，源极接地，空穴电流经由Pbody区流向源极，在基区的寄生电阻上产生压降。当压降增大到一定值时，寄生晶体管导通。当MOS晶体管的漏源电压大于击穿电压时，流过晶体管的电流可以进一步反馈，使得耗尽区的电流密度逐渐上升，造成漏-源间二次击穿，如果结温超过允许值，则引起源-漏结的烧毁。因而减小槽栅MOS器件N+源区下方的电阻，即增大P体区浓度是提高器件抗单粒子烧毁的有效方法。考虑对器件阈值的影响，Pbody区浓度不能太大，对减小VDMOS器件N+源区下方的电阻无明显作用，因此传统结构的抗单粒子烧毁能力很差。
发明内容
本发明所要解决的，就是针对上述问题，提出一种提高抗单粒子烧毁能力的槽栅MOS器件。
本发明的技术方案是：一种提高抗单粒子烧毁能力的槽栅MOS器件，其元胞结构包括从下至上依次层叠设置的漏极金属电极1、第一导电类型半导体衬底2、第一导电类型半导体外延层3和源极金属电极10；所述第一导电类型半导体外延层3的上层具有第二导电类型半导体体区6、第一导电类型半导体源区7、第二导电类型半导体体接触区8和槽栅；所述第二导电类型半导体体接触区8位于第一导电类型半导体源区7之间，且第一导电类型半导体源区7和第二导电类型半导体体接触区8的上表面与源极金属电极10连接；所述第二导电类型半导体体区6位于第一导电类型半导体源区7和第二导电类型半导体体接触区8的正下方，第二导电类型半导体体区6的上表面与第一导电类型半导体源区7和第二导电类型半导体体接触区8的下表面连接；所述槽栅位于第二导电类型半导体体区6和第一导电类型半导体源区7的侧面，所述槽栅由栅介质层5和位于栅介质层5中的栅极导电材料4构成；所述栅极导电材料4的上表面与源极金属电极10之间具有隔离介质9；所述隔离介质9的侧面与第一导电类型半导体源区7的侧面连接，所述栅介质层5的侧面与第二导电类型半导体体区6和第一导电类型半导体源区7的侧面连接；所述栅介质层5的结深大于第二导电类型半导体体区6的结深；其特征在于，所述第一导电类型半导体外延层3中还具有第二导电类型半导体柱11和第二导电类型半导体的电流引导区13，所述第二导电类型半导体柱11的上表面与源极金属电极10的下表面连接，第二导电类型半导体柱11的侧面与栅介质层5连接；所述第二导电类型半导体柱11中还具有金属电极12，所述金属电极12与源极金属电极10的下表面连接；所述第二导电类型电流引导区13的侧面与第二导电类型半导体柱11连接，第二导电类型电流引导区13的上表面与栅介质层5的下表面连接，且第二导电类型电流引导区13的横向宽度大于栅介质层5的横向宽度，第二导电类型电流引导区13超出栅介质层5下表面的部分的横向宽度还大于第一导电类型半导体源区7的横向宽度，同时第二导电类型电流引导区13超出栅介质层5下表面的部分向靠近第二导电类型半导体体区6的方向延伸；所述第二导电类型半导体柱11中含有复合中心以降低载流子寿命。
进一步的，所述第一导电类型半导体外延层3中还具有多个电流引导区14，所述电流引导区14位于槽栅的下方，且电流引导区14的侧面与第二导电类型半导体柱11连接。
本发明的有益效果为，相对于传统结构，本发明极大地提高了槽栅MOS的抗单粒子烧毁能力。
附图说明
图1是实施例1所提供的提高抗单粒子烧毁能力的槽栅MOS的剖面结构示意图；
图2是本发明的槽栅MOS和常规槽栅MOS在单粒子入射在位置a时的电子和空穴流向图；(a)为本发明的结构，(b)为常规结构；
图3是本发明的槽栅MOS和常规槽栅MOS在单粒子入射在位置b时的电子和空穴流向图；(a)为本发明的结构，(b)为常规结构；
图4是本发明的槽栅MOS在单粒子入射在位置c时的电子和空穴流向图；
图5是本发明的槽栅MOS在单粒子入射在位置d时的电子和空穴流向图；
图6是实施例2所提供的提高抗单粒子烧毁能力的槽栅MOS的剖面结构示意图；
图7是实施例3所提供的提高抗单粒子烧毁能力的槽栅MOS的剖面结构示意图；
图8是实施例4所提供的提高抗单粒子烧毁能力的槽栅MOS的剖面结构示意图。
具体实施方式
下面结合附图和实施例，详细描述本发明的技术方案：
实施例1
如图1所示，本例的一种提高抗单粒子烧毁能力的槽栅MOS器件，其元胞结构包括从下至上依次层叠设置的漏极金属电极1、第一导电类型半导体衬底2、第一导电类型半导体外延层3和源极金属电极10；所述第一导电类型半导体外延层3的上层具有第二导电类型半导体体区6、第一导电类型半导体源区7、第二导电类型半导体体接触区8和槽栅；所述第二导电类型半导体体接触区8位于第一导电类型半导体源区7之间，且第一导电类型半导体源区7和第二导电类型半导体体接触区8的上表面与源极金属电极10连接；所述第二导电类型半导体体区6位于第一导电类型半导体源区7和第二导电类型半导体体接触区8的正下方，第二导电类型半导体体区6的上表面与第一导电类型半导体源区7和第二导电类型半导体体接触区8的下表面连接；所述槽栅位于第二导电类型半导体体区6和第一导电类型半导体源区7的侧面，所述槽栅由栅介质层5和位于栅介质层5中的栅极导电材料4构成；所述栅极导电材料4的上表面与源极金属电极10之间具有隔离介质9；所述隔离介质9的侧面与第一导电类型半导体源区7的侧面连接，所述栅介质层5的侧面与第二导电类型半导体体区6和第一导电类型半导体源区7的侧面连接；所述栅介质层5的结深大于第二导电类型半导体体区6的结深；其特征在于，所述第一导电类型半导体外延层3中还具有第二导电类型半导体柱 11和第二导电类型半导体的电流引导区13，所述第二导电类型半导体柱11的上表面与源极金属电极10的下表面连接，第二导电类型半导体柱11的侧面与栅介质层5连接；所述第二导电类型半导体柱11中还具有金属电极12，所述金属电极12与源极金属电极10的下表面连接；所述第二导电类型电流引导区13的侧面与第二导电类型半导体柱11连接，第二导电类型电流引导区13的上表面与栅介质层5的下表面连接，且第二导电类型电流引导区13的横向宽度大于栅介质层5的横向宽度，第二导电类型电流引导区13超出栅介质层5下表面的部分的横向宽度还大于第一导电类型半导体源区7的横向宽度，同时第二导电类型电流引导区13超出栅介质层5下表面的部分向靠近第二导电类型半导体体区6的方向延伸；所述第二导电类型半导体柱11中含有复合中心以降低载流子寿命。本例中第一导电类型半导体为N型半导体。
本例的工作原理为：
如图2(b)所示，当单粒子入射在常规槽栅MOS的a位置时，沿着粒子径迹激发出电子空穴对，其中空穴只能通过pbody区流到源极，因此易造成寄生三极管的开启，发生单粒子烧毁。如图2(a)所示，当单粒子入射在本例器件的a位置时，由于与源极相连接的高掺杂的P柱11和空穴电流引导区13的引入，高能粒子激发产生电子-空穴对后，电子被漏极接收，只有少部分的空穴通过P+体区到达源极，大部分空穴在空穴电流引导区13的作用下向低电阻的P柱11移动，由于低电阻的P柱11内具有与源电极10相连的金属电极12，且低电阻的P柱11的载流子寿命较低，因此空穴在P柱11内很快被接收；由于P柱11内不存在n型结构，因此不存在寄生三极管，从而有效避免了寄生三极管的开启。
如图3(b)所示，当单粒子入射在常规槽栅MOS的b位置时，沿着粒子径迹激发出电子空穴对，其中空穴同样只能通过n+源区下的pbody区流到源极，因此易造成寄生三极管的开启，发生单粒子烧毁。如图3(a)所示，当单粒子入射在本例器件的b位置时，由于与源极相连接的高掺杂的P柱11和空穴电流引导区13的引入，高能粒子激发产生电子-空穴对后，电子被漏极接收，几乎所有空穴在空穴电流引导区13的作用下向低电阻的P柱11移动，由于低电阻的P柱11内具有与源电极10相连的金属电极12，且低电阻的P柱11的载流子寿命较低，因此空穴在P柱11内很快被接收；由于P柱11内不存在n型结构，因此不存在寄生三极管，从而有效避免了寄生三极管的开启。
如图4所示当单粒子入射在本例的槽栅MOS的c位置时，几乎全部的空穴都通过空穴电流引导区13和P柱11到达源极，有效的提升了抗单粒子烧毁能力。
如图5所示当单粒子入射在本例的槽栅MOS的d位置时，几乎全部的空穴都通过P柱11到达源极，有效的提升了抗单粒子烧毁能力。
实施例2
如图6所示，本例的结构为在实施例1的基础上，在低电阻的第二导电类型半导体柱11的侧面增加了一条或多条第二导电类型电流引导区14，可以进一步提升抗单粒子烧毁能力。
实施例3
如图7所示，本例的结构为在实施例1的基础上，用高掺杂的第二导电类型半导体区15和含有大量复合中心的第二导电类型半导体区16替换第二导电类型半导体柱11和金属电极12。
实施例4
如图8所示，本例的结构为在实施例1的基础上，用高掺杂的第二导电类型半导体区15和位于其中的含有大量复合中心的第二导电类型半导体区17替换第二导电类型半导体柱11和金属电极12。

Claims (2)

  1. 一种提高抗单粒子烧毁能力的槽栅MOS器件，其元胞结构包括从下至上依次层叠设置的漏极金属电极(1)、第一导电类型半导体衬底(2)、第一导电类型半导体外延层(3)和源极金属电极(10)；所述第一导电类型半导体外延层(3)的上层具有第二导电类型半导体体区(6)、第一导电类型半导体源区(7)、第二导电类型半导体体接触区(8)和槽栅；所述第二导电类型半导体体接触区(8)位于第一导电类型半导体源区(7)之间，且第一导电类型半导体源区(7)和第二导电类型半导体体接触区(8)的上表面与源极金属电极(10)连接；所述第二导电类型半导体体区(6)位于第一导电类型半导体源区(7)和第二导电类型半导体体接触区(8)的正下方，第二导电类型半导体体区(6)的上表面与第一导电类型半导体源区(7)和第二导电类型半导体体接触区(8)的下表面连接；所述槽栅位于第二导电类型半导体体区(6)和第一导电类型半导体源区(7)的侧面，所述槽栅由栅介质层(5)和位于栅介质层(5)中的栅极导电材料(4)构成；所述栅极导电材料(4)的上表面与源极金属电极(10)之间具有隔离介质(9)；所述隔离介质(9)的侧面与第一导电类型半导体源区(7)的侧面连接，所述栅介质层(5)的侧面与第二导电类型半导体体区(6)和第一导电类型半导体源区(7)的侧面连接；所述栅介质层(5)的结深大于第二导电类型半导体体区(6)的结深；其特征在于，所述第一导电类型半导体外延层(3)中还具有第二导电类型半导体柱(11)和第二导电类型电流引导区(13)，所述第二导电类型半导体柱(11)的上表面与源极金属电极(10)的下表面连接，第二导电类型半导体柱(11)的侧面与栅介质层(5)连接；所述第二导电类型半导体柱(11)中还具有金属电极(12)，所述金属电极(12)与源极金属电极(10)的下表面连接；所述第二导电类型半导体的电流引导区(13)的侧面与第二导电类型半导体柱(11)连接，第二导电类型电流引导区(13)的上表面与栅介质层(5)的下表面连接，且第二导电类型电流引导区(13)的横向宽度大于栅介质层(5)的横向宽度，第二导电类型电流引导区(13)超出栅介质层(5)下表面的部分的横向宽度还大于第一导电类型半导体源区(7)的横向宽度，同时第二导电类型电流引导区(13)超出栅介质层(5)下表面的部分向靠近第二导电类型半导体体区(6)的方向延伸；所述第二导电类型半导体柱(11)中含有复合中心以降低载流子寿命。
  2. 根据权利要求1所述的一种提高抗单粒子烧毁能力的槽栅MOS器件，其特征在于，所述第一导电类型半导体外延层(3)中还具有多个电流引导区(14)，所述电流引导区(14)位于槽栅的下方，且电流引导区(14)的侧面与第二导电类型半导体柱(11)连接。
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